Methods of forming a contact structure in a semiconductor device

[0002] This application relies for priority upon Korean Patent Application No. 2000-50108, filed on Aug. 28, 2000, the contents of which are incorporated herein by reference in their entirety.

[0003] The present invention relates to methods of forming a semiconductor device, and more particularly to methods of forming a contact structure in a semiconductor device.

[0004] As the integration density of a semiconductor device increases, the width of each wiring line, and the space between the adjacent wiring lines, become smaller and smaller in size. Given these increasing smaller requirements, a self-aligned contact technique has been proposed in order to increase alignment margins during a photolithography process for forming a contact hole.

[0005] In a Dynamic Random Access Memory (DRAM) device, a bit line and a storage node are electrically connected to active regions of a semiconductor substrate through self-aligned contact pads. The pads penetrate a predetermined region of an interlayer insulating layer and contact the active regions.

[0006] In present methods, an oxide layer containing impurities is widely used as the interlayer insulating layer, since it provides for excellent planarization and electrical insulation. Typically, a BPSG (BoroPhosphoSilicate glass) layer is used as the interlayer insulating layer. The BPSG layer is a silicon oxide layer containing impurities such as boron and phosphorous. The BPSG layer has an excellent reflow characteristic, a low dielectric constant, low stress, and excellent step coverage characteristics as compared to other oxide layer not containing impurities. The BPSG layer is generally reflowed at a temperature of about 850° C. to 1000° C. in order to planarize a top surface thereof.

[0007] Despite the advantages of the BPSG layer, there some problems in the contact structure formed in the BPSG layer. FIGS. 1 and 2 are cross-sectional views of a conventional contact structure using the BPSG layer as an interlayer insulating layer.

[0008] Referring to FIGS. 1 and 2, a trench isolation layer 3 is formed in a semiconductor substrate 1 to define active regions. A drain region 5 and a source region 7 are formed in the active region. A gate pattern 9 is formed, for example, a word line pattern comprising a gate oxide layer 9a,a polysilicon pattern 9b,a metal silicide pattern 9c,and a capping insulating layer pattern 9dwhich are sequentially stacked. The gate pattern 9 contacts the active regions and bridges the drain region 5 and source region 7. The gate pattern 9 is then covered with a conformal silicon nitride layer 11. The silicon nitride layer 11 is then covered with a BPSG layer 13, filling gap regions between the gate patterns 9. The BPSG layer 13 and the silicon nitride layer 11 are selectively etched in a self-aligned manner, to form a pad contact hole exposing the drain region 5. A conductive layer, such as a doped polysilicon layer, is formed in the pad contact hole to form a bit line pad 15. An insulating layer 17 is formed on the resultant structure having the bit line pad 15, and the insulating layer 17 is then patterned to form a bit line contact hole 19 exposing the bit line pad 15. A polycide bit line 21, a composite layer of a polysilicon layer pattern 21aand a metal silicide layer pattern 21b,is formed on the insulating layer 17. The bit line 21 is electrically connected to the bit line pad 15 through the bit line contact hole 19. At this time, the bit line pad 15 is in contact with the BPSG layer 13 and the drain region 5. Accordingly, impurities such as phosphorous within the BPSG layer 13 are diffused into the drain region 5 through the bit line pad 15 during subsequent annealing process. As a result, the concentration profile of the drain region 5 is changed, thereby degrading electrical characteristics of the semiconductor device.

[0009] In order to solve the above problem, Japanese laid-open patent number 6020989 discloses a method of forming a pad. This method comprises forming a contact hole penetrating a portion of a BPSG layer, forming a silicon oxide spacer on a sidewall of the contact hole, and then forming a conductive pad in the contact hole surrounded by the spacer. However, this method also has some problems associated with sidewall spacer formation. Namely, it is very difficult to form the sidewall spacer in a contact hole having a high aspect ratio. In addition, the active region can be damaged during an etch back process employed while forming the sidewall spacer.

[0010] It is an object of the present invention to provide a method of forming a contact structure in a semiconductor device which can prevent impurities in the interlayer insulating layer from being diffused into source/drain region.

[0011] In order to achieve the above object and other features of the present invention, a method of forming a contact structure is provided. The method includes forming an interlayer insulating layer containing impurities on a semiconductor substrate. The interlayer insulating layer is patterned to form a pad contact hole exposing a predetermined portion of the semiconductor substrate. A conductive pad is formed in the pad contact hole. The resultant structure having the conductive pad is subjected to thermal oxidation to form a thermal oxide layer on a top surface of the conductive pad and at an interface between the conductive pad and the interlayer insulating layer.

[0012] Preferably, prior to formation of the interlayer insulating layer, a plurality of insulated interconnection patterns, which are parallel to each other, are formed on the semiconductor substrate, and an etch stop layer is formed on the entire surface of the resultant structure having the interconnection patterns. Herein, the plurality of interconnection patterns are formed by sequentially forming an insulating layer, a conductive layer and a capping layer on the semiconductor substrate and sequentially patterning the capping layer and the conductive layer. Accordingly, each of the interconnection patterns comprises an interconnection and a capping layer pattern stacked on the interconnection. The insulating layer can also be patterned. The interconnection may correspond to a word line of a DRAM device.

[0013] The invention may be understood and its objects will become apparent to those skilled in the art by reference to the accompanying drawings as follows:

[0014] FIG. 1 is a schematic cross-sectional view of a bit line contact structure taken along the direction across word lines of a conventional DRAM;

[0015] FIG. 2 is a schematic cross-sectional view of a bit line contact structure taken along the direction across bit lines of a conventional DRAM;

[0016] FIG. 3 is a top plan view showing a typical DRAM cell array region;

[0017] FIGS. 4A-10A are cross-sectional views taken along line I—I of FIG. 3, at selected stages of a method of forming a contact structure according to the present invention;

[0018] FIGS. 4B-10B are cross-sectional views taken along line II—II of FIG. 3, at selected stages of a method of forming a contact structure according to the present invention; and

[0019] FIGS. 4C-10C are cross-sectional views taken along line III—III of FIG. 3, at selected stages of a method of forming a contact structure according to the present invention.

[0020] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity.

[0021] Hereinafter, the preferred embodiment of the present invention will be fully described with reference to FIG. 3, FIGS. 4A to 10A, FIGS. 4B to 10B, and FIGS. 4C to 10C. In FIGS. 4A to 10A, reference character ‘a’ represents a cell array region and reference character ‘b’ represents a peripheral circuit region.

[0022] FIG. 3 is a typical top plan view of a DRAM cell array region. Referring to FIG. 3, a plurality of T-shaped active regions 46aare defined by the isolation region (not shown). A plurality of parallel word lines 50 cross over the active regions 46a.Each active region 46ais divided into three regions by a pair of word lines 50. A common drain region is located at the active region between the pair of the word lines 50. Two source regions are located at both sides of the common drain region.

[0023] A bit line pad 78ais disposed on the common drain region, and a storage node pad 78bis disposed on each source region. A plurality of bit lines 86 are disposed to cross over the word lines 50. The bit line 86 is electrically connected to the bit line pad 78athrough a bit line contact hole 81. A storage node, namely, a lower electrode of a capacitor is formed on the storage node pad 78b.The storage node is electrically connected to the storage node pad 78bthrough a storage node contact hole 90. The T-shaped active regions 46acan be modified into various configurations, including but not limited to a bar shape or a diagonal shape, in order to realize high integration density.

[0024] Formation of the contact structure shown in FIG. 3 will now be described. For better understanding of the present invention, three cross-sectional views at the same fabrication stages, for example, FIGS. 4A and 4B and 4C will be simultaneously referred to in the discussion.

[0025] Referring now to FIGS. 4A, 4B and 4C, an isolation layer 46 is formed in a predetermined portion of a semiconductor substrate 44 to define active regions. The isolation layer 46 can be formed using a LOCOS (LOCal Oxidation of Silicon) technique or a STI (Shallow Trench Isolation) technique. The STI technique is preferably used in this embodiment. A gate insulating layer 48, a conductive layer, and a capping layer are sequentially formed on the resultant structure having the isolation layer 46. The gate insulating layer 48 is preferably formed of a thermal oxide layer. The conductive layer is formed of a composite layer of a polysilicon and metal silicide, i.e., formed of a polycide layer. Also, the capping layer is preferably formed of a silicon nitride layer. The capping layer and the conductive layer are sequentially patterned to form a plurality of interconnection patterns, i.e., gate patterns 54. Each of the gate patterns 54 comprises a gate electrode 50 and a capping layer pattern 52 which are sequentially stacked. The gate electrode 50 corresponds to a word line. At this time, another gate pattern 54 is also formed in a peripheral circuit region ‘b’.

[0026] Using the gate patterns 54 and the isolation layer 46 as ion-implantation masks, impurities are implanted into the active region to form low concentration impurity regions. Accordingly, three low concentration impurity regions 56 and 58 are formed at each active region in the cell array region ‘a’. Herein, the low concentration impurity region 56 at a central part of the active region acts as a common drain region of a pair of cell transistors, and the two low concentration regions 58 at both sides of the common drain region act as source regions of the pair of cell transistors. In addition, low concentration source/drain regions 60 are also formed in the peripheral circuit region ‘b’.

[0027] Referring now to FIGS. 5A, 5B and 5C, a conformal insulating layer 62 for a spacer is formed on the entire surface of the resultant structure having the low concentration impurity regions 56, 58 and 60. The insulating layer 62 is formed of a material that has an etching selectivity with respect to the subsequent interlayer insulating layer. For example, the insulating layer 62 is preferably formed of a silicon nitride layer. A photosensitive layer, i.e., photoresist layer, is formed on the resultant having the insulating layer 62. A photolithography process is then performed to form a photoresist pattern 64 exposing the insulating layer 62 in the peripheral circuit region ‘b’. Subsequently, the exposed insulating layer 62 is anisotropically etched to form a spacer 66 on sidewalls of the gate patterns 54 in the peripheral circuit region ‘b’. Using the photoresist pattern 64, the gate pattern 54 and the spacer 66 in the peripheral circuit region ‘b’ as implantation masks, impurities are implanted into the peripheral circuit region ‘b’ to form LDD type source/drain regions 60ain the peripheral region ‘b’.

[0028] Referring to FIGS. 6A, 6B and 6C, after removing the photoresist pattern 64, a conformal etch stop layer 68 and an interlayer insulating layer 70 are sequentially formed on an entire surface of the semiconductor substrate 44. Preferably, the etch stop layer 68 is formed of a silicon nitride layer. Also, the interlayer insulating layer 70 is formed of a silicon oxide layer containing impurities. For example, the interlayer insulating layer 70 is formed of a BPSG layer and then is annealed to reflow for planarization. As a result, gap regions between the gate patterns 54 in the cell array region ‘a’ can be completely filled without any void. At this time, the etch stop layer 68 serves as a diffusion barrier layer for preventing impurities in the interlayer insulating layer 70 from being diffused into the low concentration impurity regions 56 and 58 of the cell array region ‘a’ and into the source/drain regions 60aof the peripheral circuit region ‘b’.

[0029] A photoresist pattern 72 is then formed on the interlayer insulating layer 70 to expose selected regions of the cell array region ‘a’. Using the photoresist pattern 72 as an etching mask, the BPSG layer 70 is selectively and anisotropically etched until the etch stop layer 68 is exposed. Subsequently, the exposed etch stop layer 68 and the insulating layer 62 are sequentially and anisotropically etched to form spacers 74 on sidewalls of the gate patterns 54 of the cell array region ‘a’ while concurrently forming pad contact holes 76 exposing the low concentration impurity regions 56 and 58. Most preferably, the pad contact holes 76 are formed by the two step etching process including a first etching step for selectively etching the interlayer insulating layer 70 with respect to the etch stop layer 68 and a second etching step for selectively etching the etch stop layer 68 and the insulating layer 62. Accordingly, the gate electrodes 50 of the cell array region ‘a’, i.e., word lines can be protected from being exposed, even though the misalignment occurs during a photolithography process for forming the photoresist pattern 72. Namely, the pad contact holes 76 are formed through a self-aligned contact process.

[0030] Referring to FIGS. 7A, 7B and 7C, after removing the photoresist pattern 72, a conductive material layer is formed on the resultant to fill the pad contact holes 76. Preferably, the conductive material layer is formed of a doped polysilicon layer. The conductive material layer is then etched back until a top surface of the interlayer insulating layer 70 is exposed, to form conductive pads 78aand 78bin the pad contact holes 76. Herein, the conductive pad 78aformed on the common drain region 56 corresponds to a bit line pad, and the conductive pads 78bformed on the source regions 58 correspond to storage node pads.

[0031] Referring to FIGS. 8A, 8B and 8C, the resultant having the conductive pads 78aand 78bis thermally oxidized in H₂O and O₂ambient gas. The thermal oxidation is preferably performed at a temperature of about 600° C. to 800° C. As a result, a thermal oxide layer 80 is formed on a top surface of the conductive pads 78aand 78band at the interfaces between the conductive pads 78aand 78band the interlayer insulating layer 70. Herein, since the oxygen diffusivity within the interlayer insulating layer 70, i.e., within the BPSG layer is very high, the thermal oxide layer 80 can be very easily formed on the sidewalls of the conductive pads 78aand 78b.On the contrary, the thermal oxide layer 80 is not formed at the interface between the conductive pads 78aand 78band the silicon nitride spacers 74 of the cell array region ‘a’.

[0032] Since the conductive pads 78aand 78bare formed of a doped polysilicon layer, the oxidation rate of the conductive pads 78aand 78bis faster as compared to an undoped polysilicon layer. Accordingly, the sidewalls of the conductive pads 78aand 78bare easily oxidized before the impurities in the interlayer insulating layer 70 are diffused into the conductive pads 78aand 78b.The thermal oxide layer 80 formed on the sidewalls of the conductive pads 78aand 78bacts as a diffusion barrier layer that prevents the impurities in the interlayer insulating layer 70 from being diffused into the conductive pads 78aand 78bduring a subsequent annealing process.

[0033] Referring to FIGS. 9A, 9B and 9C, a photoresist layer is coated on the resultant having the thermal oxide layer 80. The photoresist layer is then patterned through a photolithographic process to form a photoresist pattern (not shown) exposing the thermal oxide layer 80 on the bit line pad 78a.Using the photoresist pattern as an etching mask, the exposed thermal oxide layer 80 is etched to form a bit line contact hole 81 exposing the bit line pad 78a.After removing the photoresist pattern, a conductive layer is formed on the resultant structure. Preferably, the conductive layer is formed of a polycide layer, i.e., a composite layer including a polysilicon layer and a metal silicide layer. The polycide layer is then patterned to form a bit line 86. The bit line 86 comprises a polysilicon pattern 82 covering the bit line contact hole 81 and a metal silicide pattern 84 stacked on the polysilicon pattern 82. At this time, the thermal oxide layer 80 on the storage node pads 78bserves as an etch stop layer during a dry etching process for forming the bit line 86, thereby preventing the storage node pads 78bfrom being etched.

[0034] Referring to FIGS. 10A, 10B and 10C, an insulating layer 88 is formed on the resultant structure having the bit line 86. The insulating layer 88 is formed of a conventional oxide layer. The insulating layer 88 and the thermal oxide layer 80 are sequentially patterned to form storage node contact holes 90 exposing the storage node pads 78b.Though not shown in the figure, storage nodes, which are electrically connected to the storage node pads 78bthrough the storage node contact holes 90, are formed using a conventional technique.

[0035] As described above, according to the present invention, a thermal oxide layer is formed at the interfaces between the conductive pads and the interlayer insulating layer by thermally oxidizing the resultant structure having the conductive pads penetrating the interlayer insulating layer containing impurities. Accordingly, the thermal oxide layer prevents impurities within the interlayer insulating layer from being diffused into the source/drain region through the conductive pad during the subsequent thermal process. As a result, it is possible to suppress the degradation of electrical characteristics of the semiconductor device.

[0036] In addition, according to the present invention, the thermal oxide layer is also formed on the top surface of the storage node pad as well as on the top surface of the bit line pad. Accordingly, there is no need to form an extra insulating layer for electrical isolation between the bit line and the storage node pads. As a result, the manufacturing process can be simplified.

[0037] Furthermore, according to the present invention, the thin etch stop layer is interposed between the source/drain regions of the peripheral circuit region and the interlayer insulating layer. Accordingly, it is possible to prevent the impurities in the interlayer insulating layer from being diffused out into the source/drain region.