Method for forming element isolating region

[0002] 1. Field of the Invention

[0003] The invention relates to a method for forming an element isolating region in a semiconductor device and, more particularly to, a method for forming a Shallow Trench Isolation (STI) by filling with an insulator film a shallow trench in a surface of a semiconductor substrate.

[0004] The present application claims priority of Japanese Patent Application No. 2000-078773 filed on Mar. 21, 2000, which is hereby incorporated by reference.

[0005] 2. Description of the Related Art

[0006] With improvements in fine patterning of semiconductor elements formed in a semiconductor silicon substrate, it has been difficult for a method for forming element isolating regions by use of a conventional LOCal Oxidation of Silicon (LOCOS) method to form accurately an active region having a width in an order of 0.1 μm or less, thus being mainly replaced by an STI method.

[0007] FIGS. 7A to 7E are schematically cross-sectional views for illustrating conventional steps of forming an element isolating region. As can be seen from FIGS. 7A to 7E, a conventional STI is formed as follows.

[0008] First, a pad oxide film 302 is formed on a silicon substrate 301 by thermal oxidation. A silicon nitride film 303 is formed which covers the pad oxide film 302. The portions of the silicon nitride film 303 and the pad oxide film 302 which exist on a formation-reserved element isolating region are patterned sequentially by anisotropic etching. By conducting anisotropic etching on the silicon substrate 301 using the silicon nitride film 303 as a mask, shallow trenches 305 are formed in the formation-reserved element isolating region on the surface of the silicon substrate 301.

[0009] Next, a thermal oxide film 307 is formed on the surface of the trenches 305 by thermal oxidation.

[0010] High-Density Plasma-Enhanced CVD (HD-PECVD) accompanied by bias sputtering is conducted to form a silicon oxide film 311 throughout on the surface to a predetermined film thickness to thereby fill and cover the trenches 305 completely with the silicon oxide film 311 (see FIG. 7A).

[0011] Next, Chemical Mechanical Polishing (CMP) is conducted (using the silicon nitride film 303 as a stopper) on the silicon oxide film 311 until an upper surface of the silicon nitride film 303 is exposed, to leave a silicon oxide film 311ain the trenches 305 (see FIG. 7B).

[0012] Next, etching-back is conducted on the silicon oxide film 311ausing buffered hydrofluoric acid (BHF) to leave a silicon oxide film 311bin the trenches 305. At this point in time, an upper surface of the silicon oxide film 311broughly agrees in level with an upper surface of the pad oxide film 302 in level (see FIG. 7C).

[0013] Next, for example, wet etching by use of hot phosphoric acid is conducted on the silicon nitride film 303 to remove it (see FIG. 7D).

[0014] Subsequently, the silicon oxide film 311band the pad oxide film 302 are removed by wet etching by use of hydrofluoric acid (e.g., buffered hydrofluoric acid). With this, portions of a surface of the silicon substrate 301 which are expected to be an active region (element forming region) are exposed to leave a silicon oxide film 311c in the trenches 305, thus completing the conventional STI (see FIG. 7E).

[0015] The above-mentioned conventional STI forming method, however, may generate a fine scratch (hereinafter called micro-scratch) 315 in the surface of the silicon oxide film 311aas a result of CMP conducted thereon (see FIG. 7B). The micro-scratch 315 may sometimes measure about 0.1 μm to 100 μm in length.

[0016] Further, since after the trenches 305 are formed it is difficult to avoid etching the pad oxide film 302 during cleaning before the thermal oxide film 307 is formed, an under-cut is liable to be formed at the ends of the silicon nitride film 303. Accordingly, when the silicon oxide film 311 is formed, density of the silicon oxide film 311 may decrease in vicinity of a lower edge of an end of this silicon nitride film 303, thus further generating a void (not shown).

[0017] If the silicon oxide film 311ais anisotropically etched with buffered hydrofluoric acid with a presence of the micro-scratch 315, the micro-scratch 315 expands anisotropically. When, in this case, the micro-scratch 315 comes near the lower edge of the end of the above-mentioned silicon nitride film 303, etching of the silicon oxide film 311 rapidly spreads from there as a center to all around a belonging element forming region, to form a notch shape (hereinafter called debot 316) in the silicon oxide film 311baround that element forming region (see FIG. 7C). This debot 316 further develops to provide a debot 316aduring wet-etching in which the silicon oxide film 311cis left (see FIG. 7E).

[0018] Thus, the conventional STI forming method suffers from a problem that width of a specific element forming region becomes larger than its design value all over its peripheries. If a semiconductor device has MOS transistors therein, such a transistor MOS may be formed that has, for example, an extremely increased reverse narrow channel effect, thus deteriorating the electric characteristics of the MOS transistor. Also, in patterning of gate electrodes in post-steps, etch residues of a conductive film may be induced at the debot 316a.

[0019] In view of the above, it is an object of the present invention to provide a method for forming an STI to suppress an effective expansion of an element forming region. It is another object of the invention to provide a method for forming the STI easy to suppress an increase in a reverse channel effect, deterioration of electric characteristics, and induction of etch residues of gate electrodes in a post-step in some transistors in a semiconductor device containing MOS transistors. It is further another object of the invention to provide a method for forming the STI easy to suppress an occurrence of the debot even when the micro-scratch is present.

[0020] According to a first aspect of the present invention, there is provided a method for forming an element isolating region, including the steps of:

[0021] forming a pad oxide film on a surface of a silicon substrate by thermal oxidation and forming a silicon nitride film which covers the pad oxide film and then conducting anisotropic etching sequentially on portions of the silicon nitride film and the pad oxide film which exist on a formation-reserved element isolating region to then conduct anisotropic etching using the silicon nitride film as a mask in order to form a trench in a surface of the silicon substrate, thus forming a first silicon oxide film throughout on the surface by High-Density Plasma-Enhanced CVD (HD-PECVD) accompanied by bias sputtering;

[0022] conducting Chemical Mechanical Polishing (CMP) on the first silicon oxide film until a surface of the silicon nitride film is exposed;

[0023] forming by spin coating or liquid-phase deposition a second silicon oxide film which covers a surface of the silicon nitride film and a surface of the first silicon oxide film to thereby conduct heat treatment in an oxygen atmosphere, serving also to refine the second silicon oxide film;

[0024] conducting such anisotropic etching using an etching gas that an etching rate for the silicon oxide film may be equal to an etching rate for the silicon nitride film to thereby remove the second silicon oxide film in order to remove the silicon nitride film and the first silicon oxide film; and

[0025] remove by wet etching the pad oxide film, and the first silicon oxide film until at least the surface of the silicon substrate is exposed.

[0026] In the foregoing first aspect, a preferable mode is one wherein the second silicon oxide film is formed by spin coating and consists of an inorganic SOG (Spin-On-Glass) film made of silicon hydride sesqui-oxide (HSiO_3/2) n as a material.

[0027] According to a second aspect of the present invention, there is provided a method for forming an element isolating region, including the steps of:

[0028] forming a pad oxide film on a surface of a silicon substrate by thermal oxidation and forming a silicon nitride film which covers the pad oxide film and then conducting anisotropic etching sequentially on portions of the silicon nitride film and the pad oxide film which exist on a formation-reserved element isolating region to conduct anisotropic etching using the silicon nitride film as a mask in order to form a trench in a surface of the silicon substrate, thus forming a first silicon oxide film throughout on the surface by HD-PECVD accompanied by bias sputtering;

[0029] conducting CMP on the first silicon oxide film until a surface of the silicon nitride film is exposed;

[0030] forming by spin coating or LPD a second silicon oxide film which covers a surface of the silicon nitride film and a surface of the first silicon oxide film to thereby conduct heat treatment in an oxygen atmosphere, serving also to refine the second silicon oxide film;

[0031] conducting such anisotropic etching using an etching gas that an etching rate for the silicon oxide film may be equal to an etching rate for the silicon nitride film to thereby remove the second silicon oxide film in order to remove the silicon nitride film and the first silicon oxide film partially;

[0032] remove a residue of the silicon nitride film by wet etching; and

[0033] removing by wet etching the residue of the second silicon oxide film, the pad oxide film and the first silicon oxide film until the surface of the silicon substrate is exposed. In the foregoing second aspect, a preferable mode is one wherein the second silicon oxide film is formed by spin coating and consists of an organic SOG film or an inorganic SOG film made of silicon hydride sesqui-oxide.

[0034] According to a third aspect of the present invention, there is provided a method for forming an element isolating region, including the steps of:

[0035] forming a pad oxide film on a surface of silicon substrate by thermal oxidation and forming a silicon nitride film which covers the pad oxide film and then conducting anisotropic etching sequentially on portions of the silicon nitride film and the pad oxide film which exist on a formation-reserved element isolating region to conduct anisotropic etching using the silicon nitride film as a mask in order to form a trench in the surface of the silicon substrate, thus forming a first silicon oxide film throughout on the surface by HD-PECVD accompanied by bias sputtering;

[0036] conducting CMP on the first silicon oxide film until a surface of the silicon nitride film is exposed;

[0037] forming by spin coating or LPD a second silicon oxide film which covers a surface of the silicon nitride film and a surface of the silicon oxide film to thereby conduct heat treatment in an oxygen atmosphere, serving also to refine the second silicon oxide film;

[0038] conducting such anisotropic etching using an etching gas that an etching rate for the silicon oxide may be equal to an etching rate for silicon nitride film to thereby remove the second silicon oxide film in order to remove the silicon nitride film and the first silicon oxide film partially;

[0039] remove a residue of the silicon nitride film by wet etching; and

[0040] removing by wet etching the pad oxide film and the first silicon oxide film until the surface of the silicon substrate is exposed.

[0041] In the foregoing third aspect, a preferable mode is one wherein the second silicon oxide film is formed by spin coating and consists of an organic SOG film or an inorganic SOG film made of silicon hydride sesqui-oxide as a material. According to a fourth aspect of the present invention, there is provided a method for forming an element isolating region, including the steps of:

[0042] forming a pad oxide film on a surface of a silicon substrate by thermal oxidation and forming a silicon nitride film which covers the pad oxide film and then conducting anisotropic etching sequentially on portions of the silicon nitride film and the pad oxide film which exist on a formation-reserved element isolating region to conduct anisotropic etching using the silicon nitride film as a mask in order to form a trench in the surface of the silicon substrate, thus forming a first silicon oxide film throughout on the surface by HD-PECVD accompanied by bias sputtering;

[0043] conducting CMP on the first silicon oxide film until a surface of the silicon nitride film is exposed;

[0044] forming by spin coating or LPD a second silicon oxide film which covers the silicon nitride film and the first silicon oxide film to thereby conduct heat treatment, serving also to refine the second silicon oxide film;

[0045] conducting such anisotropic etching using an etching gas that an etching rate for the silicon oxide film may be higher than an etching rate for the silicon nitride film to thereby remove the second silicon oxide film in order to remove the silicon nitride film partially at the same time as removing the first silicon oxide film until a surface of the first silicon oxide film is equal to a surface of the pad oxide film in level;

[0046] removing a residue of the silicon nitride film by wet etching; and

[0047] removing by wet etching the second oxide film, the pad oxide film, and the first silicon oxide film until the surface of the silicon substrate is exposed.

[0048] In the foregoing fourth aspect, a preferable mode is one wherein the second silicon oxide film is formed by spin coating and consists of an organic SOG or an inorganic SOG film made of silicon hydride sesqui-oxide as a material. According to a fifth aspect of the present invention, there is provided a method for forming an element isolating region, including the steps of:

[0049] forming a pad oxide film on a surface of a silicon substrate by thermal oxidation and forming a silicon nitride film which covers the pad oxide film and then conducting anisotropic etching sequentially on portions of the silicon nitride film and the pad oxide film which exist on a formation-reserved element isolating region to conduct anisotropic etching using the silicon nitride film as a mask in order to form a trench in the surface of the silicon substrate, thus forming a first silicon oxide film which has a film thickness smaller than ½ of a minimum width of the trench by Low Pressure CVD (LPCVD) throughout on the surface;

[0050] forming by spin coating or LPD a second silicon oxide film which covers a surface of the first silicon oxide film to thereby conduct first heat treatment in an oxygen atmosphere, serving also to refine the second silicon oxide film;

[0051] conducting CMP on the second and first silicon oxide films until a surface of the silicon nitride film is exposed;

[0052] forming by spin coating or LPD a third silicon oxide film which covers the silicon nitride film and the first and second silicon oxide films to thereby conduct second heat treatment in an oxygen atmosphere, serving also to refine the third silicon oxide film;

[0053] conducting such anisotropic etching using an etching gas that an etching rate for the silicon oxide film may be equal to an etching rate for the silicon nitride film to remove the third silicon oxide film and also remove the silicon nitride film, the second silicon oxide film, and the first silicon oxide film until the silicon nitride film is removed completely; and

[0054] removing by wet etching the pad oxide film, the second silicon oxide film, and the first silicon oxide film until at least the surface of the silicon substrate is exposed. According to a sixth aspect of the present invention, there is provided a method for forming an element isolating region, including the steps of:

[0055] forming a pad oxide film on a surface of a silicon substrate by thermal oxidation and forming a silicon nitride film which covers the pad oxide film and then conducting anisotropic etching sequentially on portions of the silicon nitride film and the pad oxide film which exist on a formation-reserved element isolating region to conduct anisotropic etching using the silicon nitride film as a mask in order to form a trench in the surface of the silicon substrate, thus forming a first silicon oxide film having a film thickness smaller than ½ of a minimum width of the trench throughout on the surface by LPCVD.

[0056] forming by spin coating or LPD a second silicon oxide which covers a surface of the first silicon oxide film to thereby conduct first heat treatment in an oxygen atmosphere, serving also to refine the second silicon oxide film;

[0057] conducting CMP on the second and first silicon oxide films until a surface of the silicon nitride film is exposed;

[0058] forming by spin coating or LPD a third silicon oxide film which covers the silicon nitride film and the first and second silicon oxide films to thereby conduct second heat treatment, serving also to refine the third silicon oxide film;

[0059] conducting such anisotropic etching using an etching gas that an etching rate for the silicon oxide film may be equal to an etching rate for the silicon nitride film to remove the third silicon oxide film and also remove the silicon nitride film, the second silicon oxide film, and the first silicon oxide film so as to leave a residue of the silicon nitride film partially;

[0060] removing the residue of the silicon nitride film by wet etching; and

[0061] removing by wet etching the residue of the third silicon oxide film, the pad oxide film, the second silicon oxide film, and the first silicon oxide film until the surface of the silicon substrate is exposed.

[0062] According to a seventh aspect of the present invention, there is provided a method for forming an element isolating region, including the steps of:

[0063] forming a pad oxide film on a surface of a silicon substrate by thermal oxidation and forming a silicon nitride film which covers the pad oxide film and then conducting anisotropic etching sequentially on portions of the silicon nitride film and the pad oxide film which exist on a formation-reserved element isolating region to conduct anisotropic etching using the silicon nitride film in order to form a trench in the surface of the silicon substrate, thus forming a first silicon oxide film having a film thickness smaller than ½ of a minimum width of the trench throughout on the surface by LPCVD;

[0064] forming by spin coating or LPD a second silicon oxide film which covers a surface of the first silicon oxide film to thereby conduct first heat treatment in an oxygen atmosphere, serving also to refine the second silicon oxide film;

[0065] conducting CMP on the second and first silicon oxide films until a surface of the silicon nitride film is exposed;

[0066] forming by spin coating or LPD a third silicon oxide film which covers surfaces of the silicon nitride film and the first and second silicon oxide films to thereby conduct second heat treatment in an oxygen atmosphere, serving also to refine the third silicon oxide film;

[0067] conducting anisotropic etching using such an etching gas that an etching rate for the silicon oxide film may be higher than an etching rate for the silicon nitride film to remove the third silicon oxide film, thus removing the silicon nitride film, the second silicon oxide film, and the first silicon oxide film partially;

[0068] removing a residue of the silicon nitride film by wet etching; and

[0069] removing by wet etching the pad oxide film, the second silicon oxide film, and the first silicon oxide film until the surface of the silicon substrate is exposed.

[0070] According to a eighth aspect of the present invention, there is provided a method for forming an element isolating region, including the steps of:

[0071] forming a pad oxide film on a surface of a silicon substrate by thermal oxidation and forming a silicon nitride film which covers the pad oxide film and then conducting anisotropic etching sequentially on portions of the silicon nitride film and the pad oxide film which exist on a formation-reserved element isolating region to conduct anisotropic etching using the silicon nitride film as a mask in order to form a trench in the surface of the silicon substrate, thus forming a first silicon oxide film having a film thickness smaller than ½ of a minimum width of the trench throughout on the surface by LPCVD;

[0072] forming by spin coating or LPD a second silicon oxide film which covers a surface of the first silicon oxide film to thereby conduct first heat treatment in an oxygen atmosphere, serving also to refine the second silicon oxide film;

[0073] conducting CMP on the second and first silicon oxide films until a surface of the silicon nitride film is exposed;

[0074] forming by spin coating or LPD a third silicon oxide film which covers surfaces of the silicon nitride film and the first and second silicon oxide films to thereby conduct second heat treatment, serving also to refine the third silicon oxide film;

[0075] conducting such anisotropic etching using an etching gas that an etching rate for the silicon oxide film may be higher than an etching rate for the silicon nitride film to remove the third silicon oxide film and remove the silicon nitride film partially and also remove the second and first silicon oxide films until a surface of the second silicon oxide film and an upper edge surface of the first silicon oxide film is equal to a surface of the pad oxide film in level;

[0076] removing a residue of the silicon nitride film by wet etching; and

[0077] removing by wet etching the third oxide film, the pad oxide film, the second silicon oxide film, and the first silicon oxide film until the surface of the silicon substrate is exposed.

[0078] With the above configurations, the silicon nitride film is used as the mask to form the trenches, on the surface of which is formed the thermal-oxidized film to thereby fill the trenches completely in order to form buried silicon oxide film, which then undergoes CMP using the silicon nitride film as the stopper, after which the organic SOG film or the inorganic SOG film made of silicon hydride sesqui-oxide as the material undergoes spin coating or LPD to form covering silicon oxide film to thereby cover the surface of the above-mentioned buried silicon oxide film, thus effectively repairing the micro-scratch generated in the surface of the buried silicon oxide film during the CMP step.

[0079] Accordingly, when heat treatment is conducted in an oxidation atmosphere for refinement also, a debot can be prevented from occurring even if wet etching is conducted after anisotropic etching conducted on both of the silicon oxide film and the silicon nitride film.

[0080] As a result, the invention makes it possible to easily avoid occurrence of the debot even in presence of a micro-scratch and easily suppress the effective expansion of the element forming region. Also, in a semiconductor device containing MOS transistors, the invention makes it possible to easily suppress an increase in the reverse narrow channel effect, deterioration of electric characteristics, and induction of etch residues of gate electrodes in post-steps.

[0081] The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings in which:

[0082] FIGS. 1A to 1F are schematic cross-sectional views for showing element-isolating region forming steps according to a first embodiment of the present invention;

[0083] FIGS. 2A to 2E are schematic cross-sectional views for showing element-isolating region forming steps according to a second embodiment of the present invention;

[0084] FIGS. 3A to 3E are schematic cross-sectional views for showing element-isolating region forming steps according to a third embodiment of the present invention;

[0085] FIGS. 4A, 4B and 4C are schematic cross-sectional views for showing element-isolating region forming steps according to a fourth embodiment of the present invention;

[0086] FIGS. 5A, 5B and 5C are schematic cross-sectional views for showing further element-isolating region forming steps according to the fourth embodiment of the present invention;

[0087] FIGS. 6A and 6B are schematic cross-sectional views for showing still further element-isolating region forming steps according to the fourth embodiment of the present invention; and

[0088] FIGS. 7A to 7E are schematic cross-sectional views for showing conventional STI forming steps, illustrating its problems.

[0089] Best modes for carrying out the present invention will be described in further detail using various embodiments with reference to the accompanying drawings.

[0090] According to first, second, and third embodiments of the present invention, an STI trench (surface of which is covered by a thermal oxide film) is filled with a silicon oxide film formed by HD-PRCVD accompanied by bias sputtering. Also, according to the fourth embodiment of the present invention, the STI trench (surface of which is covered by a thermal oxide film) is filled with a first silicon oxide film formed by LPCVD and a second silicon oxide film formed by LPD or spin coating.

[0091] FIGS. 1A to 1F are schematic cross-sectional views for showing element-isolating region forming steps according to a first embodiment of the present invention;

[0092] The following will describe a method for forming an STI according to the first embodiment with reference to FIGS. 1A to 1F.

[0093] First, a pad oxide film 102 with a film thickness of, for example, about 20 nm is formed on a surface of a silicon substrate 101 by thermal oxidation. Then, a silicon nitride film 103 with a film thickness of, for example, about 200 nm is formed on the pad oxide film 102 by CVD. The silicon nitride film 103 and the pad oxide film 102 are sequentially patterned anisotropically on a formation-reserved region of an element isolating region.

[0094] Next, trenches 105 are formed by anisotropic etching using the silicon nitride film 103 as a mask. Trenches 105 have their minimum width of, for example, about 0.25 μm, a minimum inter-spacing of, for example, about 0.25 μm, and a depth of about 0.3-0.4 μm. This anisotropic etching employs HBr (+O₂) or Cl₂(+O₂) as its etching gas.

[0095] Next, on a surface of trenches 105 is formed a thermal-oxidized film 107 with a film thickness of up to about 20 nm by thermal oxidation at a temperature of 900-950° C. When the thermal-oxidized film 107 is thus formed, an upper edge of the trenches 105 is rounded off. Subsequently, a first silicon oxide film 111 with a film thickness of, for example, about 600 nm is formed by HD-PECVD (e.g., ECR) accompanied by bias sputtering. This first silicon oxide film 111 completely fills the trenches 105 (see FIG. 1A).

[0096] Next, CMP is conducted on the first silicon oxide film 111 using the silicon nitride film 103 as a stopper, to leave a silicon oxide film 111a. In this embodiment also, when CMP is conducted, a micro-scratch 115 is generated in a surface of the silicon oxide film 111a(see FIG. 1B).

[0097] Note here that in this embodiment, it is not preferable to employ a silicon oxide film by use of LPCVD in place of the first silicon oxide film 111 thus formed. This is because if the silicon oxide film by use of LPCVD has a large film thickness, it has a key-hole shaped void (key-hole void) formed at its trench, which cannot be eliminated by CMP, thus contributing to a variety of troubles. If this silicon oxide film by use of LPCVD has a small film thickness, on the other hand, a portion which fills the trenches 105 have a recess in this silicon oxide film. By the above-mentioned CMP processing, however, slurry residues in this recess cannot easily be removed, which is not preferably from a viewpoint of reliability.

[0098] Next, a second silicon oxide film 121aconsisting of an organic SOG (Spin-On-Glass) film is formed by spin coating to thereby cover the surface of the silicon oxide film 111aincluding the silicon nitride film 103. The second silicon oxide film 121ahas a film thickness of, for example, about 280 nm and preferably about 0.1-0.4 μm. Since a starting material for forming the silicon oxide film 121ais in a liquid state, in contrast to a case of using CVD or PVD such as sputtering, the micro-scratch 115 formed in the surface of the silicon oxide film 111ahas also part of this second silicon oxide film 121aformed therein (see FIG. 1C). This second silicon oxide film 121acomes in, for example, an organic SOG film made of a material containing, for example, a Si—R (R: alkyl group).

[0099] Subsequently, heat treatment is conducted in a dry-O₂atmosphere at a temperature of 900-950° C. to transform the second silicon oxide film 121aand silicon oxide film 111ainto a silicon oxide film 121aaand silicon oxide film 121aaarespectively. This heat treatment makes the second silicon oxide film 121afiner and sufficiently dehydrates it and liberates R groups therefrom (see FIG. 1D). It is not preferable to conduct this heat treatment in a steam atmosphere in this embodiment because the surface of the trenches 105 are also oxidized. Prior to this heat treatment, cure processing may be conducted in a nitrogen atmosphere at a temperature of 500-600° C. in order to remove the R groups from the silicon oxide film 111a.

[0100] Note here that it is not preferable to employ a typical silica-based inorganic SOG film made of a material containing a Si—OH (silanol) bond, because it encounters drastic volumetric shrinkage during the above-mentioned heat treatment, thus being liable to generate a lot of cracks.

[0101] Next, an etching gas is used which is made up of trifluoro-methane (CHF₃) with a flow rate of 3.3×10⁻²L/min, tetrafluoro-methane (CF₄) with a flow rate of 2.7×10⁻²L/min, argon (Ar) with a flow rate of 5×10⁻³L/min, and oxygen (O₂) with a flow rate of 1×10⁻³L/min, to conduct anisotropic etching by use of a leaf-type RIE (Reactive Ion Etching) apparatus under conditions of a pressure of 10 Pa and a high-frequency source power of 1000 W (at a frequency of 13.56 MHz). In this anisotropic etching, an etching rate for the silicon oxide film is roughly equal to that for the silicon nitride film 103. This anisotropic etching is continued until the silicon nitride film 103 is removed to thus remove the silicon oxide film 121aa, leaving the silicon oxide film 111aaas a silicon oxide film 111ab. At this point in time, an upper surface of the silicon oxide film 111abroughly agrees with a surface of the pad oxide film 102 in level. In this embodiment, this anisotropic etching is stopped from removing also the pad oxide film 102 in order not to damage by RIE a surface of portions of the silicon substrate 101 which are reserved as an element forming region (see FIG. 1E).

[0102] In this anisotropic etching, an emission spectrum (with a wavelength of 483 nm) of carbon monoxide (CO) generated during the etching of the silicon oxide film is used by a monitor. Also, when an emission amount of the emission spectrum of CO starts to decrease, etching is terminated of the silicon oxide film 121aaand, when it starts to increase again, etching is terminated of the silicon nitride film 103, thus stopping this anisotropic etching.

[0103] Subsequently, the pad oxide film 102 is removed using a buffered hydrofluoric acid (or diluted hydrofluoric acid) until the surface of the silicon substrate 101 is exposed. At the same time, the thermal-oxidized film 107 and the silicon oxide film 111abare also removed partially, to thereby provide a thermal-oxidized film 107aand a silicon oxide film lilac respectively. At this point in time, an upper edge of the thermal-oxidized film 107 roughly agrees with an upper surface of the silicon oxide film 107ain level. With this, the trenches 105 are filled by the silicon oxide film 111acwith the thermal-oxidized film 107 therebetween, thus completing the STI according to this embodiment (see FIG. 1F).

[0104] With the first embodiment, even if the micro-scratch 115 has already been formed on the surface of the silicon oxide film 111aimmediately after CMP, the second silicon oxide film 121ais formed to completely fill a void of the micro-scratch 115, so that the micro-scratch 115 can be considered to have disappeared effectively. When the silicon oxide film 111aundergoes anisotropic etching or wet etching to provide the silicon oxide film 111abor the silicon oxide film 111ac, the micro-scratch 115 does not expand anisotropically. Accordingly, even if the above-mentioned micro-void is present near a lower edge of the end of the silicon nitride film 103, occurrence of a debot is suppressed.

[0105] As a result, the element isolating region can be easily regulated from expanding effectively. Also, in a semiconductor device having MOS transistors therein, it is possible to easily suppress increases in reverse narrow channel effect, deterioration in electric characteristics, and induction of etch residue of gate electrodes in post-steps.

[0106] FIGS. 2A to 2E are schematic cross-sectional views for showing element-isolating region forming steps according to a second embodiment of the present invention;

[0107] The following will describe a method for forming an STI according to the second embodiment with reference to FIGS. 2A to 2E.

[0108] First, like in the case of the above-mentioned first embodiment, a pad oxide film 102 is formed by thermal oxidation on a surface of a silicon substrate 101 and then a silicon nitride film 103 is formed by CVD on a surface of the pad oxide film 102. Portions of the silicon nitride film 103 and the pad oxide film 102 which exist on a formation-reserved element isolating region are sequentially patterned by anisotropic etching. Trenches 105 are formed by anisotropic etching using the silicon nitride film 103 as a mask. On a surface of the trenches 105 is formed a thermal-oxidized film 107. The first silicon oxide film (not shown) having a film thickness of, for example, about 600 nm is formed by HD-PECVD accompanied by bias sputtering. Subsequently, CMP is conducted on the above-mentioned first silicon oxide film using the silicon nitride film 103 as a stopper to thereby leave the first silicon oxide film 111b. By this CMP processing, a micro-scratch 115 is generated in the surface of the first silicon oxide film 111b.

[0109] Next, a second silicon oxide film 121bmade of an organic SOG film containing silicon hydride sesqui-oxide (HSiO_3/2) n (where n is an arbitrary natural number) as a material is formed by spin coating to thereby cover the first surface of the silicon oxide film 111bincluding the silicon nitride film 103. The second silicon oxide film 121bhas preferably a film thickness of about 0.1-0.4 μm. Since a starting material for forming the second silicon oxide film 121bis in a liquid state, the micro-scratch 115 formed in the surface of the first silicon oxide film 111balso has part of the second silicon oxide film 121bformed therein (see FIG. 2A).

[0110] Subsequently, heat treatment is conducted in a dry-O₂atmosphere at a temperature of 900-950° C. to thereby transform the second silicon oxide film 121band the first silicon oxide film 111binto a silicon oxide film 121baand silicon oxide film 111barespectively. This heat treatment makes the second silicon oxide film 121bfiner and sufficiently dehydrates it and liberates R groups therefrom (see FIG. 2B). Prior to this heat treatment, cure processing may be conducted in a nitride atmosphere at a temperature of 500-600° C. in order to remove water contents from a silicon oxide film 121bbeforehand.

[0111] In contrast to typical inorganic SOG films made of a material containing silanol bonds, the above-mentioned second silicon oxide film 121bencounters little volumetric shrinkage, actually less than the silicon oxide film 121a(FIG. 1C) in the above-mentioned first embodiment, and also little crack generation.

[0112] Next, such anisotropic etching is conducted that an etching rate for the silicon oxide film and that for the silicon nitride film 103 used in the above-mentioned first embodiment may be roughly equal to each other. This anisotropic etching is actually conducted not to remove the silicon nitride film 103 completely, thus leaving a silicon nitride film 103band a silicon oxide film 111bbrespectively. An upper surface of the silicon nitride film 103band that of the silicon oxide film 111bbroughly agree with each other, with the silicon nitride film 103bhaving a film thickness of, for example, about 10 nm (see FIG. 2C).

[0113] Next, wet etching by use of hot phosphoric acid is conducted on the silicon nitride film 103bto remove it locally, thus exposing a surface of the pad oxide film 102 (see FIG. 2D).

[0114] Subsequently, the pad oxide film 102 is removed by buffered hydrofluoric acid (or diluted hydrofluoric acid) until a surface of the silicon substrate 101 is exposed. At a same time, the thermal-oxidized film 107 and the silicon oxide film 111bbare also removed partially to thereby provide a thermal-oxidized film 107band a silicon oxide film 111bcrespectively. By this etching, it is not difficult to keep a level difference between an upper surface of the silicon oxide film 111bcand a surface of the silicon substrate 101 within ±5 nm. In fact, at this point in time an upper edge of the thermal-oxidized film 107bhas become lower than the upper surface of the silicon oxide film 111bcby about 10 nm in level. With this, the trenches 105 are filled by the silicon oxide film 111bcwith the thermal-oxidized film 107btherebetween to thus complete the STI according to the second embodiment of the present invention (see FIG. 2E).

[0115] With the second embodiment, in anisotropic etching for etching the silicon nitride film and silicon oxide films roughly at a same etching rate, the silicon nitride film 103 is not completely removed to thereby leave its residues, thus avoiding the pad oxide film 102 from being subjected to this anisotropic etching.

[0116] Accordingly, controllability of a series of etching steps up to removing of the pad oxide film 102 is more superior in the second embodiment than in the above-mentioned first embodiment.

[0117] Also, in the second embodiment, the second silicon oxide film 121bis not limited to an inorganic SOG film made of such a material as silicon hydride sesqui-oxide but may be an organic SOG film like in the case of the above-mentioned first embodiment. Similarly, the second silicon oxide film 121bemployed in the above-mentioned first embodiment maybe an inorganic SOG film made of such a material as silicon hydride sesqui-oxide.

[0118] FIGS. 3A to 3E are schematic cross-sectional views for showing element-isolating region forming steps according to a third embodiment of the present invention;

[0119] The following will describe a method for forming an STI according to the third embodiment with reference to FIGS. 3A to 3E.

[0120] First, like in cases of the above-mentioned first embodiment and second embodiment, a pad oxide film 102 is formed on a surface of a silicon substrate 101 by thermal oxidation and then a silicon nitride film 103 is formed by CVD on a surface of the pad oxide film 102. Portions of the silicon nitride film 103 and the pad oxide film 102 which exit on a formation-reserved element isolating region are patterns by anisotropic etching respectively. Anisotropic etching by use of the silicon nitride film 103 as a mask is conducted to form trenches 105. On a surface of trenches 105 is formed a thermal-oxidized film 107. A first silicon oxide film (not shown) having a film thickness of, for example, about 600 nm is formed by HD-PECVD accompanied by bias sputtering. Subsequently, CMP is conducted on the above-mentioned first silicon oxide film using the silicon nitride film 103 as a stopper to thereby leave a first silicon oxide film 111c. By this CMP processing, the micro-scratch 115 is generated in a surface of the first silicon oxide film 111c.

[0121] Next, liquid-phase deposition (LPD) is conducted to form a second silicon oxide film 121cto thereby cover a surface of the first silicon oxide film 111cand the silicon nitride film 103. An solution used in this LPD processing is prepared, as disclosed in Japanese Patent Application Laid-open No. Hei 6-61343, for example by adding 10-50 ml/h of a 0.6 wt % solution of ortho-acetic acid (H₃BO₃) to 1L of a 40 wt % solution of hexa-fluoro silicic acid (H₂SiF₆). The second silicon oxide film 121chas preferably a thickness of about 0.1-0.4 μm. Since the second silicon oxide film 121cis formed in a liquid, the micro-scratch 115 formed in the surface of the silicon oxide film 111chas also part of this second silicon oxide film 121cformed therein (see FIG. 3A).

[0122] Subsequently, heat treatment is conducted in a dry-O₂atmosphere at a temperature of 900-950° C. to thereby transform the second silicon oxide film 121cand the silicon oxide film 111cinto a silicon oxide film 121caand a first silicon oxide film 111carespectively. This heat treatment makes the second silicon oxide film 121cfiner and sufficiently dehydrates it and liberates R groups therefrom (see FIG. 3B). Prior to this heat treatment, cure processing may be conducted in a nitrogen atmosphere at a temperature of 500-600° C. to remove water contents from the second silicon oxide film 121cbeforehand.

[0123] Next, the silicon oxide film and the silicon nitride film are subjected to such anisotropic etching by use of an etching gas that gives a higher etching rate for the former than that for the silicon nitride film 103, to remove the silicon oxide film 121cacompletely, thus removing also the silicon nitride film 103 and the first silicon oxide film 111capartially. For example, supposing an etching rate ratio is about 2.0, an etching gas consisting of octa-fluoro-cylcobutane (C₄F₄) with a flow rate of 1.8×10⁻²L/min and argon with a flow rate of 0.4 L/min is used for a high-density plasma-etching apparatus (e.g., ECR etching apparatus) under conditions of a pressure of 2.7 Pa, a high-frequency source power of 2000 W (27 MHz) for an upper electrode, and a high-frequency source power of 1200 W (800 KHz) for a lower electrode to thereby conduct the above-mentioned anisotropic etching. This etching is actually conducted to leave a silicon nitride film 103cwith a film thickness of, for example, about 105 nm and a silicon oxide film 111cbwith its high surface higher by, for example, about 10 nm higher than a surface of the pad oxide film 102 in level (see FIG. 3C).

[0124] Note here that in the third embodiment, by the above-mentioned anisotropic etching, the silicon nitride film 103 may be etched until an upper surface of the first silicon oxide film 111caroughly agrees with the surface of the pad oxide film 102 in level, to leave the silicon nitride film 103 to a film thickness of about 100 nm.

[0125] Next, wet etching by use of hot phosphoric acid is conducted on the silicon nitride film 103cto remove it locally until the surface of the pad oxide film 102 is exposed (see FIG. 3D).

[0126] Subsequently, the pad oxide film 102 is removed by buffered hydrofluoric acid (or diluted hydrofluoric acid) until a surface of the silicon substrate 101 is exposed. At the same time, the thermal-oxidized film 107 and the silicon oxide film 111cbare also removed partially to provide a thermal-oxidized film 107cand a silicon oxide film 111ccrespectively. By this etching also, it is not difficult to hold a level difference between an upper surface of the silicon oxide film 111ccand the surface of the silicon substrate 101 within ±5 nm. An upper edge of the thermal-oxidized film 107cis roughly lower than the upper surface of the silicon oxide film 111ccby about 10 nm in level. Accordingly, the trenches 105are filled by the silicon oxide film 111ccwith the thermal-oxidized film 107ctherebetween, to complete the STI according to the third embodiment (see FIG. 3E).

[0127] The third embodiment has same effects as described in the above-mentioned second embodiment.

[0128] Also, in the above-mentioned third embodiment, the second silicon oxide film 121cis not limited to one by LPD but may be an organic SOG film, an inorganic SOG film made of such a material as silicon hydride sesqui-oxide like in the case of the above-mentioned first embodiment and second embodiment. Likewise, the second silicon oxide film 121cin the above-mentioned first embodiment and second embodiment may be formed by LPD.

[0129] FIGS. 4A to 6B are schematic cross-sectional views for showing element-isolating region forming steps according to a fourth embodiment of the present invention;

[0130] The following will describe a method for forming an STI according to the fourth embodiment with reference to FIGS. 4A to 6B.

[0131] First, a pad oxide film 202 with a film thickness of, for example, about 20 nm is formed on a silicon substrate 201 by thermal oxidation. A silicon nitride film 203 with a film thickness of, for example, about 200 nm is formed by CVD on a surface of the pad oxide film 202. Portions of the silicon nitride film 203 and the pad oxide film 202 which exist on a formation-reserved element isolating region are sequentially patterned by anisotropic etching.

[0132] Next, anisotropic etching is conducted using the silicon nitride film 203 to thereby form trenches 205. The trenches 205 have a minimum width of, for example, about 0.25 μm, a minimum inter-spacing of, for example, about 0.25 μm, and a depth of about 0.3-0.4 μm. An etching gas used in this anisotropic etching is HBr (+O₂) or Cl₂(+O₂) Next, on a surface of the trenches 205 is formed a thermal-oxidized film 207 with a film thickness of about up to 20 nm by thermal oxidation at a temperature of 900-950° C. The thermal-oxidized film 207 is thus formed to round off an upper edge of the trenches 205. Subsequently, a first silicon oxide film 212 having a film thickness of, for example, about 100 nm is formed by LPCVD. At this point in time, in the trenches 205, a recess (not key hole void) has been formed in the first silicon oxide film 212. To fill the trenches 205 only with the first silicon oxide film 212 formed by CVD, the first silicon oxide film 212 must have a film thickness not larger than ½ (e.g., 125 nm) of a minimum width of the trenches 205 because the trenches 205 have a key hole void formed therein due to the first silicon oxide film 212.

[0133] Next, a second silicon oxide film 221 is formed by spin-coating an inorganic SOG film made of, for example, a silicon hydride sesqui-oxide as a material. To completely fill the recess in the first silicon oxide film 212 formed in the trenches 205, the second silicon oxide film 221 must have a film thickness of about 550-700 nm (see FIG. 4A). Note here that in this embodiment, the second silicon oxide film 221 is not limited to the above-mentioned inorganic SOG film but may be an organic SOG film or even a silicon oxide film formed by LPD.

[0134] Subsequently, first heat treatment is conducted in a dry-O₂atmosphere at a temperature of 900-950° C. to thereby transform the second silicon oxide film 221 and first silicon oxide film 212 into silicon oxide film 221aand silicon oxide film 212arespectively. This heat treatment makes the second silicon oxide film 221 finer and sufficiently dehydrates it (see FIG. 4B). Prior to this heat treatment, to remove water contents from the second silicon oxide film 221, cure processing may be conducted in a nitrogen atmosphere at a temperature of 500-600° C.

[0135] Next, CPM is conducted on the silicon oxide film 221asilicon oxide film and 212ausing the silicon nitride film 203 as a stopper to thereby leave a silicon oxide film 221band a silicon oxide film 212brespectively. In this embodiment also, when CMP is thus conducted, a micro-scratch 215 is generated in a surface of the silicon oxide film 221b(or the silicon oxide film 212b) (see FIG. 4C).

[0136] Next, an inorganic SOG film made of, for example, silicon hydride sesqui-oxide as a material is spin-coated to thereby form a third silicon oxide film 222. The third silicon oxide film 222 has preferably have a film thickness of about 0.1-0.4 μm. The surface of the silicon oxide film 221band an upper edge surface of the silicon oxide film 212bare covered by the third silicon oxide film 222. Like in a case of the above-mentioned first embodiment, a starting material of silicon oxide is also in a liquid state, so that a void due to the micro-scratch 215 is also filled with part of the third silicon oxide film 222 (see FIG. 5A). Note here that as the above-mentioned second silicon oxide film 221 in this embodiment, the third silicon oxide film 222 in this embodiment is not limited to the above-mentioned SOG film but may be an organic SOG film or even a silicon oxide film formed by LPD.

[0137] Subsequently, second heat treatment is conducted in a dry-O₂atmosphere at a temperature of 900-950° C. to thereby transform the third silicon oxide film 222 into a silicon oxide film 222a. This heat treatment makes the third silicon oxide film 222 finer and sufficiently dehydrates it (see FIG. 5B). Prior to this second heat treatment, in order to remove water contents from the third silicon oxide film 222, cure processing may be conducted in a nitrogen atmosphere at a temperature of 500-600° C.

[0138] Next, anisotropic etching similar to, for example, that in the third embodiment is conducted to completely remove the silicon oxide film 222a, thus leaving a silicon nitride film 203awith a film thickness of, for example, about 105 nm and a silicon oxide film 221cand a silicon oxide film 212chaving their respective upper surface and upper edge surface higher than the surface by, for example, about 10 nm (see FIG. 5C).

[0139] Note here that in this embodiment also, the above-mentioned anisotropic etching may be conducted to etch the silicon nitride film 203 until the upper surface of the second silicon oxide film 221 (and the upper edge surface of the first silicon oxide film 212) may roughly agree with the surface of the pad oxide film 202 in level. Further, this anisotropic etching may be conducted like in a case of the above-mentioned first embodiment or second embodiment.

[0140] Next, the silicon nitride film 203ais subjected to wet etching using hot phosphoric acid and locally removed to thereby expose a surface of the pad oxide film 202 (see FIG. 6A).

[0141] Subsequently, buffered hydrofluoric acid (or diluted hydrofluoric acid) is used to remove the pad oxide film 202 until a surface of the silicon substrate 201 is exposed. At a same time, the thermal-oxidized film 207, the silicon oxide film 212c, and the silicon oxide film 221care also removed partially to provide a thermal-oxidized film 207a, a silicon oxide film 212d, and a silicon oxide film 221drespectively. By this etching also, it is not difficult to hold a level difference between an upper end surface of the silicon oxide film 212dand an upper surface of the silicon oxide film 221dand a surface of the silicon substrate 201 within ±5 nm. An upper edge of the thermal-oxidized film 207ais lower than the upper surface of the silicon oxide film 221d(and the upper edge surface of the silicon oxide film 212d) by about 10 nm. With this, the trenches 205 are filled by the silicon oxide film 212dand the silicon oxide film 221dwith the thermal-oxidized film 207ato thereby complete the STI according to this embodiment (see FIG. 6B).

[0142] The fourth embodiment has same effects as described in the above-mentioned third embodiment. Also, the above-mentioned anisotropic etching thus selectively conducted on the silicon oxide film and the silicon nitride film permits the fourth embodiment to have effects equivalent to those of the above-mentioned first or second embodiment.

[0143] It is apparent that the present invention is not limited to the above embodiments but may be changed and modified without departing from the scope and spirit of the invention.