Gate ground circuit approach for I/O ESD protection

[0002] 1. Field of the Invention

[0003] The invention relates to the protection of integrated circuits from electrostatic discharge (ESD), and more particularly to the method of providing substrate current flow in an NMOS cascode circuit in an ESD event.

[0004] 2. Description of the Related Art

[0005] In the present conventional 5VT Input/Output (I/O) circuit structure for ESD protection where two NMOS cascode circuits are used, the protection from ESD is diminished because current flow, caused by an ESD, is impeded in the NMOS cascode circuits. While the first NMOS transistor of each NMOS cascode circuit is on—caused by the coupling up of an ESD pulse into its gate—the second NMOS transistor of the second NMOS cascode circuit is off. The resulting current non-uniformity between the NMOS cascode circuits causes the device to fail at low ESD zapping voltages. FIG. 1 is a depiction of such a circuit of the prior art which will be described next.

[0006] Circuit 10 of FIG. 1 comprises at least one driver circuit 2, ESD protection circuit 3, and Vcc/Vss protection circuit 4. Driver circuit 2 has input 6 which couples to the gate of PMOS transistor 200, and input 7 which couples to the gate of NMOS transistor 220. Connected in series between voltage supply 8 and reference potential 9 (typically ground) are PMOS transistor 220, and NMOS transistors 210 and 220. The gate of transistor 210 is coupled to voltage supply 8, and the junction J1 of transistors 200 and 210 is connected to I/O pad 32. ESD protection circuit 3 comprises, in series between voltage supply 8 and reference potential 9, PMOS transistor 300, and NMOS transistors 310 and 320, respectively. The gates of transistors 300 and 310 are coupled to voltage supply 8, and the gate of transistor 320 is coupled to reference potential 9. The junction J2 between transistors 300 and 310 is coupled to I/O pad 32. Vcc/Vss protection circuit 4 is coupled in series between voltage supply 8 and reference potential 9. Typically Vcc/Vss protection circuit 4 comprises a plurality of NMOS transistors 400 and resistive means 410, where the latter are coupled between the gates of NMOS transistors 400 and reference potential 9. The drains and sources of transistors 400 are coupled to voltage supply 8 and reference potential 9, respectively.

[0007] Referring now to FIG. 1, FIG. 2a, and FIG. 2b, we continue with the description of the prior art circuit. NMOS transistors 210 and 220 form a cascode circuit 20 where the source 212 of transistor 210 and the drain 221 of transistor 220 share a diffusion region 21. Similarly, NMOS transistors 310 and 320 form a cascode circuit 30 where the source 312 of transistor 310 and the drain 321 of transistor 320 share a diffusion region 31. NMOS transistor 210 and NMOS transistor 310 are customarily called the “first transistor” or “N1” of each cascode circuit, and transistors 220 and 320 are called the “second transistor” or “N2.”

[0008] The problem with the circuit of FIG. 1 is that the voltage at the gate of NMOS transistors 210, 220 and 310 will be coupled up by an ESD pulse because these gates are in effect floating with respect to an ESD (when transistor 400 is off then the gates of transistors 210 and 310 are in effect floating, therefore, the gate voltage of transistors 210 and 310 will be coupled up by the drain voltage of 210 and 310, respectively). Therefore, the ESD pulse will travel at the surface of NMOS transistors 210 and 220 (in the n-channel). In the second cascode circuit, the gate of NMOS transistor 320 is connected to ground and, therefore, off (no n-channel) during an ESD while transistor 310 is on. Thus, the ESD pulse cannot travel at the surface of NMOS transistors 310 and 320. Hence, ESD protection will fail at low ESD voltages because of the current non-uniformity between driver circuit 2 and ESD protect circuit 3.

[0009] Prior art U.S. Patents which relate to the subject of ESD protection are:

[0010] U.S. Pat. No. 5,572,394 (Ker et al.) CMOS On-Chip Four-LVTSCR ESD Protection Scheme.

[0011] U.S. Pat. No. 5,804,861 (Leach) Electrostatic Discharge Protection in Integrated Circuits, Systems and Methods.

[0012] U.S. Pat. No. 5,852,375 (Byrne et al.) 5V Tolerant I/O Circuit.

[0013] U.S. Pat. No. 67005,413 (Schmitt) 5V Tolerant PCI I/O Buffer on 2.5′V Technology.

[0014] U.S. Pat. No. 6,028,450 (Nance) Programmable Input/Output Circuit with Pull-Up Bias Control.

[0015] U.S. Pat. No. 6,049,119 (Smith) Protection Circuit for a Semiconductor Device.

[0016] U.S. Pat. No. 67097,071 (Krakauer) ESD Protection Clamp for Mixed Voltage I/O Stages Using NMOS Transistors.

[0017] While above U.S. Patents offer various circuits and methods of protecting devices from destructive ESD, none of them use a clamping circuit to pull down to ground (reference potential) the first poly gate of each cascode circuit. The proposed circuit improves the ESD performance and eliminates the non-uniform current distribution in the cascode circuits of the prior art.

[0018] It is an object of the present invention to improve the ESD performance of the I/O ESD protection circuit.

[0019] It is another object of the present invention to create a uniform current flow between the first and the second NMOS cascode circuit.

[0020] It is yet another object of the present invention to force the gates of the first NMOS transistors to near ground (reference potential).

[0021] It is still another object of the present invention to improve the ESD performance with a minimal change to the I/O ESD protection circuit.

[0022] These and many other objects have been achieved by providing the I/O ESD protection circuit with driver circuits, ESD protection circuits, a Vcc/Vss protection circuit with a plurality of NMOS transistors, and by adding clamping circuits between the I/O pad of the ESD protection circuit and the Vcc/Vss protection circuit. Clamping circuits are implemented typically by a diode which has its cathode coupled to the I/O pad. NMOS cascode circuits of each driver circuit and each ESD protection circuit react to an ESD by having their first poly gates pulled down to ground by each clamping circuit. This clamping action prevents the gate voltage of the first NMOS transistor of the NMOS cascode circuits to be coupled up by an ESD pulse. This clamping action creates a current flow from the drain of the first NMOS transistor through the P-well to the source of the second NMOS transistor of each of the NMOS cascode circuits and, thus, prevents device failure at low ESD voltages. The current flow through the P-well is made possible by the action of a parasitic bipolar npn transistor which is created by the N+ drain (collector) of the first NMOS transistor, the P-well (base), and the N+ source (emitter) of the second NMOS transistor of both NMOS cascode circuits. The parasitic bipolar npn transistor is created when the poly gate of the first transistor is clamped to ground.

[0023] These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.

[0024] FIG. 1 is a circuit diagram of the prior art.

[0025] FIG. 2ais a schematic cross-section of the cascode circuit part of the ESD protection circuit of FIG. 1.

[0026] FIG. 2bis a schematic cross-section of the cascode circuit part of the driver circuit of FIG. 1.

[0027] FIG. 3 is a circuit diagram of the preferred embodiment of the present invention.

[0028] FIG. 4ais a schematic cross-section of the cascode circuit part of the ESD protection circuit of FIG. 3.

[0029] FIG. 4bis a schematic cross-section of the cascode circuit part of the driver circuit of FIG. 3.

[0030] The present invention provides a very successful solution to the problems of the circuit of the prior art by adding at least one clamping circuit to the circuit of FIG. 1, such that NMOS gates of driver circuit 2 and ESD protection circuit 3 become grounded during an ESD event. Referring now to FIG. 3, FIG. 4a, and FIG. 4b, we begin a description of the preferred circuit of the present invention. Note that the same numerals in FIGS. 1, 2a, 2b, 3, 4a, and 4bdesignate the same components. The gate ground circuit 30 for I/O electrostatic discharge (ESD) comprises at least one driver circuit 2, ESD protection circuit 3, Vcc/Vss protection circuit 4, and clamping circuit 5.

[0031] Referring now to FIG. 3 and FIG. 4b, each driver circuit 2 has at least one input, but typically two (inputs 6 and 7, with Signal 1 and Signal 2 applied, respectively), and an output J1, which is coupled to I/O pad 32 (Signal 2 is typically the inverse of Signal 1). Driver circuit 2 is further in communication with voltage supply 8 and reference potential 9 (typically ground). Each driver circuit 2 comprises PMOS transistor 200 in series with first and second NMOS transistors 210 and 220. Transistors 210 and 220 are part of a first NMOS cascode circuit 20. The source of transistor 200 is in communication with voltage supply 8, and its drain is coupled to the drain 211 of transistor 210. The gate of transistor 200 is coupled to input 6. The junction J1 of transistors 200 and 210 (drain of transistor 200 and drain of transistor 210) couples to I/O pad 32. The gate 213 of transistor 210 is in communication with voltage supply 8. The source 212 of transistor 210 connects to the drain 221 of transistor 220. The gate 223 of transistor 220 couples to input 7. The source 222 of transistor 220 is coupled to reference potential 9. Referring specifically to FIG. 4b, note that source 212 and drain 221 share the same active area 21 of the P-well 11.

[0032] ESD protection circuit 3, in communication with voltage supply 8 and reference potential 9, and further coupled to I/O pad 32, provides protection from ESD. Referring to FIG. 3 and FIG. 4a, each ESD protection circuit 3 comprises PMOS transistor 300 in series with first and second NMOS transistors 310 and 320. Transistors 310 and 320 are part of a second NMOS cascode circuit 30. The source of transistor 300 is in communication with voltage supply 8, and its drain is coupled to the drain 311 of transistor 310. The gate of transistor 300 is coupled to voltage supply 8. The junction J2 of transistors 300 and 310 (drain of transistor 300 and drain of transistor 310) couples to I/O pad 32. The gate 313 of transistor 310 is coupled to voltage supply 8. The source 312 of transistor 310 couples to the drain 321 of transistor 320. The gate 323 of transistor 320 is in communication with reference potential 9. The source 322 of transistor 320 is coupled to reference potential 9. Referring specifically to FIG. 4a, note that source 312 and drain 321 share the same active area 31 of the P-well 11.

[0033] Vcc/Vss protection circuit 4 is in communication with voltage supply 8 and reference potential 9. Vcc/Vss protection circuit 4 typically comprises a plurality of NMOS transistors 400 and resistive means 410. The drains of transistors 400 are in communication with voltage supply 8, the gates are coupled to terminal T, and the sources of transistors 400 and one side of resistive means 410 couple to reference potential 9. The other side of resistive means 410 couples to terminal T. Vcc/Vss protection circuit 4 provides further protection from ESD because transistors 400 go into controlled conduction upon being subjected to ESD.

[0034] Still referring to FIG. 3, FIG. 4a, and FIG. 4b, each clamping circuit 5, coupled between I/O pad 32 and terminal T of Vcc/Vss protection circuit 4, typically comprises a diode 51, where the cathode of diode 51 couples to I/O pad 32 and the anode couples to terminal T. The anode and cathode of Diode 51 are typically created by a P+ and an N+ region in an N-well (not shown). When the voltage of the ESD is high enough diode 51 will become reverse biased and conduct (zener effect). Current flowing through resistive means 410 will cause the voltage at terminal T to rise. Therefore, NMOS transistor 400 will turn on and its drain will be pulled to near ground (reference potential 9), thereby grounding gates 213 and 313 and turning off transistors 210 and 310. ESD current is now forced to flow through parasitic bipolar npn transistors 225 and 325 of the first NMOS cascode circuit 20 and second NMOS cascode circuit 30, respectively. Each of these parasitic bipolar npn transistors is created by the N+ diffusions of drains 211 and 311 acting as collectors of the parasitic bipolar npn transistors 225 and 325, respectively, the P-well 11 acting as base, and the N+ diffusions of sources 222 and 322 acting as emitters. More specifically, current flows from the drain 211 of first NMOS transistor 210 through the buried area of P-well 11 to the source 222 of second NMOS transistor 220 (driver circuit 2). The current, as identified by arrow A, is conducted by parasitic, bipolar transistor 225 turning on. Similarly, current flows from the drain 311 of first NMOS transistor 310 through the buried area of P-well 11 to the source 322 of second NMOS transistor 320 (ESD protection circuit 3). The current, as identified by arrow B, is conducted by bipolar transistor 325 turning on. Thus, the uniform current between driver circuit 2 and ESD protect circuit 3 improves the ESD performance of gate ground circuit 30.

[0035] Advantages of the present invention are that by adding a clamping circuit (typically a diode) to the circuit of the prior art the first poly gate of an NMOS cascode circuit gets grounded in an ESD event. The grounded first poly gate

[0036] a) prevents the gates of the first NMOS transistors 210 and 310 from getting coupled up to high by the drain voltage of 210 and 310, respectively, and

[0037] b) creates a uniform current flow from the drain of the first transistor through the P-well to the source of the second transistor of each NMOS cascode circuit.

[0038] While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.