US 6,413,842 B2Grant
Semiconductor device and method of fabricating the same
Issue Date:2002-07-02
•25 Claims
•5 Drawing Sheets
Abstract
A method for improving the reliability and yield of a thin film transistor by controlling the crystallinity thereof. The method comprises the steps of forming a gate electrode on an island amorphous silicon film, injecting an impurity using the gate electrode as a mask, forming a coating film containing at least one of nickel, iron, cobalt, platinum and palladium so that it adheres to parts of the impurity regions, and annealing it at a temperature lower than the crystallization temperature of pure amorphous silicon to advance the crystallization starting therefrom and to crystallize the impurity regions and channel forming region.
Metadata
Assignee
- Semiconductor Energy Laboratory Co., Ltd.
Inventors
- Shunpei Yamazaki
- Yasuhiko Takemura
- Hongyong Zhang
Application Information
Application Number:US 09/848,307
Filing Date:2001-05-04
Priority Date:1993-02-15
Art Unit:7
Classifications
IPC:
H01L 2120
Field of Search:
438478438482438486438166438164438149
Patent Drawings (5 sheets)
Description
[0002] This application is a Divisional of Ser. No. 09/334,645, filed Jun. 17, 1999, now U.S. Pat. No. 6,232,621, which is a Divisional of Ser. No. 08/821,656, filed Mar. 20, 1997, now U.S. Pat. No. 5,985,741, which is a Continuation of Ser. No. 08/486,218, filed Mar. 7, 1995, now abandoned, which is a Continuation-in-Part of Ser. No. 08/195,713, filed Feb. 14, 1994, now abandoned.
BACKGROUND OF THE INVENTION
[0003] 1. Field of the Invention
[0004] The present invention relates to a method of obtaining a crystalline semiconductor used for thin film devices such as a thin film insulated gate type field effect transistor (thin film transistor or TFT).
[0005] 2. Description of the Related Art
[0006] Conventionally, a crystalline semiconductor thin film used for thin film devices such as a thin film insulated gate type field effect transistor (TFT) has been fabricated by crystallizing an amorphous silicon film formed by a plasma CVD method or thermal CVD method at a temperature of more than 600° C. in an apparatus such as an electric furnace.
[0007] This conventional method, however, has had various problems. The biggest problem has been that it is difficult to obtain a good product because the crystalline silicon film obtained is polycrystal and there is difficultly in controlling its grain boundary, and its reliability and yield is not so high because of its dispersion characteristic. That is, because the silicon crystals obtained by conventional heat treatment grow totally at random, it has been almost impossible to control the direction of its crystal growth.
[0008] Accordingly, it is an object of the present invention to solve the aforementioned problems by providing a method for controlling the growth of the crystal.
SUMMARY OF THE INVENTION
[0009] According to the present invention, crystal growth is controlled, and a TFT having high reliability and high yield is obtained, by forming a gate electrode on a silicon film in an amorphous state or in a random crystal state (for example a state in which portions having good crystallinity and amorphous portions exist in a mixed state) which can be said to be a substantially amorphous state, by forming impurity regions within the silicon film using the gate electrode as a mask, forming regions containing at least one of nickel, iron, cobalt platinum or palladium so that they adhere on part of the impurity regions, and by annealing the whole to crystallize it starting from the region containing nickel.
[0010] In particular, the present invention allows substantial elimination of the grain boundary between the source and drain and the active layer and to obtain a good characteristic by advancing the crystallization of the source and drain at the same time as the crystallization of the active layer (channel forming region).
[0011] A method of growing a crystal of silicon film epitaxially in solid phase centering on a crystalline island film as a nucleus or as a seed crystal has been proposed as a prior art method (for example, Japanese Patent Laid-Open No. 1-214110, etc.). However, it has been difficult to suppress crystal growth from other sites even if the crystal nucleus exists. That is, because the annealing temperature for growing the crystal is a temperature suited for fully generating the crystal nucleus, the crystal often starts to grow from unexpected locations.
[0012] The inventor of the present invention found that nickel (Ni), cobalt, iron platinum and palladium are readily coupled with silicon and that the crystal would grow centering on them. The inventor noticed that nickel is readily made into nickel silicide (NiSX, 0.4≦×≦2.5) and that the lattice constant of the nickel silicide is close to that of silicon crystal, then devised a method of growing a silicon crystal centering on the nickel silicide. Actually, the crystal growing temperature could be lowered by 20° C. to 150° C. compared to that of the conventional method. Because no crystal nucleus was produced in a pure silicon film at this temperature, crystals did not grow from unexpected locations. It was assumed that the crystal grew from the crystal nucleus by the same mechanism as the conventional one and that the higher the temperature, the faster the speed of advancement of the crystallization, at temperatures at which crystal nuclei did not grow naturally (preferably less than 580° C.). A similar effect was seen also with iron (Fe), cobalt (Co) platinum (Pt) and palladium (Pd).
[0013] According to the present invention, a film or the like containing a simple substance of nickel, iron, cobalt, platinum or palladium or their suicides, acetates, nitrates and other organic acid salts is adhered to the impurity regions of the thin film transistor, and the region of the crystal silicon is expanded away therefrom as the starting point. By the way, oxide is not preferable as the material containing the aforementioned material because oxide is a stable compound and a silicide which is likely to become the crystal nucleus is not produced therefrom.
[0014] The crystal silicon which expands thus from a specific location has a structure close to a monocrystal having good continuous crystallinity. A better result could be obtained with an amorphous silicon film having less hydrogen concentration serving as the starting material for crystallization. However, because hydrogen was released as crystallization advanced, no clear correlation could be seen between the hydrogen concentration within the silicon film obtained and that of the amorphous silicon film as the starting material. The hydrogen concentration within the crystal silicon of the present invention was typically more than 1×1015atoms·cm−30.01 atomic % and less than 5 atomic %.
[0015] While a heavy metal material such as nickel, iron, cobalt or platinum or palladium is used in the present invention, those material themselves are not suitable for silicon as a semi-conductor material. It is therefore necessary to remove them if those elements are contained in excess. It was found from a result of the study conducted by the inventor that nickel can be fully removed by annealing it in an atmosphere of hydrogen chloride, various methane chlorides (CH3C1 etc.), various ethane chlorides (C2H3Cl3, etc.) and various ethylene chlorides (C2HCl3, etc.) at 400 to 650° C. It was found that the concentration of nickel, iron, cobalt, platinum or palladium within the silicon film of the present invention was preferably set at 1×1015cm−3to 1 atomic %, or the minimum concentration of nickel, iron, cobalt, platinum and palladium was more preferably 1×1015cm−3to 1×1019cm−3with a measured value of SIMS. Crystallization does not fully advance at a concentration less than this range and, conversely, characteristics and reliability are degraded when the concentration exceeds this range.
[0016] Various physical and chemical methods may be used for forming film nickel, iron, cobalt, platinum or palladium. They are, for example, those methods which require vacuum equipment such as a vacuum deposition method, sputtering method and CVD method and those methods which may be performed in air such as a spin coating method, dip method (application method), doctor blade method, screen printing method and spray thermal decomposition method.
[0017] Even though the spin coating method and dip method require no particular facility, they allow production of a film having a homogeneous film thickness and minute control of the concentration. As a solution used for these means, whatever acetates, nitrates or various carboxylic acid salts or other organic acid salts of nickel, iron, cobalt, platinum or palladium dissolve or diffuse in water, various alcohols (low and high grades) and petroleums (saturated hydrocarbons or unsaturated hydrocarbons) may be used.
[0018] In such a case, however, there has been the possibility that oxygen and carbon contained in those salts might diffuse within the silicon film, degrading the semiconductor characteristics. However, as a result of research advanced by a thermobalance method and differential thermal analysis, it was confirmed that they are decomposed into oxide or a simple substance in an adequate material at a temperature of less than 450° C., and that they would not diffuse into the silicon film thereafter. When such low order substances as the acetate and nitrate were heated under a reduced atmosphere such as a nitrogen atmosphere, they decomposed at less than 400° C. and became a simple metallic substance. Similarly, it was observed that when they were heated in an oxygen atmosphere, oxide was initially produced and eventually become a metallic simple substance as oxygen desorbed at higher temperatures.
[0019] The manner in which the foregoing and other objects of the present invention are accomplished will become apparent from the accompanying specification and claims, taken together with the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] FIGS. 1 (A) to 1 (C) are section views showing a process of an embodiment of the present invention (refer to first embodiment);
[0021] FIGS. 2 (A) to 2 (D) are section views showing a process of an embodiment of the present invention (refer to second embodiment);
[0022] FIGS. 3 (A) to 3 (D) are section views showing a process of an embodiment of the present invention (refer to third embodiment);
[0023] FIGS. 4 (A) to 4 (D) are section views showing a process of an embodiment of the present invention (refer to fourth embodiment); and
[0024] FIG. 5 is a graph showing nickel concentration within crystal silicon (refer to fourth embodiment).
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0025] Referring now to the drawings, preferred embodiments of the present invention will be explained.
First Embodiment
[0026] A ground silicon oxide film 11 having a thickness of 2000 angstroms was formed on a substrate (Corning 7059) 10 by a plasma CVD method. Further, an amorphous silicon film having a thickness of 200 to 3000 angstroms or preferably 500 to 1500 angstroms was fabricated by a plasma CVD or vacuum CVD method. The amorphous silicon film could be easily crystallized by reducing hydrogen concentration within the film to less than 5 atomic % by dehydrogenizing it by annealing for 0.1 to 2 hours at a temperature of from 350 to 450° C. It was then patterned to form an island silicon region 12. Then a silicon oxide film 13 having a thickness of 500 to 1500 angstroms which functions as a gate insulating film was formed by a RF plasma CVD, ECR plasma CVD or sputtering method. A favorable result could be obtained by using TEOS (tetraethoxisillane) and oxygen as original gases when the plasma CVD method was adopted. Then a tantalum film (5000 angstroms thick) containing 1% of silicon was deposited by a sputtering method and was patterned to form gate wiring and an electrode 14. Titanium, silicon, chromium or aluminum may be used as the material of the gate electrode.
[0027] Then, the substrate was soaked in an ethylene glycol solution of 3% tartaric acid and was anodized by setting platinum as the cathode and tantalum wire as the anode and circulating a current therebetween. The current was applied such that its voltage rises 2V/min. and becomes constant when it reaches 220 V. The current was stopped when it was reduced to less than 10 micro A/m2. As a result, an anodic oxide (tantalum oxide) 15 having a thickness of 2000 angstroms was formed. Similarly, titanium oxide, aluminum oxide or silicon oxide can be obtained as an anodic oxide when titanium, aluminum or silicon is used for the gate electrode (FIG. 1(A)).
[0028] Next, an impurity was introduced by a plasma doping method. For the doping gas, phosphine (PH3) was used for a N type TFT and diborane (B2H6) was used for a P type TFT. The N type TFT is shown in the figure. The acceleration voltage was 80 keV for phosphine and 65 keV for diborane. Impurity regions 16A and 16B were thus formed. At this time, the impurity regions and the gate electrode were offset as seen in the figure. Further, holes were created on the silicon oxide film 13 on the impurity regions to form nickel silicide (or nickel) films 17A and 17B so that they adhere to the semiconductor region 12 through the holes. Then annealing was carried out in a nitrogen atmosphere, at 550° C. for four hours to crystallize the impurity regions 16 and other semiconductor regions (FIG. 1(B)).
[0029] Finally, a silicon oxide film having a thickness of 5000 angstroms was deposited as an interlayer insulator 18 in the same manner as the fabrication method of normal TFTs, and contact holes were created therethrough to form wiring and electrodes 19A and 19B on the source and drain regions. Aluminum, titanium, titanium nitride or a multilayer film thereof is suitable for the wiring and electrode material. A multilayer film of titanium nitride (1000 angstroms thick) and aluminum (5000 angstroms thick) was used in this embodiment (FIG. 1(C)).
[0030] The TFT (N-channel type in the figure) was fabricated through the process described above. The field effect mobility of the TFT obtained was 40 to 60 cm2/Vs in the N-channel type and 30 to 50 cm2/Vs in the P-channel type. Further, the threshold voltage, field effect mobility and sub-threshold characteristic barely changed and high reliability could be obtained even when a voltage of from 17 to 25 V was applied for 48 hours between the gate and the drain. This is because the source, drain and channel forming region (the semiconductor region under the gate electrode) were crystallized simultaneously and their direction of crystallization is the same.
Second Embodiment
[0031] A ground silicon oxide film 21 having a thickness of 2000 angstroms was formed on a substrate (Corning 7059) 20 by a plasma CVD method. Further, an amorphous silicon film having a thickness of 200 to 3000 angstroms or preferably 500 to 1500 angstroms was fabricated by a plasma CVD or vacuum CVD method. The amorphous silicon film could be easily formed by reducing the hydrogen concentration within the film to less than 5 atomic % by dehydrogenizing it by annealing for 0.1 to 2 hours at 350 to 450° C. It was then patterned to form an island silicon region 23. Then a silicon oxide film 24 having a thickness of 500 to 1500 angstroms which functions as a gate insulating film was formed by a RF plasma CVD, ECR plasma CVD or sputtering method. A favorable result could be obtained by using TEOS (tetraethoxisillane) and oxygen as original gases when the plasma CVD method was adopted. Then a polycrystal silicon film (5000 angstroms thick) containing 1% to 5% of phosphorus was deposited by a LPCVD method and patterned to form gate wiring and electrodes 25A and 25B (FIG. 2(A)).
[0032] After that, an impurity was diffused thereinto by an ion doping method to form N type impurity regions 26A and P type impurity regions 26B. At this time, phosphorus (doping gas is phosphine PH3) can be used as the N type impurity for example to dope on the whole surface with 60 to 110 kV or 80 kV of acceleration voltage, for example, and then boron for example (doping gas is diborane B2H6) could be used as the P type impurity doped at an acceleration voltage of 40 or 80 kV or 65 kV, for example, to cover the region of the N channel type TFT by photoresist.
[0033] Further, holes were created in the silicon oxide film 24 on the impurity regions to form nickel silicide (or nickel) films 27A and 27B having a thickness of 200 to 1000 angstroms or 300 angstroms, for example, so that they adhere to the impurity regions 26 through the holes. Then annealing was carried out in a nitrogen atmosphere at 550° C. for four hours to crystallize the impurity regions 26 and other semiconductor regions. At this time, the crystal growth advances from both ends of the island semiconductor region and finishes around the middle thereof. Accordingly, no grain boundary was produced in the channel forming region and no detrimental effects were imposed on the characteristics of the TFT (FIG. 2 (B)).
[0034] Alternatively, a nickel silicide film 27 C may be provided in the middle of the island semiconductor region as shown in FIG. 2(C). In this case, crystallization advances from the center (FIG. 2(C)).
[0035] Finally, a silicon oxide film having a thickness of 5000 angstroms was deposited as an interlayer insulator 28 in the same manner as the fabrication method of normal TFTs, and contact holes were created therethrough to form wiring and electrodes 29A, 29B and 29C on the source and drain regions. Aluminum, titanium, titanium nitride or a multilayer film thereof is suitable for the wiring and electrode material. A multilayer film of titanium nitride (1000 angstroms thick) and aluminum (5000 angstroms thick) was used in this case.
[0036] The CMOS type TFT was fabricated by the process described above. Then a shift register was fabricated using a CMOS circuit thus fabricated to study its operating characteristics. As a result, the maximum operating frequency was 11 MHz when the drain voltage was 15 V and 18 MHz when the drain voltage was 17 V.
Third Embodiment
[0037] The present embodiment relates to an arrangement in which the crystallinity of the semiconductor region is further improved by annealing it by radiating it with laser beams following crystallization by means of heating, as in the process of the first embodiment.
[0038] The fabricating process thereof will be explained below, referring to FIG. 3. A ground silicon oxide film 31 having a thickness of 2000 angstroms was formed on a substrate (Corning 7059) 30 by a plasma CVD method. Further, an amorphous silicon film having a thickness of 200 to 3000 angstroms or preferably 500 to 1500 angstroms was fabricated by a plasma CVD or vacuum CVD method. The amorphous silicon film could be easily crystallized by reducing hydrogen concentration within the film to less than 5 atomic % by dehydrogenizing it by annealing for 0. 1 to 2 hours at 350 to 450° C. It was then patterned to form an island silicon region 32. Then a silicon oxide film 33 having a thickness of 500 to 1500 angstroms which functions as a gate insulating film was formed by a RF plasma CVD, ECR plasma CVD or a sputtering method. A favorable result could be obtained by using TEOS (tetraethoxisillane) and oxygen as original gases when the plasma CVD method was adopted.
[0039] Then a tantalum film (5000 angstroms thick) containing 1% silicon was deposited by a sputtering method and patterned to form gate wiring and an electrode 34. Titanium, silicon, chromium or aluminum may be used as the material of the gate electrode.
[0040] Then the substrate was soaked in an ethylene glycol solution of 3% tartaric acid and was anodized by setting platinum as the cathode and a tantalum wire as the anode and circulating a current therebetween. The current was applied so that its voltage rises 2 V/min. and becomes constant when it reaches 220 V. The current was stopped when it was reduced to 10 micro A/m2. As a result, an anodic oxide (tantalum oxide) 35 having a thickness of 2000 angstroms was formed. Similarly, titanium oxide, aluminum oxide or silicon oxide can be obtained as the anodic oxide when titanium, aluminum or silicon is used for the gate electrode (FIG. 3(A)).
[0041] Next, an impurity was introduced by a plasma doping method. As a doping gas, phosphine (PH3) was used for the N type TFT and diborane (B2H6) was used for the P type TFT. The N type TFT is shown in the figure. The acceleration voltage used was 80 keV for phosphine and 65 kev for diborane. Impurity regions 36A and 36B were thus formed. At this time, the impurity regions and the gate electrode are offset as seen in the figure. Further, holes were created in the silicon oxide film 33 on the impurity regions to form nickel silicide (or nickel) films 37A and 37B so that they adhere to the semiconductor region 32 through the holes. Then annealing was carried out in a nitrogen atmosphere at 550° C. for four hours to crystallize the impurity regions 36A and 36B and other semiconductor regions (FIG. 3(B)).
[0042] Next, crystallization was promoted by radiating a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) thereon. Laser beam irradiation was carried out here in two shots with 200 to 400 mJ/cm2of energy density or 250 mJ/cm2of energy density. Further, at this time, the laser beam was radiated while heating the substrate up to 300° C. to increase the effect of the laser beam radiation. The substrate may be heated up to a temperature of between 200° C. and 450° C.
[0043] XeCl (wavelength: 308 nm), ArF (wavelength: 193 nm) or the like may be used as the laser beam. It is also possible to radiate a strong light instead of a laser beam. RTA (rapid thermal annealing) performed by radiating an infrared beam for a short time is particularly useful because it allows the silicon film to be heated selectively.
[0044] Thus a silicon film having good crystallinity may be obtained. As a result of such treatment, the region crystallized by thermal annealing became a silicon film having improved crystallinity. According to observation made through a transmission type electronic microscope, relatively large crystals of the same direction were observed in the region irradiated by the laser after the crystallization method of the present invention.
[0045] Finally, a silicon oxide film having a thickness of 5000 angstroms was deposited as an interlayer insulator 38 in the same manner as the fabrication method of normal TFTs, and contact holes were created therethrough to form wiring and electrodes 39A and 39B on the source and drain regions. Aluminum, titanium, titanium nitride or a multilayer film thereof is suitable for the wire and electrode material. A multilayer film of titanium nitride (1000 angstroms thick) and aluminum (5000 angstroms thick) was used in this embodiment. The TFT (N-channel type in the figure) was fabricated by the process described above (FIG. 3(C)).
Fourth Embodiment
[0046] The present embodiment is a method for introducing a catalytic element into an amorphous silicon film by a solution containing a catalytic element for accelerating crystallization.
[0047] Referring now to FIG. 4, the fabrication process thereof will be explained. Firstly, a ground silicon oxide film 41 having a thickness of 2000 angstroms was formed on a 10 cm square substrate (Corning 7059) 40 by a plasma CVD method. The amorphous silicon film having a thickness of 200 to 3000 angstroms or preferably 500 to 1500 angstroms was fabricated by a plasma CVD or vacuum CVD method. The amorphous silicon film could be easily crystallized by reducing the hydrogen concentration within the film to less than 5 atomic % by dehydrogenizing it by annealing for 0.1 to 2 hours at 350 to 450° C. It was then patterned to form an island silicon region 42.
[0048] Then a silicon oxide film 43 having a thickness of 500 to 1500 angstroms which functions as a gate insulating film was formed by RF plasma CVD, ECR plasma CVD or a sputtering method. A favorable result could be obtained by using TEOS (tetraethoxisilane) and oxygen as original gases when the plasma CVD method was adopted. Then a tantalum film (5000 angstroms thick) containing 1% of silicon was deposited by a sputtering method and was patterned to form gate wiring and an electrode 44. Titanium, silicon, chromium or aluminum may be used as the material of the gate electrode.
[0049] Then the substrate was soaked in an ethylene glycol solution of 3% tartaric acid and anodized by setting platinum as the cathode and a tantalum wire as the anode and by circulating a current therebetween. The current was applied such that its voltage rises 2 V/min. and becomes constant when it reaches 220 V. The current was stopped when it was reduced to 10 micro A/m2. As a result, an anodic oxide (tantalum oxide) 45 having a thickness of 2000 angstroms was formed. Similarly, titanium oxide, aluminum oxide or silicon oxide can be obtained as the anodic oxide when titanium, aluminum or silicon is used for the gate electrode (FIG. 4(A)).
[0050] Next, an impurity was introduced by a plasma doping method. As a doping gas, phosphine (PH3) was used for the N type TFT and diborane (B2H6) was used for the P type TFT. The N type TFT is shown in the figure. The acceleration voltage was 80 keV for phosphine and 65 keV for diborane. Impurity regions 46A and 46B were thus formed. At this time, the impurity regions and the gate electrode are offset as seen in the figure (FIG. 4(B)).
[0051] Further, holes were created in the silicon oxide film 43 on the impurity regions. Then a thin silicon oxide film 51 was formed by radiating an ultraviolet beam thereon for five minutes in an oxygen atmosphere. The thickness of this silicon oxide film 51 was assumed to be around 20 to 50 angstroms.
[0052] This silicon oxide film was formed to improve the wettability of a solution applied in a later process. In this state, 5 ml of acetate solution into which 100 ppm (reduced weight) of nickel was added was dripped (in the case of the 10 cm square substrate). At this time, a homogeneous water film 52 was formed on the entire surface of the substrate by spin-coating it for 10 seconds at 50 rpm by means of a spinner 41. Further, after holding the substrate for five minutes in this state, it was spin-dried for 60 seconds at 2000 rpm using the spinner 41. Incidentally, it may be held on the spinner while rotating it from 0 to 150 rpm (FIG. 4(C)).
[0053] By the way, although FIG. 4(C) is drawn as if the substrate 40 on which one TFT is provided is placed on the spinner 41, actually a large number of TFTs are formed on the substrate 40.
[0054] Then, the amorphous silicon film 42 was crystallized by heat treating it for four hours at 550° C. (in a nitrogen atmosphere). At this time, the crystal grew in the horizontal direction from the region into which nickel was introduced (the region contacting with an oxide film 51) to the region into which no nickel was introduced.
[0055] It is effective to improve the crystallinity of the crystalline silicon film by irradiating it with a laser or equivalent strong light to obtain the film described in the third embodiment. Because nickel concentration within the silicon film was relatively high in the third embodiment, nickel within the silicon film precipitated and grains of nickel silicide of around 0.1 to 10 microns were formed within the silicon film by the laser radiation, thus worsening the morphology of the film. However, because the present embodiment allows reduction of the nickel concentration to a greater extent than the third embodiment, no nickel silicide precipitated and the film could be prevented from being roughened by laser irradiation.
[0056] FIG. 5 shows a study result on the nickel concentration in a region denoted by the reference number 50 after finishing the crystallization process in SIMS. This region is a region crystallized by the crystal growth from the region into which nickel was directly introduced and functions as a channel forming region of the TFT. It was confirmed that the concentration of nickel in the region where nickel was directly introduced presents a concentration higher than the concentration distribution shown in FIG. 5 by one digit. That is, it was confirmed that the nickel concentration of the channel forming region was less by more than one digit as compared to the nickel concentration of the source/drain region of the TFT after completion, as shown in FIG. 5.
[0057] The nickel concentration shown in FIG. 5 can be controlled by controlling the nickel concentration within the solution. While the nickel concentration in the solution was 100 ppm in the present embodiment, it was found that it would be possible to crystallize even with 10 ppm of nickel concentration. In this case, the nickel concentration shown in FIG. 5 can be further reduced by one digit. However, a problem arises when the nickel concentration within the solution is reduced, in that the distance of crystal growth in the horizontal direction from the region into which nickel is introduced is shortened.
[0058] Finally, a silicon oxide film having a thickness of 5000 angstroms was deposited as an interlayer insulator 48 in the same manner as the fabrication method of normal TFTs, and contact holes were created therethrough to form wiring and electrodes 49A and 49B on the source and drain regions. Aluminum, titanium, titanium nitride or a multilayer film thereof is suitable for the wiring and electrode material. A multilayer film of titanium nitride (1000 angstroms thick) and aluminum (5000 angstroms thick) was used in this case.
[0059] Although the acetate solution was used as the solution containing the catalytic element in the present embodiment, it is possible to use an aqueous solution, organic solvent solution or the like. Here the catalytic element may be contained not as a compound but merely as a dispersed substance.
[0060] One solvent chosen from water, alcohol, acid and ammonia, which are polar solvents, may be used as the solvent for containing the catalytic element.
[0061] When nickel is used as the catalyst and is contained in the polar solvent, it is introduced as a nickel compound. As the nickel compound, one compound chosen from among nickel bromide, nickel acetate, nickel oxalate, nickel carbonate, nickel chloride, nickel iodide, nickel nitride, nickel sulfate, nickel formate, nickel acetylacetonate, nickel 4-cyclohexyl butyric acid, nickel oxide and nickel hydroxide is typically used.
[0062] For the solvent, one chosen from among benzene, toluene, xylene, carbon tetrachloride, chloroform and ether, which are non-polar solvents, may be used.
[0063] In this case, nickel is introduced as a nickel compound. One chosen compound from among nickel acetylacetonate and nickel 2-ethylhexanodic acid is typically used as the nickel compound.
[0064] It is also useful to add a surface active agent to the solution containing the catalytic element to improve its adhesiveness to the surface to be applied and to control its adsorption. It is possible to apply the surface active agent on the surface to be applied beforehand. A simple substance nickel must be dissolved by an acid into a solution when it is used as the catalytic element.
[0065] Although the case in which the solution into which nickel, the catalytic element, was completely dissolved was used has been described above, it is possible to use materials such as an emulsion in which powder composed of the simple substance nickel or nickel compound is dispersed homogeneously within a dispersion medium without dissolving the nickel completely. As such a solution, OCD (Ohka Diffusion Source) available from Tokyo Ohka Kogyo Co., Ltd. may be used. The use of the OCD solution allows easy formation of a silicon oxide film by applying it on the surface for forming the film and by baking it at around 200° C. Further, because it allows impurities to be added freely, they can be used.
[0066] The aforementioned description applies also to a case wherein a material other than nickel is used as the catalytic element.
[0067] Furthermore, the use of a non-polar solvent such as a toluene solution of nickel 2-ethylhexanodic acid as the solution allows directly application on the surface of the amorphous silicon film. In this case, it is effective to apply such a material as an adhesive used in applying resists beforehand. However, one must be careful not to apply the solution too much because doping of the catalytic element into the amorphous silicon is impaired.
[0068] While the amount of the catalytic element contained in the solution depends on the type of solution, it is desirable that it be 200 ppm to 1 ppm or preferably 50 ppm to 1 ppm (reduced weight) to the solution as a general tendency. This value is determined in consideration of the nickel concentration within the film and hydrofluoric acid resistance after completion of crystallization.
[0069] As described above, the present invention allows control of the direction of crystal growth, which has been difficult in the past, and allows remarkable improvement of the reliability and yield of thin film transistors. Further, because the facilities, apparatuses and techniques necessary for the present invention are very general and are excellent in terms of mass-producibility, the present invention contributes an immeasurable benefit to the industry. Thus the present invention is industrially beneficial and worthy of patent.
[0070] While the present invention has been particularly shown and described with reference to preferred embodiments thereof, it should be understood by those skilled in the art that the foregoing and other changes in form and details can be made therein without departing from the spirit and scope of the present invention.
[0071] These are some methods to perform solid phase crystallization by using a metal catalyst. In using such metal catalyst elements, including Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au, etc., the conventional method was physical formation such as sputtering method, electron beam evaporation method, etc.
[0072] In this case, a film including the catalyst of 5 to 200 Å in average thickness, e. g. 10 to 50 Å thick is formed in an island-form on a surface. That is, the catalyst element is dotted on the surface in the form of micrograins with an average diameter of 50 to 200 Å. The grain are separated from each other by approximately 100 to 1000 Å. In other words, it does not form a continuous film in any way, but forms a discontinuous film. Consequently, the metal islands form nuclei for crystallization. Crystals are grown from the nuclei in an amorphous silicon film on an insulating substrate by means of a thermal treatment at 450° C. to 600° C.
[0073] In the above conventional method, the crystallization temperature can be dropped by 50 to 100° C., in comparison to when such catalyst elements are not used for the crystallization. However, the following thing became clear as a result of observing the crystallized film carefully. A number of amorphous regions are left and that such regions have a metallic property. It is presumed that the metal catalyst is left as they are.
[0074] These metal regions form recombination centers of electrons and halls. Adding a reverse bias voltage to a semiconductor device, in particular, PI or NI junction because of the metal region existing in the junction region, it has quite inferior characteristics in that a leak current is increased. When thin-film transistors of channel length/channel width=8 μm/8 μm is formed with such a semiconductor layer, the Off-state current is 10−10to 10−6A, which is 102to 106times larger than 1012although an OFF=-state current should be as small as about 1012A.
[0075] The present invention aims at giving the chemical formation method which is quite different from above. In order to solve the problem above, it is a characteristic of the present invention to form a catalytic layer by using a solution (water, isopropyl alcohol, etc.) which contains a metal organic compound at a concentration 10 ppm to 100 ppm. For example, the following metal complex salt can be used as the metal compound. Namely, ferrous bromide (FeBr26H2), ferric bromide (FeBr36H2O), ferric acetate (Fe(C2H3O2)3xH2O), ferrous chloride (FeCl24H2O), ferric chloride (FeCl36H2O), ferric fluoride (FeF33H2O), ferric nitrate (Fe(NO3)39H2O), ferrous phosphate (Fe3(PO4)28H2O), ferric phosphate (FePO42H2O), cobalt bromide (CoBr 6H2O), cobalt acetate (Co(C2H3O2)24H2O), cobalt chloride (CoCl26H2O), cobalt fluoride (CoF2xH2O), cobalt nitrate (Co(NO3)26H2O), ruthenium chloride (RuCl3H2O), rhodium chloride (RhCl33H2O), palladium chloride (PdCl22H2O), osmium chloride (OsCI3), iridium trichloride (IrCl33H2O), iridium tetrachloride (IrCl4), platinic chloride (PtCl45H2O), cupric acetate (Cu(CH3COO)2), cupric chloride (CuCl22H2O), cupric nitrate (Cu(NO3)23H2O), auric trichloride (AuCl3xH2O), auric chloride (AuHCI44H2O), sodium auric tetrachloride (AuNaCl42H2O).
[0076] The above materials can be dispersed in a solution in a monomolecular form. This solution can be spread on an entire surface of a substrate by spin coating in which the solution is dropped and then the substrate is rotated at a rotational speed of 50 to 500 r.p.m.
[0077] When a silicon oxide film of 5 to 100 Å thick is formed on the surface of a silicon semiconductor in order to improve a wettability of the silicon surface with respect to the solution, this thin film can prevent the. solution from becoming spot condition by the surface tension of liquid. It is also practicable to improve the wettability of semiconductor silicon without a silicon oxide film by adding a surface active agent into the solution.
[0078] In these methods, the metal catalyst atoms can be dispersed into semiconductor through the oxide film. In particular, it is possible to promote a crystallization without forming crystal nuclei in the form of grains. Therefore, it is a favorable method.
[0079] It is also useful to coat the organic metal uniformly and a UV treatment (ozone treatment) in oxygen is performed for formation of a metal oxide film. In this case, oxidized organic substance can be vaporized and removed as carbon dioxide, so it is possible to make the solid phase growth more uniform.
[0080] When the spin coating is carried out only at low rational speed, too much metal constituent for solid phase growth is apt to be supplied into the semiconductor film. Therefore, after the rotation at a low speed, the substance is rotated at 1000 to 10,000 r.p.m. e.g., 2000 to 5000 r.p.m. Thus, an excess organic metal can be eliminated from the surface of substrate and the surface can be dried sufficiently. Moreover, it is effective to control the amount of the organic metal to be formed on the surface. In the above chemical formation method, a continuous layer can be formed on a surface of semiconductor without forming nuclei of metal particles for crystallization.
[0081] A metal catalyst layer becomes inhomogeneous layer when it is formed by a physical formation method, on the other hand, it becomes homogeneous layer when it is formed by a chemical method as is the case in the present invention.
[0082] In accordance with the above new concept, the crystals can be grown far more uniformly on an entire surface of the semiconductor film when the crystallization is performed by thermal treatment which is performed at 450° C. to 650° C. Therefore, it is possible to form excellent P—I and N—I junctions by using the thus crystallized semiconductor film. In this case, the leak is controlled to be as small as 1012A even if a reverse bias voltage is applied.
[0083] In the case of a physical method, 90 to 100 out of 100 P—I junctions have a large leak current, that is 10−10to 10−5A and 50 to 70 out of 100 N—I junctions have 10−12to 10−6leak current. On the other hand, in the chemical method of the present invention, 5 to 20 out of 100 P—I junctions have a leak current as small as 10−13to 10−8A and 0 to 20 out of 100 N—I junctions have a leak current as small as 10−13to 10−8A. So, the present invention improves the characteristics quite remarkably because both an OFF-state current and the probability of a film that leak current is large are reduced.
[0084] Besides, the fine effect can be obtained in both P-channel TFTs (having a PIP junctions) and N-channel TFTs (having a NIN junctions) by forming the above semiconductor film on an insulating surface. Moreover, the present invention can reduce the probability by about 1 or 2 orders that TFTs having large leak current are formed. However, if the TFTs are used for making thin film IC, the probability which TFTs having large current are formed should be decreased 1/103to 1/109.
[0085] In the present invention, after the thermal crystallization, a laser light having a wavelength 248 nm or 308 nm is irradiated on the surface of the semiconductor with the energy density being at 250 to 400 mJ/cm2. The absorption of light is larger in the region that metal constituent exist largely compared to the silicon region crystallized. That is, the region which remains an amorphous structure becomes black optically while the crystal constituent is transparent. Because of this, the slightly remaining amorphous component can be melted by the irradiation of the laser light selectively. Further, the metal existing in the amorphous component can be dispersed to an atomic level in this manner.
[0086] As a result, it was possible to reduce the possibility that the metal regions are formed within a recrystallized film, and it was possible to reduce the leak current of a TFT to 10−13to 10−12A, and further, when 104to 108pieces of TFTs were manufactural, only 1-3 of them had an undesirable large leak current. This is because the metal regions which form recombination centers and cause the increase in a leak current are removed from the semiconductor film.
[0087] By spin coating in the present method, the leak current of the reversed direction i. e. Ioff is reduced by two orders, and the probability which TFTs having a large leak current exist can be reduced by two orders. Nevertheless, TFTs having a large leak current are formed. Assumably, the cause of forming such defective TFTs is that dust adheres to the surface of the semiconductor, on which organic metal concentrates. The characteristic can be improved by the improvement of experimental equipment.
[0088] An experiment was conducted in which laser light was irradiated to a film which was obtained by forming a catalyst metal through a conventional physical formation method and heat crystallizing. In this case, however, an OFF current- could not be reduced at all at P—I or N—I junctions when a reverse bias voltage was applied, even if the semiconductor is fused by the irradiation of laser light for recrystallization because metal grains in the starting film tend to be too big.
[0089] Accordingly, the method which utilizes a chemical formation method for forming a continuous layer of an organic metal catalyst is entirely different from the conventional method which utilizes a physical formation method followed by a thermal crystallization process. It is clearly understood that the chemical formation method is superior.
[0090] Instead of using a solution for forming the continuous catalyst layer, it is possible to utilize a CVD method with an organic metal gas as a starting material. The method is quite effective in order to reduce both an OFF current and the probability which TFTs having a large leak current exist. Further, the process of the present invention is a homogeneous crystal growth, that is, isotropic growth by using metal catalyst. On the other hand, the process of the conventional method is a non-uniform crystal growth, that is, a non-isotropic growth by using metal nuclei.
[0091] In the present invention, there are two ways as to how the crystal growth occurs; one is that the crystals are grown in the transverse direction with the surface of the substrate and the other is that the crystals are grown in the vertical direction with the surface of the substrate from the lower side of the semiconductor to the upper side thereof or vice versa. In either case, it was possible to obtain a semiconductor having an excellent electrical characteristics.
Claims
What is claimed is:
1. A method of manufacturing a semiconductor device, said method comprising the steps of:
forming an amorphous semiconductor film on an insulating surface;
adding a material into at least a portion of the amorphous semiconductor film to form a material additional region, said material being capable of promoting a crystallization of the amorphous semiconductor film;
crystallizing the amorphous semiconductor film to form a crystalline semiconductor film;
patterning the crystalline semiconductor film to form a crystalline semiconductor island;
forming a gate electrode adjacent to the crystalline semiconductor island with a gate insulating film interposed therebetween;
introducing an impurity into the crystalline semiconductor island to form a first impurity region, a second impurity region and a channel region formed between the first and second impurity regions,
wherein a crystal growth extends from the material additional region through the channel region in the crystalline semiconductor island and finishes in a portion of the other one of the first and second impurity regions.
2. A method according to claim 1 further comprising the step of:
forming at least a wiring in contact with the portion of the other one of the first and second impurity regions.
3. A method according to claim 1, wherein the material contains metal silicide.
4. A method according to claim 1,
wherein the material contains at least one selected from the group consisting of nickel, cobalt, iron, platinum and palladium.
5. A method according to claim 1,
wherein the crystalline semiconductor island comprises hydrogen at a concentration in a range of 0.01-5 atomic %.
6. A method according to claim 2,
wherein the wiring comprises at least one selected from the group consisting of aluminum, titanium and titanium nitride.
7. A method according to claim 1, wherein the channel region includes no grain boundary.
8. A method of manufacturing a semiconductor device, said method comprising the steps of:
forming an amorphous semiconductor film on an insulating surface;
adding a material into at least a portion of the amorphous semiconductor film to form a material additional region, said material being capable of promoting a crystallization of the amorphous semiconductor film;
crystallizing the amorphous semiconductor film to form a crystalline semiconductor film;
patterning the crystalline semiconductor film to form a crystalline semiconductor island;
forming a first gate electrode and a second gate electrode each adjacent to the crystalline semiconductor island with a gate insulating film interposed therebetween;
introducing a first impurity into the crystalline semiconductor island to form a first pair of impurity regions and a first channel region formed between the first pair of impurity regions;
introducing a second impurity into the crystalline semiconductor island to form a second pair of impurity regions and a second channel region formed between the second pair of impurity regions,
wherein the material additional region is formed in at least one of the first pair of impurity regions and at least one of the second pair of impurity regions,
wherein a crystal growth extends from the material additional region through each of the first channel region and the second channel region in the crystalline semiconductor island and finishes in a portion of the other one of the first pair of impurity.
9. A method according to claim 8 further comprising the step of:
forming at least a wiring in contact with each of the portion of the other one of the first pair of impurity regions and the portion of the other one of the second pair of impurity regions.
10. A method according to claim 8,
wherein the first pair of impurity regions comprises an n-type impurity while the second pair of impurity regions comprises a p-type impurity.
11. A method according to claim 8,
wherein the material additional region is formed at an end of the crystalline semiconductor island while each of the portion of the other one of the first impurity regions and the portion of the other one of the second impurity regions is formed at a middle of the crystalline semiconductor island.
12. A method according to claim 8, wherein the material contains metal silicide.
13. A method according to claim 8,
wherein the material contains at least one selected from the group consisting of nickel, cobalt, iron, platinum and palladium.
14. A method according to claim 8,
wherein the crystalline semiconductor island comprises hydrogen at a concentration in a range of 0.01-5 atomic %.
15. A method according to claim 9,
wherein the wiring comprises at least one selected from the group consisting of aluminum, titanium and titanium nitride.
16. A method according to claim 8,
wherein each of the first and second channel regions includes no grain boundary.
17. A method of manufacturing a semiconductor device, said method comprising the steps of:
forming an amorphous semiconductor film on an insulating surface;
introducing a material into the amorphous semiconductor film, said material being capable of promoting a crystallization of the amorphous semiconductor film;
crystallizing the amorphous semiconductor film to form a crystalline semiconductor film;
patterning the crystalline semiconductor film to form a crystalline semiconductor island;
forming a first gate electrode and a second gate electrode each adjacent to the crystalline semiconductor island with a gate insulating film interposed therebetween;
introducing an n-type impurity into the crystalline semiconductor island to form a pair of n-type impurity regions and a first channel region formed between the pair of n-type impurity regions;
introducing a p-type impurity into the crystalline semiconductor island to form a pair of p-type impurity regions and a second channel region formed between the pair of p-type impurity regions;
wherein one of the pair of n-type impurity regions is in contact with one of the pair of p-type impurity regions at a first portion in the crystalline semiconductor island,
wherein the material is introduced into a portion of the other one of the pair of n-type impurity regions and a portion of the other one of the pair of p-type impurity regions,
wherein a crystal growth extends from the portion of the other one of the pair of n-type impurity regions and the portion of the other one of the pair of p-type impurity regions, respectively, through each of the first channel region and the second channel region, and collides each other in the vicinity of the first portion.
18. A method according to claim 17 further comprising the step of:
forming first and second wirings in contact with the portion of the other one of the pair of n-type impurity regions and the portion of the other one of the pair of p-type impurity regions, respectively.
19. A method according to claim 17 further comprising the step of:
forming a third wiring in contact with the first portion in the crystalline semiconductor island.
20. A method according to claim 17, wherein the material contains metal silicide.
21. A method according to claim 17,
wherein the material contains at least one selected from the group consisting of nickel, cobalt, iron, platinum and palladium.
22. A method according to claim 17,
wherein the crystalline semiconductor island comprises hydrogen at a concentration in a range of 0.01-5 atomic %.
23. A method according to claim 18,
wherein each of the first and second wirings comprises at least one selected from the group consisting of aluminum, titanium and titanium nitride.
24. A method according to claim 19,
wherein the third wiring comprises at least one selected from the group consisting of aluminum, titanium and titanium nitride.
25. A method according to claim 17,
wherein each of the first and second channel regions includes no grain boundary.
Patent Citations (38)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3783049(A) | 1974-01-01 | Sandera | Applicant |
| USRE28385(E) | 1975-04-01 | Mayer | Applicant |
| USRE28386(E) | 1975-04-01 | Heiman et al. | Applicant |
| US4231809(A) | 1980-11-01 | Schmidt | Applicant |
| US4727044(A) | 1988-02-01 | Yamazaki | Applicant |
| US4783049(A) | 1988-11-01 | Northman et al. | Applicant |
| US4959700(A) | 1990-09-01 | Yamazaki | Applicant |
| US5075259(A) | 1991-12-01 | Moran | Applicant |
| US5147826(A) | 1992-09-01 | Liu et al. | Applicant |
| US5219786(A) | 1993-06-01 | Noguchi | Applicant |
| US5225355(A) | 1993-07-01 | Sugino et al. | Applicant |
| US5244819(A) | 1993-09-01 | Yue | Applicant |
| US5264383(A) | 1993-11-01 | Young | Applicant |
| US5275851(A) | 1994-01-01 | Fonash et al. | Applicant |
| US5289030(A) | 1994-02-01 | Yamazaki et al. | Applicant |
| US5298075(A) | 1994-03-01 | Lagendijk et al. | Applicant |
| US5300187(A) | 1994-04-01 | Lesk et al. | Applicant |
| US5352291(A) | 1994-10-01 | Zhang et al. | Applicant |
| US5488000(A) | 1996-01-01 | Zhang et al. | Applicant |
| US5492843(A) | 1996-02-01 | Adachi et al. | Applicant |
| US5508533(A) | 1996-04-01 | Takemura | Applicant |
| US5529937(A) | 1996-06-01 | Zhang et al. | Applicant |
| US5569936(A) | 1996-10-01 | Zhang et al. | Applicant |
| US5608232(A) | 1997-03-01 | Yamazaki et al. | Applicant |
| US5646424(A) | 1997-07-01 | Zhang et al. | Applicant |
| US5773327(A) | 1998-06-01 | Yamazaki et al. | Applicant |
| US5818076(A) | 1998-10-01 | Zhang et al. | Applicant |
| US5897347(A) | 1999-04-01 | Yamazaki et al. | Applicant |
| US5985741(A) | 1999-11-01 | Yamazaki et al. | Examiner |
| JP45-022173 | 1970-07-01 | Applicant | |
| JP62-245674 | 1987-10-01 | Examiner | |
| JP63-142807 | 1988-06-01 | Applicant | |
| JP64-035958 | 1989-02-01 | Examiner | |
| JP2-42419 | 1990-02-01 | Applicant | |
| JP2-140915 | 1990-05-01 | Examiner | |
| JP2-222546 | 1990-09-01 | Examiner | |
| JP4-100211 | 1992-04-01 | Applicant | |
| JP4-139728 | 1992-05-01 | Applicant |
Non-Patent Literature (26)
- Millman, ---, 1982, pp.278-282, ---.Applicant
- Oana, “16.3: A 240 X 360 Element Active Matrix LCD with Integrated Gate-Bus Drivers Using Poly-Si TFTS”, 1984, pp. 312-315, SID 84 Digest.Applicant
- Troxell, “16.7: Polysilicon Thin-Film Transistors on a Novel 800 <Glass Substrate”, 1986, pp. 298-300, SID 86 Digest.Applicant
- Wolf, “Silicon Processing For the VLSI Era”, ., pp.144-146, Lattice Press, vol. 2.Applicant
- Wu, “17.2: Performance of Polysilicon TFT Digital Circuit Fabricated with Various Processing Techniques and Device Architechtures”, 1990, pp.307-310, SID 90 Digest.Applicant
- Yamaguchi, “Drastically Improved Performance in Poly-Si TFT6 with Channel Dimensions Comparable to Grain Size”, 1989, pp. 353-355, IEDM 89.Applicant
- Fortuna et al., “Ion Beam Induced Si Crystallization from a Silicide Interface”, 1993, pp. 264, Appl. Surf. Sci., vol. 73.Applicant
- .,“Encyclopedia Semiconductor and Integrated Circuit”, ., pp. 272,.Applicant
- Daieisha, “Silicon Integrated Circuit Step Technics”, 1991, pp. 147-148, ---.Applicant
- Cammarata, “Silicide Precipitation and Silicon Crystallization in Nickel Implanted Amorphous Silicon Thin Films”, ., pp. 2133-2138, Journal of Materials Res., vol. 5.Applicant
- Caune, “Combined CW Laser and Furnace Annealing of Amorphous Si and GE in Contact with Some Metals”, ., pp. 597-604, Applied Surface Science, vol. 36.Applicant
- Dvurechenskii, “Transport Phenomena in Amorphous Silicon Doped by Ion Implantation of 3D Metals”, ., pp. 635-640, Phys. Stat. Sol.Applicant
- Fortuna, “In Situ Study of Ion Beam Induced Si Crystallization From a Silicide Interface”, ., pp. 264-267, Applied Surface Science, vol. 73.Applicant
- Gong, “Thermodynamic Investigations of Solid-State Si-MMetal Interactions LL. General Analysis of Si-Metal Binary Systems”, ., pp. 45242-4549, J. Appl. Phys., vol. 68.Applicant
- Green, “Method to Purify Semiconductor Wafers”, ., pp. 1612-1613, IBM Technical Disclosure Bulletin, vol. 16.Applicant
- Hayzelden, “In Situ Transmission Electron Microscopy Studies of Silicid-Mediated Crystallization of Amorphous Silicon”, ., pp. 225-227, Appl. Phys. Lett., vol. 60.Applicant
- Hemple, “Needle-Like Crystallization of NI Doped Amorphous Silicon Thin Films”, ., pp. 921-924, Solid State Communications, vol. 85.Applicant
- Kakkad, “Crystallized Si Films by Low-Temperature Rapid Thermal Annealing of Amorphous Silicon”, ., pp. 2069-2072, J. Appl. Phys., vol. 65.Applicant
- Kakkad, “Low Temperature Selective Crystallization of Amorphous Silicon”, ., pp. 66-68, Journal of Non-Crystalline Solids, vol. 115.Applicant
- Kawazu, “In Situ Study of Ion Beam Induced Si Crystallization From a Silicide Interface”, ., pp. 264-267, Applied Surface Science, vol. 73.Applicant
- Kuznetsov, “Transient Kinetics in Solid Phase Epitaxy of NI Doped Amorphous Silicon”, . ., pp. 261-264, Nuclear Instruments & Methods in Physics Research, vol. 96.Applicant
- Lee, “Low Temperature Poly-Si TFT Fabrication by Nickel-Induced Lateral Crystallization of Amorphous Silicon Films”, ., pp. 113-116, AM-LCD 95.Applicant
- Lee, “PD Induced Lateral Crystallization of Amorphous Si Thin Films”, ., pp. 1671-1673, Appl. Phys. Lett., vol. 66.Applicant
- Liu, “Selective Area Crystallization of Amorphous Silicon Films by Low-Temperature Rapid Thermal Annealing”, ., pp. 660-662, Appl. PHys. Lett., vol. 55.Applicant
- Liu, “Polycrystalline Silicon Thin Film Transistors on Corning 7059 Glass Substrates Using Short Time”, ., pp. 2554-2556, Appl. Phys. Lett., vol. 62.Applicant
- Daieisha, “Silicon Integrated Circuit Step Technics”, pp. 147-148, 108-111, 1991.Applicant