Dual-modulus prescaler for RF synthesizer

[0002] 1. Technical Field

[0003] The present invention relates to a dual-modulus prescaler for a RF frequency synthesizer, and more particularly to a dual-modulus prescaler for a RF frequency synthesizer, which may operate in a high speed and reduce energy consumption.

[0004] 2. Description of the Prior Art

[0005] Generally, a radio frequency (RF) synthesizer means a phase locked loop (hereinafter, referred as PLL), which outputs wider-ranged frequency by adjusting values of a programmable counter and is applied mainly to communication systems such as a portable personal mobile communication, an amateur communication, airplane, and so on.

[0006] FIG. 1 is a block diagram showing a receiver in the general portable personal mobile communication. As shown in the figure, the receiver includes a low-noise amplifier 10 for linearly amplifying at a predetermined ratio a signal received from a public network through an antenna 1, a variable frequency synthesizer 20 for generating an oscillation signal with a variable frequency, a first mixer 40 for generating a signal with a middle frequency by mixing a frequency of the signal amplified in the low-noise amplifier 10 and a frequency of the output signal of the variable frequency synthesizer 20, a middle frequency amplifier 60 for amplifying the signal with the middle frequency at a predetermined ratio and outputting the amplified signal, a fixed frequency synthesizer 80 for first and second oscillation signals with fixed frequencies, a second mixer 100 for outputting first and second mixed signals by mixing a frequency of the signal amplified in the middle frequency amplifier 60 and a frequency of the signal from the fixed frequency synthesizer 80, a low-pass filter 120 for filtering to pass a low frequency bandwidth of the first and second mixed signals, and an analog-digital (AD) converter 140 for converting an analog signal filtered in the low-pass filter 120 to a digital signal and outputting a baseband signal (BBS).

[0007] FIG. 2 is a block diagram for illustrating the general frequency synthesizer 20. As shown in the figure, the frequency synthesizer 20 includes a phase detector 21 for detecting phases of a reference frequency F_rand a feedback input frequency to generate an error signal voltage, a charge pump 22 for pumping a charge according to the error signal voltage, a loop filter 24 for integrating outputs of the charge pump 22 and controlling a PLL loop gain, a voltage controlled oscillator (VCO) 26 for outputting, as a clock signal CLK, a signal in an oscillation frequency F_ocontrolled in response to an error signal voltage, which eliminates noise from the loop filter 24, and a programmable frequency divider 28 outputting a frequency signal divided at a predetermined ratio in response to the clock signal CLK from the VCO 26 and feeding back the divided frequency signal as an input of the phase detector 21.

[0008] The programmable frequency divider 28 includes a dual-modulus prescaler 28afor dividing the clock signal CLK from the VCO in first and second modes with different dividing ratios in response to a feedback counting signal (MC) and outputting the divided clock signal CLK, a first counter 28bfor counting clock pulses divided in the dual-modulus prescaler 28ato output the count as an input frequency signal of the phase detector 21, and a second counter 28cfor counting clock pulses divided in the dual-modulus prescaler 28aand outputting a mode control signal (MC) according to the count to the dual-modulus prescaler 28a.

[0009] The frequency synthesizer 20 has a configuration that the loop filter 24 and the VCO are attached to outside of a PLL module having the phase detector 21, the charge pump 22 and the programmable frequency divider 28.

[0010] In the frequency synthesizer constructed as above, the output frequency F_obecomes a value multiplying the reference frequency F_rby a total dividing ratio (M) which is divided by the programmable frequency divider 28.

[0011] Such RF variable frequency synthesizer using a Pulse Swallow Method includes the programmable frequency divider 28 in which a total dividing ratio is M and which is composed of three elements: the dual-modulus prescaler 28aand the first and second counters 28b, 28c. At this time, the output frequency F_oof each element is determined by combinations of programmed counts of the elements.

[0012] Provided that a dividing ratio of the dual-modulus prescaler 28ais P and counts of the first and second counters 28b, 28care respectively N and S, the output frequency F_ois calculated as follows. $\begin{array}{cc}\begin{array}{c}{F}_o={\mathrm{M\_F}}_r\\ =\left(\mathrm{P\_N}+S\right)F_r\end{array}& \mathrm{Equation}1\end{array}$

[0013] where,

[0014] P=2ⁿ, (n=1, 2, - - - )

[0015] S=0˜(P−1)

[0016] N≧S.

[0017] The dual-modulus prescaler 28aat first divides the CLK frequency of the VCO 26 in the first and second modes having different dividing rates, for example P and P+1. In fact that the VCO 26 operates in the highest frequency in the frequency synthesizer, the dual-modulus prescaler 28aalso requires high speed operation.

[0018] Such high speed operation consumes much energy and the prescaler 28aoccupies most of the power consumed in the PPL module.

[0019] Therefore, the high speed operation and low energy consumption of the prescaler 28ais needed to the RF synthesizer for the mobile communications.

[0020] The prescaler 28acurrently used is implemented in a shift register ring method.

[0021] FIG. 3 is a block diagram showing the conventional prescaler 28aemploying the shift register ring method. As shown in the figure, the prescaler 28aincludes a high speed synchronous divider 28a-1 operating at a 4/5 dividing rate, a low speed asynchronous divider 28a-2 operating at a 32 dividing rate, and a logic gate 28a-3.

[0022] The synchronous divider 28a-1 includes first to third flip-flops FF1-FF3 which is synchronous with the CLK of the VCO 26, an inverter INV for inverting an output of the first flip-flop, a first NAND gate (ND1) for inverted-AND operating an output signal of the inverter INV and an inputted control signal CTR and outputting the operated signal as an input of the second flip-flop FF2, and a second NAND gate (ND2) for inverted-AND operating the output signals of the first and second flip-flops FF1, FF2 and outputs the operated signals as inputs of the third flip-flop FF3.

[0023] The output signal of the third flip-flop FF3 is fed back as an input of the first flip-flop FF1 as well as used as a synchronous signal of the asynchronous divider 28a-2.

[0024] The asynchronous divider 28a-2 includes five two-dividing flip-flops (FF4-FF8) for supplying an output Q as a synchronous signal of the next flip-flop and feeding back an inverse output /Q as an input thereof. The fourth flip-flop FF4 is synchronous with an output signal of the third flip-flop FF3.

[0025] The logic gate 28a-3 includes an AND gate for AND operating output signals of the two-dividing flip-flops FF4-FF8 and a mode control signal MC from the second counter 28c.

[0026] Operation of the dual-modulus prescaler 28aemploying the shift register ring method and constructed is explained below with reference to a timing diagram in FIG. 4.

[0027] The dual-modulus prescaler 28aselects a dividing rate according to a logic level of the mode control signal MC, which can be P or P+1. In other words, the dividing ratio is P when the mode control signal MC is a logic level “low”, or else the dividing ratio is P+1.

[0028] At first, a dividing operation at P(=2⁷=128) is same as a ripple counter. That is, because the AND gate of the decoder 28a-3 always outputs low when the mode control signal MC is selected as a logic level “low”, the control signal CTR become a logic level “low”. If the signal is inputted to the first and second ANAD gates ND1, ND2 of the synchronous divider 28a-1, the NAND gates output a logic level “high”. As a result, the synchronous divider 28a-1 becomes a four-divider having two flip-flops and an inverter. Therefore, as shown in FIG. 4, the synchronous divider 28a-1 operates in a four dividing mode (/4mode), which maintains one cycle for every four clock cycles (4CLK).

[0029] A 4-divided output of the synchronous divider 28a-1 is supplied to the asynchronous divider 28a-2, which operation division at a 32 dividing ratio, as a synchronous signal. Therefore, the asynchronous divider 28a-2, obtains a 128-divided signal.

[0030] Next, in a dividing operation at P+1(=2⁷+1=129), if outputs of all flip-flops FF4-FF8 of the asynchronous divider 28a-2, in state that a logic level of the mode control signal MC is “high”, the control signal CTR maintains a logic level “high” during 4 cycles of the clock CLK. If the signal is inputted to the first and second NAND gates ND1, ND2 of the synchronous divider 28a-1, the NAND gates operate like the inverter, resulting in 5-divider having three flip-flops, an inverter and a NAND gate. Therefore, the P+1 divider operates in a 5-dividing mode only for 4 clock cycles, as shown in FIG. 4.

[0031] When comparing a result of the 5-dividing mode with the 4-dividing mode, the 5-dividing mode becomes identical to the 4-dividing mode when delaying a logic level “high” signal of the 4-dividing mode as much as one cycle. When taking over the signal to the next asynchronous divider 28a-2, 1 clock cycle (1CLK) is delayed to obtain 129-divided signal.

[0032] However, such conventional dual-modulus prescaler employs many flip-flops, or 1 to 3 flip-flops, operated by an output frequency of a high speed VCO, which requires a large amount of energy for each flip-flops. In addition, because a drive capability of the VCO is limited due to abundant loads for each flip-flop, the prescaler requires more power. Moreover, a load amount, which the first flip-flop should drive, is more than that of a general asynchronous divider.

[0033] In addition, in the conventional dual-modulus prescaler, logic gates of the synchronous divider for making the P+1 dividing are used as delay elements. That is, the suitable P+1 dividing operation can be obtained only when a delay generated in the first flip-flop have an equational relation with a delay generated in the inverter and the first NAND gate during one cycle. $\begin{array}{cc}{t}_{\mathrm{dFF1}}+t_{\mathrm{dINV}}+t_{\mathrm{dND1}}<T& \mathrm{Equation}2\end{array}$

[0034] where T is a clock cycle, t_dFF1is a delay time of the first flip-flop, t_dINVis a delay time of the inverter and t_dND1is a delay time of the first NAND gate.

[0035] Furthermore, in the prior art, the synchronous divider generates delays twice as much as the asynchronous divider.

[0036] The present invention is designed to overcome drawbacks of the prior art. An object of the present invention is to provide a dual-modulus prescaler for a RF synthesizer, which may give more improved characteristics in operation rate and energy consumption aspects by implementing the dual-modulus prescaler, which is one component of the PPL module, with use of a selective latch technique which makes a selective latch latching a feedback signal thereof in an area where a latch control signal is enabled and makes a clock pulse from a voltage controlled oscillator passing as it is.

[0037] In order to accomplish the above object, the present invention provides a dual-modulus prescaler for a RF (Radio Frequency) synthesizer which has a voltage controlled oscillator (VCO) for generating a clock signal and a programmable counter for generating a mode control signal to select a frequency-dividing mode, the dual-modulus prescaler comprising a first frequency-dividing circuit for being synchronized to the clock signal to generate a latch control signal, latching the clock signal at a leading edge of the generated latch control signal, changing the frequency-dividing mode from a first frequency-dividing mode to a second frequency-dividing mode when latching the clock signal, and frequency-dividing and outputting the clock signal; a second frequency-dividing circuit for frequency-dividing the frequency divided signal from the first frequency-dividing circuit at a predetermined frequency-dividing ratio and outputting a plurality of frequency divided signals; and a logic operation circuit for logically operating a plurality of the frequency divided signals and the mode control signal to control the dividing mode of the first frequency-dividing circuit.

[0038] The first frequency-dividing circuit may include a first flip-flop circuit for being synchronized to the clock signal to generate the latch control signal; a latch for selectively latching the clock signal in a predetermined cycle of the clock signal at the leading edge of the latch control signal; a second flip-flop circuit for frequency-dividing an output signal of the latch at a predetermined frequency-dividing ratio to generate a first frequency divided signal; a third flip-flop for frequency-dividing the first frequency divided signal at a predetermined frequency-dividing ratio to output second and third frequency divided signals; and a first AND gate for AND operating the second and third frequency divided signals and the frequency-dividing mode control signal from the logic operation circuit to output the operated signal to an input terminal of the first flip-flop.

[0039] The latch preferably feeds back an output signal as an input thereof.

[0040] The second flip-flop may generate the first frequency divided signal, made by two frequency-dividing an output signal of the latch in response to a falling edge of the output signal of the latch.

[0041] The second flip-flop preferably feeds back an inverted output signal as an input thereof.

[0042] The third flip-flop may output the second frequency divided signal, which is made by dividing by two the first frequency divided signal in response to a falling edge of the first frequency divided signal, and the third frequency divided signal, which is made by delaying the second frequency divided signal as much as a half cycle.

[0043] The third flip-flop preferably feeds back an inverted output signal of the first frequency divided signal as an input thereof.

[0044] The second frequency-dividing circuit may include a plurality of stages of asynchronous flip-flop circuits, which sequentially divide the second frequency divided signal at a predetermined frequency-dividing ratio and output a plurality of the frequency divided signals.

[0045] Preferably, one flip-flop of a plurality of the flip-flops outputs an output signal to a synchronous signal input terminal of a next flip-flop, and feeds back an inverted output signal to an input terminal of the flip-flop itself.

[0046] The first frequency-dividing circuit may perform a four frequency-dividing mode operation when the output signal of the first AND gate is in a first logic level, and perform a five frequency-dividing mode operation when the output signal of the first AND gate is enabled to a second logic level.

[0047] The logic operation circuit may include a second AND gate for AND operating a plurality of frequency divided signals from the second frequency-dividing circuit and the frequency-dividing mode control signal.

[0048] These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings, in which like components are referred to by like reference numerals. In the drawings:

[0049] FIG. 1 is a block diagram showing a receiver in a common portable personal mobile communication terminal;

[0050] FIG. 2 is a block diagram showing a general frequency synthesizer;

[0051] FIG. 3 is a block diagram showing a conventional dual-modulus prescaler using a shift register ring method;

[0052] FIG. 4 shows a timing diagram for illustrating operation of the conventional dual-modulus prescaler;

[0053] FIG. 5 is a block diagram showing a dual-modulus prescaler according to the present invention;

[0054] FIG. 6 shows a detailed circuit of a selective latch according to the present invention;

[0055] FIG. 7 shows a detailed circuit of a two divider flip-flop and a first flip-flop according to the present invention;

[0056] FIG. 8 shows a timing diagram for illustrating a delay operation of an output signal of the first flip-flop according to the present invention;

[0057] FIG. 9 shows a detailed circuit of one AND gate having first and second AND gates according to the present invention;

[0058] FIG. 10 shows a timing diagram for illustrating a dividing mode operation of the dual-modulus prescaler according to the present invention;

[0059] FIG. 11 shows a timing diagram for illustrating a swallowing operation of a clock pulse according to the present invention;

[0060] FIG. 12 shows a timing diagram for illustrating a swallowing operation of a positive clock pulse according to the present invention;

[0061] FIG. 13 shows a timing diagram for illustrating a swallowing operation of a negative clock pulse according to the present invention;

[0062] FIG. 14 is a wave diagram showing a latch control signal according to the present invention;

[0063] FIG. 15 is a wave diagram showing an output of the selective latch according to the present invention;

[0064] FIG. 16 is a wave diagram showing a divided signal in a first dividing mode operation according to the present invention;

[0065] FIG. 17 is a wave diagram showing a divided signal in a second dividing mode operation according to the present invention;

[0066] FIG. 18 is a wave diagram showing an output wave of the dual-modulus prescaler according to the present invention; and

[0067] FIG. 19 is a diagram for showing comparison of operation rates of dual-modulus prescaler according to the present invention.

[0068] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0069] FIG. 5 is a block diagram for illustrating a dual-modulus prescaler according to an embodiment of the present invention. A reference “CLK” indicates a clock signal that a voltage controlled oscillator VCO supplies, and “MC” indicates a mode control signal that a programmable counter provides for selecting a dividing mode.

[0070] The dual-modulus prescaler includes a first dividing unit 200 for generating a latch control signal LC with being synchronized with the clock signal CLK, selectively latching the clock signal CLK at a leading edge of the generated latch control signal LC for a predetermined cycle area, converting to a second dividing mode from a first dividing mode when latching the clock signal CLK, dividing the clock signal and then outputting the divided signal, a second dividing unit 220 for dividing the divided signal from the first dividing unit 200 at a predetermined ratio and then outputting a plurality of divided signals DS4-DS8, and an arithmetic and logic unit 240 for logically operating a plurality of the divided signals DS4-DS8 and the mode control signal MC, generating a control signal CTR to control the dividing mode of the first dividing unit 200 and then supplying the control signal CTR to the first dividing unit 200.

[0071] The first dividing unit 200 includes a first flip-flop FF1 for generating the latch control signal LC with being synchronized with the clock signal CLK, a latch L1 for selectively latching the clock signal CLK at a leading edge of the latch control signal LC for a predetermined cycle area, a second flip-flop FF2 for dividing the output signal of the latch L1 and then outputting a first divided signal DS1, a third flip-flop FF3 for dividing the output signal of the second flip-flop FF2 at a predetermined ratio and then outputting second and third divided signals DS2, DS3 through output terminals I, Q, and a first AND gate AND1 for AND operating the second and third divided signals DS2, DS3 and the control signal CTR from the arithmetic and logic unit 240 and then outputting the operated signal to an input terminal D of the first flip-flop FF1.

[0072] The latch L1 outputs a latch signal SL through the output terminal Q to feed back the latch signal SL to a first input terminal (a) thereof and receives the clock signal CLK at a second input terminal (b).

[0073] The second flip-flop FF2 generates the first divided signal DS1 by 2-dividing the latch signal SL of the latch L1 in response to a falling edge of the latch signal SL of the latch L1 and feeds back an inverse output signal of the first divided signal DS1 to an input terminal D thereof through an inverse output terminal Qb.

[0074] The third flip-flop FF3 outputs the second divided signal DS2 which is made by 2-dividing the first divided signal DS1, and the third divided signal, made by delaying the first divided signal DS1 as much as a half cycle. The third flip-flop FF3 also outputs an inverse output signal of the first divided signal DS1 through an inverse output terminal Qb to feed back the inverse output signal as an input thereof.

[0075] The second dividing unit 220 includes a plurality of flip-flops FF4-FF8, which sequentially divides the second divided signal DS2 and outputs a plurality of the divided signals DS4-DS8. A plurality of the flip-flops FF4-FF8, respectively, output an output signal to an input terminal C of the next flip-flop in an asynchronous method and output an inverse output signal through an inverse output terminal Qb to feed back the inverse output signal to an input terminal D thereof.

[0076] The arithmetic and logic unit 240 includes a second AND gate AND2 for AND operating a plurality of the divided signals DS3-DS7 from the second dividing unit 220 and the mode control signal MC.

[0077] FIG. 6 shows a detailed circuit of the selective latch L1 according to an embodiment of the present invention. In the figure, a reference symbol “B1” indicates a first bias voltage input terminal, “B2” indicates a second bias voltage input terminal, “MP1” and “MP2” indicate PMOS (P-channel Metal Oxide Semiconductor) transistors, “MN1” and “MN7” indicate NMOS (N-channel Metal Oxide Semiconductor) transistors, “a” indicates a first input terminal, “ab” indicates an inverse first input terminal, “b” indicates a second input terminal, “bb” indicates an inverse second input terminal, “c” indicates a third input terminal, “cb” indicates an inverse third input terminal, “Q ” indicates an output terminal, and “Qb” indicates an inverse output terminal.

[0078] The selective latch L1 has a differential IO (input-output) terminal in a current mode logic (CML) shape, and forms a feedback circuit by that the output terminal Q is combined to a gate terminal of the NMOS transistor MN1, the inverse output terminal Qb is combined to a gate terminal of the NMOS transistor MN2, the output terminal Q is combined to a gate terminal of the NMOS transistor MN2, and the inverse output terminal Qb is combined to a gate terminal of the NMOS transistor MN1.

[0079] FIG. 7 shows a detailed circuit of the first flip-flop FF1 which is a sampling flip-flop, and 2-divider flip-flops FF2, FF3, FF4, FF5, FF6, FF7, FF8 according to an embodiment of the present invention. A reference symbol “B1” indicates a first bias voltage input terminal, “B2” indicates a second bias voltage input terminal, “MP3” to “MP6” indicate PMOS transistors, “MN8” to “MN21 ” indicate NMOS transistors, “D” indicates an input terminal, “Db” indicates an inverse input terminal, “Q” indicates an output terminal, “Qb” indicates an inverse output terminal, “ck” indicates a clock signal input terminal, and “ckb” indicates an inverse clock signal input terminal, respectively.

[0080] The 2-divider flip-flop includes a master latch and a slave latch, each of which is designed in a current mode logic CML shape and has input and output terminals in a differential type. The output terminal Q and the inverse output terminal Qb of the flip-flop are respectively connected to the inverse input terminal Db and the input terminal D.

[0081] The 2-divider flip-flops FF2, FF3, FF4, FF5, FF6, FF7, FF8 operates in a transparent mode when the clock signal CLK is a logic level “high” and operates in a latch mode when the clock signal CLK is a logic level “low”.

[0082] The latch L1 employs same flip-flop as one used in the 2-divider, which has two functions described below.

[0083] At first, the flip-flop synchronizes an output signal of the first AND gate AND1, asynchronously generated, with the clock signal.

[0084] Next, the flip-flop delays the clock signal as much as one cycle by sampling the output of the first AND gate AND1, caused when the output of the third flip-flop FF3 is a logic level “high”.

[0085] If the first flip-flop FF1 does not exist, the output of the latch L1 maintains its value at the instant of latching the clock signal CLK by the output signal of the first AND gate AND1.

[0086] FIG. 8 is a timing diagram for illustrating the delaying operation of the latch control signal LC of the first flip-flop FF1 according to an embodiment of the present invention. In the figure, a reference symbol “T_CLK” indicates a falling time of the clock signal CLK, which makes a falling edge of the latch control signal LC and “T_LC” indicates a leading time of the latch control signal LC.

[0087] As shown in the figure, the falling edge of the latch control signal LC for releasing the latch operation is a falling edge next to the falling edge of the clock signal CLK, which initiates the latch operation. Therefore, if latching the clock signal CLK itself before the falling edge of the clock signal is made, the latch operation cannot be released.

[0088] Therefore, in order to make a falling edge of the clock signal CLK for completing the latching operation as described above, the output signal of the first AND gate AND1 should be delayed as much as one cycle. That is, it should ensure an equation 3 below. $\begin{array}{cc}{T}_{\mathrm{CLK}}<T_{\mathrm{LC}}& \mathrm{Equation}3\end{array}$

[0089] FIG. 9 is a detailed circuit showing one of AND gates composing the first AND gate AND1 and the second AND gate AND2 according to an embodiment of the present invention. A reference symbol “B1” indicates a first bias input terminal, “B2” indicates a second bias input terminal, “MP7” and “MP8” indicate PMOS transistors, “MN22” and “MN27” indicate NMOS transistors, “a” and “b” indicate first and second input terminals, “ab” and “bb” indicate an inverse first input terminal and an inverse second input terminal, “Q” indicates an output terminal, and “Qb” indicates an inverse output terminal, respectively.

[0090] FIG. 9 shows one AND gate. But, in the embodiment of the present invention, two AND gates are combined to construct the first AND gate AND1 and five AND gates are combined to construct the second AND gate AND2.

[0091] Operations of the present invention as construct above are now described below with reference to timing diagrams in FIG. 9 to FIG. 12.

[0092] FIG. 10 is a timing diagram for illustrating a dividing mode operation of the dual-modulus prescaler according to an embodiment of the present invention.

[0093] Referring to the figure, if the first AND gate AND1 generates an output signal DTR in a logic level “low” when the clock signal CLK is supplied to the latch L1 of the first dividing unit 200, the latch L1 passes the input clock signal CLK as it is in response to the latch control signal LC from the first flip-flop FF1 and then supplies the clock signal CLK to the input terminal of the second flip-flop FF2 which is a 2-divider in the next step.

[0094] On the contrary, if the output signal DTR of the first AND gate AND1 changes from a logic level “low” to “high” with the clock signal being supplied, the latch L1 latches a proceeding clock signal in an area that the output signal DTR of the first AND gate AND1 maintains a logic level “high”. Then, the latch L1 generates an output signal SL in a logic level “low” and then gives the output signal SL to a synchronous input terminal of the second flip-flop FF2 in the next step.

[0095] Therefore, the present invention swallows a positive pulse A of the clock signal, dot-lined in FIG. 9, in an area that the output signal DTR of the AND gate AND1 maintains a logic level “high”, and then supplies the positive pulse A to the synchronous input terminal of the second flip-flop FF2. At this time, the term “swallow” means eliminating the clock pulse.

[0096] On the other hand, the second flip-flop FF2 2-divides the signal from the latch L1 and supplies the divided signal to a synchronous input terminal of the third flip-flop FF3.

[0097] Because the second and third flip-flops FF2, FF3 performs 2-dividing, when the output signal DTR of the AND gate AND1 maintains a logic level “low”, the third flip-flop FF3 of the first dividing unit 200 operates in a first dividing mode for generating 4-divided signals (P=4) at a timing area T1. On the other hand, when the output signal DTR of the AND gate AND1 is enabled to a logic level “high”, the first dividing unit 200 operates in a second dividing mode for generating 5-divided signals, which is a signal divided as much as P+1 at a timing area T2.

[0098] The third flip-flop FF3 of the present invention generates a second divided signal DS2 which is 4-divided, and a third divided signal DS3 which delays the second divided signal DS2 as much as a half cycle, and then supplies the second and third divided signals DS2, DS3 to the AND gate AND1. The third flip-flop FF3 also supplies the second divided signal DS2 to a synchronous input terminal of the fourth flip-flop FF4 of the second dividing unit 220 as a synchronous signal.

[0099] A plurality of the flip-flops FF4-FF8 composing the second dividing unit 220 of the present invention are respectively 2-dividers and perform the dividing operation in a asynchronous method.

[0100] In the second dividing unit 220, the fourth flip-flop FF4 2-divides the second divided signal DS2 and output the third divided signal DS3. The fourth flip-flop FF4 supplies the third divided signal DS3 to a synchronous input terminal of the fifth flip-flop FF5. The fifth to eighth flip-flops FF5-FF8 output divided signals DS4-DS8 with same operation as the fourth flip-flop FF4 in which the divided signal DS8 of the eighth flip-flop FF8 is supplied to the first and second counters 28b,28cin FIG. 1.

[0101] On the other hand, the second AND gate AND2 of the arithmetic and logic unit 240 receives the mode control signal MC from the second counter 28cand receives the divided signals DS4-DS8 from the second dividing unit 220. The second AND gate AND2 then AND operates the mode control signal MC and the divided signals DS4-DS8 to generate a control signal CTR.

[0102] FIG. 11 is a timing diagram for illustrating a pulse swallowing process according to an embodiment of the present invention. As shown in the figure, if the second and third divided signals DS2, DS3 are in a logic level “high” in an area that the control signal CTR is in a logic level “high”, the first AND gate AND1 outputs the signal DTR in a logic level “high” for one clock cycle. The output signal DTR is supplied to an input terminal D of the first flip-flop FF1 which is synchronized with the clock signal CLK. The output signal DTR is also applied to a synchronous input terminal© of the latch L1 as a latch control signal LC after delaying for a predetermined time in the first flip-flop FF1

[0103] Then, the latch L1 latches the clock signal CLK supplied synchronous with a leading edge of the latch control signal LC. At this time, because the latch control signal LC maintains a logic level “high” only for one cycle of the clock signal CLK, as a result, a pulse of the clock signal CLk is eventually eliminated to obtain the P+1 dividing.

[0104] On the other hand, as shown in FIG. 11, a propagation delay is generated as much as t_d1+t_d2+t_d3+t_d4until the AND gate generates an output signal because an output signal SL of the latch L1 is delayed as much as t_d1, the divided signal DS1 divided by the second flip-flop FF2 is delayed as much as t_d2to a falling edge of the output signal SL of the second flip-flop FF2 the divided signal DS2 of the second flip-flop FF3 is delayed as much as td₃to a falling edge of the divided signal DS1 of the second flip-flop FF2 the output signal DTR of the AND gate AND1 is delayed as much as td₄to a leading edge of the divided signal DS3 of the third flip-flop, the latch control signal LC is delayed as much as t_d5to a falling edge of the clock signal supplied in an area that the output signal DTR of the AND gate AND1 maintains a logic level “high”. However, the output signal is synchronized again in the latch L1 by the clock signal CLK in the present invention, only the t_d5gives an important effect on the propagation delay. If the latch L1 having a pulse swallow logic may eliminate only the positive pulse of the clock signal, the Equation 4 below should be satisfied for ensuring suitable operations of the dual-modulus prescaler. $\begin{array}{cc}{t}_{\mathrm{d5}}<\frac{T}{2}& \mathrm{Equation}4\end{array}$

[0105] where t_d5is a delay time of the latch control signal LC and T is a cycle of the clock signal CLK.

[0106] However, the conditions exhibited in the Equation 3 are not easily ensured due to such as change of the process. In the present invention, though such conditions are not satisfied, the operation of the dual-modulus prescaler is not influenced. That is, the present invention may always eliminate one pulse of the clock pulse CLK because the latch L1 latches the feedback signal whether the feedback signal is in a logic level “high” or “low” when the output signal of the first flip-flop FF1 is just enabled through the propagation t_d5of the first flip-flop FF1 is larger than T/2. If using the selective latching technique, all of positive and negative pulses of the clock signal CLK may be swallowed.

[0107] Therefore, because the propagation acts as latency only and ensures a certain latency for whole processes, the present invention may obtain a periodical P+1 dividing operation.

[0108] On the other hand, the latching operation of the latch L1, as shown in FIG. 11, starts at a point delayed as much as t_d6at a leading edge of the latch control signal and ends after delaying for a predetermined time at a falling edge of the latch control signal.

[0109] FIG. 12 is a timing diagram showing the swallowing process of the positive clock pulse and FIG. 13 is a timing diagram showing the swallowing process of the negative clock pulse according to an embodiment of the present invention. This figures may be easily understood in the above clock pulse swallowing process and not described in detail.

[0110] FIG. 14 shows wave shapes of the output signal DTR of the AND gate AND1 and the latch control signal LC of the first flip-flop FF1. As shown in the figure, the latch control signal LC is delayed as much as one cycle to the output signal DTR of the AND gate AND1.

[0111] FIG. 15 shows a wave shape of the output signal SL of the latch L1 according to an embodiment of the present invention. In the figure, it can be seen that the clock signal CLK is latched from a logic level “high” to “low”.

[0112] FIG. 16 shows a wave shape of the divided signal in the first dividing mode operation according to an embodiment of the present invention. The figure shows the divided signals, which are two frequency-divided, four frequency-divided and eight frequency-divided.

[0113] FIG. 17 shows a wave shape of the divided signal in the second dividing mode operation according to an embodiment of the present invention. The figure shows the divided signals, which are three frequency-divided, five frequency-divided and nine frequency-divided.

[0114] FIG. 18 shows a wave shape of a final output signal of the dual-modulus prescaler according to an embodiment of the present invention. In the figure, it can be easily understood that a dividing ration depends on the mode control signal MC, which determines the dividing ratio of the dual-modulus prescaler. That is, in an area that the mode control signal MC is in a logic level “high”, the prescaler operates the P dividing, or 128 frequency-dividing, which makes it unnecessary to latch the clock signal CLK and so the output signal of the first flip-flop FF1 does not appear. On the other hand, if the mode control signal MC becomes in a logic level “low”, it would be understood that the prescaler operates the P+1 dividing, or 129 frequency-dividing, which makes the output signal of the first flip-flop FF1 be enabled once per 129 frequency-dividing.

[0115] FIG. 19 shows a simulated result which compares operating ratios of the conventional dual-modulus prescaler using the shift ring method and the dual-modulus prescaler in an asynchronous type of the present invention. The figure shows change of an action frequency F for a line voltage Vdd.

[0116] As shown in the figure, when the line voltage Vdd is 2.7V, a maximum action frequency is 2.9 GHz in the prior art and 3.2 GHz in the present invention.

[0117] When comparing energy consumption, the prior art consumes 28.3 mW and the present invention consumes 22.6 mW at an action frequency of 2.6 GHz.

[0118] Therefore, it is understood that the present invention has improved in aspects of action rate and energy consumption.

[0119] In the future, it is inevitable that the frequency band becomes higher and therefore consumption energy becomes increased to used the frequency, which is a limited resource. In such a circumstance, if being applied to the PLL module in a RF band, the present invention may improve the action rate up to 17% and reduce the energy consumption down to 20%.

[0120] Though specific embodiments such as a 4/5 divider and 32-divider are described and shows, it is apparent to the person skilled in the art that any change or modification will be possible.

[0121] It should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

[0122] As described above, the present invention may give more improved characteristics in operation rate and energy consumption aspects by implementing the dual-modulus prescaler, which is one component of the PPL module with use of a selective latch technique which makes a selective latch latching a feedback signal thereof in an area where a latch control signal is enabled and makes a clock pulse from a voltage controlled oscillator passing as it is, and may give another effect that solves the delay problems in an asynchronous configuration by enabling to eliminate both positive and negative pulses of the clock signal.