Charge pump DC/DC converters with reduced input noise

[0002] This invention relates to charge pump DC/DC converters. More specifically, this invention relates to charge pump DC/DC converters with reduced noise at the input voltage source.

[0003] A charge pump DC/DC converter is a power supply circuit that provides a regulated output voltage to a load from an input voltage source. One type of charge pump DC/DC converter is a switching DC/DC converter power supply that uses switches to convert the input voltage to a regulated output voltage. The switches are operated in sequence to first charge a capacitor from the input voltage and then transfer the charge to the output.

[0004] However, one of the most common drawbacks of switching power supplies is the noise induced on the input voltage source due to fluctuations or variations in the current drawn by the converter power supply. When current flows from the input voltage to the capacitor, the input voltage is loaded causing it to decrease slightly. When the capacitor is decoupled from the input voltage, the input voltage rises. These voltage changes appear as noise on the input voltage bus. The magnitude of these changes in the input voltage level depends upon the equivalent series resistance of the input voltage source and the magnitude of the changes in the input current.

[0005] Certain applications such as cellular telephones, precision instrumentation, etc. are sensitive to noise generated on the input voltage. Therefore, noise on the input voltage caused by a power supply must be filtered to prevent degraded electrical performance in other circuitry that is powered from the same input voltage source.

[0006] It would therefore be desirable to provide a charge pump DC/DC converter that has reduced noise on the input voltage source.

[0007] It would therefore be desirable to provide a charge pump DC/DC converter with a substantially constant input current.

[0008] It is an object of the present invention to provide a charge pump DC/DC converter that has reduced noise on the input voltage source.

[0009] It is an object of the present invention to provide a charge pump DC/DC converter with a substantially constant input current.

[0010] These and other objects of the present invention are provided by charge pump DC/DC converters including circuitry to reduce variations in the input current, and methods for using the same. The circuitry may include an adjustable resistor, current mirror, or current mirrors coupled to the input voltage, and feedback loop circuitry. The feedback loop circuitry is coupled to the output voltage, and responds to changes in the output voltage to control the output current of the charge pump to maintain the output voltage at the regulated value. Additional circuitry may be added to charge pumps of the present invention to provide a substantially constant input current during the blanking intervals when all of the switches are open. Charge pump DC/DC converters of the present invention include buck and boost converters.

[0011] The above-mentioned objects and features of the present invention can be more clearly understood from the following detailed description considered in conjunction with the following drawings, in which the same reference numerals denote the same structural elements throughout, and in which:

[0012] FIG. 1A is a schematic diagram of a prior art charge pump DC/DC converter;

[0013] FIG. 1B is a graph of the input current for the charge pump DC/DC converter shown in FIG. 1A;

[0014] FIG. 2A is a schematic diagram of another prior art charge pump DC/DC converter;

[0015] FIG. 2B is a graph of the input current for the charge pump DC/DC converter of FIG. 2A;

[0016] FIG. 3A is a schematic of a boost charge pump DC/DC converter of the present invention;

[0017] FIG. 3B is a graph of the input current and clock signals for the boost charge pump DC/DC converter of FIG. 3A;

[0018] FIG. 4A is a schematic of another boost charge pump DC/DC converter of the present invention;

[0019] FIG. 4B is a graph of the input current for the boost charge pump DC/DC converter of FIG. 4A;

[0020] FIG. 4C is another graph of the input current for the boost charge pump DC/DC converter of FIG. 4A;

[0021] FIG. SA is a schematic of another boost charge pump DC/DC converter of the present invention;

[0022] FIG. 5B is a graph of the input current for he boost charge pump DC/DC converter of FIG. 5A;

[0023] FIG. 6A is a schematic of a buck charge pump C/DC converter;

[0024] FIG. 6B is a graph of the input current and lock signals for the buck charge pump DC/DC converter of FIG. 6A;

[0025] FIG. 7A is a schematic of a buck charge pump DC/DC converter of the present invention;

[0026] FIG. 7B is a graph of the input current for the buck charge pump DC/DC converter of FIG. 7A;

[0027] FIG. 8A is a schematic of another boost charge pump DC/DC converter of the present invention;

[0028] FIG. 8B is a graph of the input current and clock signals for the boost charge pump DC/DC converter of FIG. 8A;

[0029] FIG. 9A is a schematic of another buck charge pump DC/DC converter of the present invention; and

[0030] FIG. 9B is a graph of the input current for the buck charge pump DC/DC converter of FIG. 9A.

[0031] One previously known charge pump DC/DC converter 10 is shown in FIG. 1A. Charge pump 10 has capacitor 8 and switches S1, S2, S3, and S4. Charge pump 10 supplies a regulated voltage V_OUTat an output node from input voltage V_IN. The equivalent series resistance of output capacitor 9 is represented by resistor 12, and resistor 11 represents a load. Switches S1/S3 are switched out of phase with switches S2/S4 by clock signals V_CLKand V_CLKB, respectively.

[0032] Circuit 10 also has resistors 13A and 13B, reference voltage source 14, and hysteretic comparator 16. When comparator 16 senses that V_OUThas risen to a voltage threshold set by reference 14, the output of comparator 16 goes HIGH causing oscillator 18 to stop so that switches S1-S4 remain open and no charge is transferred to V_OUTfrom V_IN. When V_OUTfalls below the threshold of comparator 16, its output goes LOW, and oscillator 18 resumes the switching of switches S1-S4.

[0033] The input current into circuit 10 is represented by I_INand is shown in graphical form in FIG. 1B. I_INvaries substantially as switches S1-S4 are opened and closed, and is zero between times t0 and tx when the output of comparator 16 is HIGH. The large variations in I_INcaused by circuit 10 as shown in FIG. 1B produce variations in V_INthat correspond to undesirable low frequency noise. Low frequency noise tends to be very difficult and impractical to filter because very large and expensive filter components are needed to remove low frequency noise.

[0034] Previously known charge pump DC/DC converter is shown in FIG. 2A. Circuit 20 has capacitor 8, adjustable resistor 26, oscillator 25, and switches S1, S2, S3, and S4. Oscillator 25 provides clock signals V_CLKand V_CLKBthat control the opening and closing of switches S1-S4 as discussed above with respect to FIG. 1A. Circuit 20 also has resistor divider 21A/21B, amplifier 24, and reference voltage source 22. Amplifier 24 varies the resistance of adjustable resistor 26 in response to the voltage at its non-inverting input to maintain V_OUTat the regulated voltage. Adjustable resistor 26 may be a field effect transistor (such as an N-channel MOSFET) that is operated in its linear region.

[0035] Input current I_INis shown in FIG. 2B for circuit 20. At time t1, switches S2/S4 are closed and I_INflows through adjustable resistor 26. Resistor 26 limits the current and reduces the spike input current I_IN. The charge stored in capacitor 8 is limited by resistor 26 when switches S2/S4 are conducting. However, at time t3 when switches S2/S4 are open and S1/S3 are closed, the current spike is still undesirably large. Circuit 20 has less noise on the input voltage source because of the reduced input current when S2/S4 conduct. Nevertheless, the variations in I_INcaused by circuit 20 still produce undesirably large input voltage noise characteristics in the low frequency range (i.e., at the switching frequency). Undesirable higher frequency noise is caused by variations in the input current during each blanking interval (e.g., between times t2 and t3) when all of the switches are open. Another previous known charge pump converter is the LT1054 discussed in LTC's (Linear Technology Corporation's) 1994 databook.

[0036] Charge pump DC/DC converters of the present invention may include control circuitry coupled to the input voltage that reduces variations in the input current. The control circuitry controls the input current during each phase of a switching cycle in order to reduce voltage fluctuations on the input voltage source that cause low frequency noise. A control circuit including an amplifier and a resistor divider coupled to the output voltage adjusts the current through the control circuitry so that the output current of the converter matches the load current and the output voltage remains at the regulated value. The control circuitry may include an adjustable resistor, a current mirror, or current mirrors.

[0037] Charge pump DC/DC converter 30 of the present invention is shown in FIG. 3A. Converter 30 has capacitor 8, oscillator 25, adjustable resistor 38, and switches S1, S2, S3, and S4. Switches S1-S4 (and all other switches discussed with respect to the present invention) may comprise FETs (such as MOSFETs) or BJTs (bipolar junction transistors). The circuit components are coupled in a boost arrangement so that converter 30 regulates an output voltage V_OUTthat is higher than V_IN. Circuit 30 provides an output current to load 11 and maintains V_OUTat the regulated voltage. Output capacitor 9 is coupled to V_OUT. Oscillator outputs clock signals V_CLKand V_CLKBwhich are digital periodic pulse waveforms that control the opening and closing of switches S1, S2, S3, and S4. Clock signals V_CLKand V_CLKBare shown in FIG. 3B. V_CLKand V_CLKBare out of phase with each other, and include brief blanking intervals when both clock signals are LOW and all four switches are open (e.g., between times t2 and t3) to prevent shorting V_INor capacitor 8 to ground or V_OUT.

[0038] Switches S2/S4 are closed (i.e., conducting current) when V_CLKBis HIGH, for example, between times t1 and t2. Switches S2/S4 are open (i.e., not conducting current) when V_CLKBis LOW. Switches S1/S3 are closed (i.e., conducting current) when V_CLKis HIGH, for example, between times t3 and t4. Switches S1/S3 are open (i.e., not conducting current) when V_CLKBis LOW. When switches S2/S4 are closed and switches S1/S3 are open, input current I_INflows from input voltage V_INthrough adjustable resistor 38 and switch S4 to capacitor 8. An illustrative graph of the input current I_INfor circuit 30 is shown in FIG. 3B, wherein switches S2/S4 are closed between times t1 and t2. When switches S2/S4 close at time t1, I_INincreases rapidly (i.e., spikes). Between times t1 and t2, current I_INramps down according to the time constant determined by capacitor 8 and the series resistance of switches S2/S4 and resistor 38. By limiting current I_IN, adjustable resistor 38 reduces the input current spikes at time t1, so that variations in input current I_INare reduced during the first half of each switching cycle between t1 and t2, thereby reducing undesirable low frequency noise on the input voltage.

[0039] When switches S1/S3 are closed and switches S2/S4 are open, input current I_INflows from input voltage V_INthrough adjustable resistor 38 and switch S3 to capacitor 8, and current flows from capacitor 8 through switch S1 to the load. Switches S1 and S3 are closed between times t3 and t4 in FIG. 3B. When switches S1/S3 close at time t3, I_INspikes. Between times t3 and t4, current I_INramps down according to the time constant determined by capacitor 8 and the series resistance of switches S1/S3 and resistor 38. Adjustable resistor 38 reduces the input current spike at time t3 relative to circuit 20, so that variations in input current I_INare reduced between times t3 and t4 during the second half of each switching cycle, thereby reducing undesirable low frequency noise at the input voltage. Thus, adjustable resistor 38 controls the input current through capacitor 8 and all four switches during each phase of the clock cycle.

[0040] The current through a capacitor is determined by the following standard equation: $\begin{array}{cc}I=C\frac{dV}{dt}& \left(1\right)\end{array}$

[0041] The current through a capacitor is determined by the following standard equation: $\begin{array}{cc}I=C\frac{dV}{dt}& \left(1\right)\end{array}$

[0042] The charge that is added to capacitor 8 from V_INwhen switches S2 and S4 are closed equals the charge that is transferred to the load when switches S1 and S3 are closed, during a steady state condition (i.e., constant load current). The change in voltage across capacitor 8 (dV_tx) when S2 and S4 are closed equals the change in voltage across capacitor 8 (dV_ty) when S1 and S3 are closed during a steady state. Setting these quantities equal to each other from equation (1) it can be seen that: $\begin{array}{cc}d{V}_{\mathrm{tX}}=d{V}_{\mathrm{tY}}=\frac{I_{\mathrm{R38}}}{C_8}{t}_x=\frac{I_{\mathrm{R38}}}{C_8}{t}_Y& \left(2\right)\end{array}$

[0043] where C₈is the capacitance of capacitor 8, t_xis the time period that switches S2 and S4 are closed in each switching cycle, and t_yis the time period that switches S1 and S3 are closed in each switching cycle. I_R38is the average current through resistor 38, which is about the same during both time periods. Solving equation (2), it can be seen that t_x=t_y. Therefore, the optimum duty cycle for switches S1-S4 is 50% (ignoring the relatively brief blanking interval). Times t_xand t_yare determined by clock signals V_CLKBand V_CLK, respectively.

[0044] The average output current I_OUTof converter (i.e., the average current through switch S1) equals the load current I_Lduring steady state operation. Current flowing through resistor 38 is only sent to V_OUTfor one half of each switching cycle when S1 is closed. During the other half of the switching cycle, the output current of converter 30 equals zero, because S1 is open. Therefore, the average current I_R38through adjustable resistor 38 must be twice the average output current I_OUT.

[0045] The average current through resistor 38 when switches S2 and S4 are closed is shown in the following equation: $\begin{array}{cc}{I}_{\mathrm{R38}}=\frac{V_{\mathrm{IN}}-V_{\mathrm{C8}}}{R_{38}}& \left(3\right)\end{array}$

[0046] where R₃₈is the resistance of adjustable resistor 38, and V_C8is the average voltage across capacitor 8. The average current through resistor 38 when switches S1 and S3 are closed is shown in the following equation: $\begin{array}{cc}{I}_{\mathrm{R38}}=\frac{V_{\mathrm{IN}}+V_{\mathrm{C8}}-V_{\mathrm{OUT}}}{R_{38}}& \left(4\right)\end{array}$

[0047] The current through resistor 38 equals the current through capacitor 8, because the two elements are coupled in series during both switching states. Therefore, the average current through resistor 38 when switches S2 and S4 are closed as shown by equation (3) equals the average current through resistor 38 when S1 and S3 are closed as shown by equation (4), during a steady state. Solving equations (3) and (4), it can be shown that V_C8equals one half of V_OUT.

[0048] Substituting I_R38=2I_OUT=2I_Land V_C8=V_OUT/2 into equation (3), one can derive the following equation: $\begin{array}{cc}{R}_{38}=\frac{V_{\mathrm{IN}}-\frac{V_{\mathrm{OUT}}}{2}}{2I_L}& \left(5\right)\end{array}$

[0049] The resistance value R₃₈of resistor 38 can be adjusted (by amplifier 34 as discussed below) according to equation (5) to supply the load current I_L, for selected values of V_INand V_OUT.

[0050] For the following discussion, equation (5) can be rearranged so that V_OUT=2V_IN−4I_LR₃₈. Assuming for purposes of illustration that R₃₈equals zero, V_INis applied across capacitor 8 when switches S2/S4 are closed. The voltage across a capacitor does not change instantaneously. Thus, when switches S1/S3 close, the voltage across capacitor 8 (V_IN) plus V_INis applied to V_OUT. Therefore, V_OUTequals 2V_INin the illustrative case where R₃₈equals zero for boost converter 30. This is the maximum value for V_OUT. When R₃₈has a positive non-zero value, V_OUTbecomes less than twice V_INaccording to the load current as shown by equation (5).

[0051] Charge pump 30 also includes a feedback loop that comprises a resistor divider including resistors 31A and 31B, reference voltage source 32, and amplifier 34. The feedback loop is used to control the resistance of variable resistor 38 and thereby control current delivered to output capacitor 9 and load 11 to regulate output voltage V_OUT. The resistance of resistor 38 is set by the feedback loop circuitry to be a function of the output current. Resistor divider 31A/31B provides a voltage feedback signal proportional to V_OUTat the non-inverting input of amplifier 34. Reference voltage source 32 provides a constant reference voltage signal at the inverting input of amplifier 34. Amplifier 34 amplifies the difference between the feedback signal and the reference voltage, and provides an amplified signal at its output to control the resistance of adjustable resistor 38. Adjustable resistor 38 may be a field effect transistor (such as an N-channel MOSFET) that is operated in its linear region.

[0052] When load current I_Lis less than the average output current delivered to load 11 by circuit 30, the excess charge is stored on output capacitor 9 and V_OUTincreases by a small amount. The voltage feedback signal increases proportionally with V_OUT, causing the voltage output signal of amplifier 34 to increase. This increases the resistance of adjustable resistor 38 causing the average output current of circuit 30 to decrease so that V_OUTis maintained at the regulated voltage.

[0053] When load current I_Lis greater than the average output current delivered to load 11 by circuit 30, charge is removed from output capacitor 9 by load current I_Land V_OUTdecreases by a small amount. The voltage feedback signal also decreases proportionally with V_OUT, causing the voltage output signal of amplifier 34 to decrease. The resistance of adjustable resistor 38 now decreases, causing the average output current of circuit 30 to increase so that V_OUTis maintained at the regulated voltage.

[0054] Instead of variable resistor 38, DC/DC charge pump converters of the present invention may include one or more current mirrors coupled to the input voltage that conduct a substantially constant input current in a steady state condition during each phase of the switching cycle. The current mirrors control the input current during each phase of the clock cycle (except during the blanking intervals) to reduce voltage fluctuations on the input voltage source that cause noise. A feedback loop including a transconductance amplifier and a resistor divider coupled to the output voltage adjusts the current through the current mirrors so that the output current of the converter matches the load current and the output voltage stays regulated.

[0055] An embodiment of the present invention using current mirrors is shown in FIG. 4A, wherein charge pump DC/DC converter 40 includes switches S1 and S2, flying capacitor 8, inverters 41 and 42, oscillator 25, and a current mirrors 54 and 55. Converter 40 also has feedback circuitry that includes a resistor divider formed by resistors 47A and 47B, reference voltage source 48, and transconductance amplifier 49. Converter 40 also includes NOR gate 60, n-channel FET 62, p-channel FETs 61, 63 and 64, and schottky diodes 67 and 68. Transistors 43-46, 50-53, and 61-64 may be, for example, MOSFETs. Switches S1 and S2 are coupled in a boost arrangement so that converter 40 regulates an output voltage V_OUTthat is higher than V_IN.

[0056] In circuit 40, switch S4 has been replaced by inverter 41 and current mirror 54, and switch S3 has been replaced by inverter 42 and current mirror 55. Transistors 43 and 44 form current mirror 54, because their gates are coupled together. Transistors 45 and 46 form current mirror 55, because their gates are coupled together. Transistors 44 and 46 may each comprise a single transistor or multiple transistors coupled together in parallel that have effective gate width-to-length areas that are N times the gate width-to-length areas of transistors 43 and 45, respectively. This provides current mirrors 54 and 55 with a current gain of N. Current mirror transistors 43-46 and other current mirror transistors discussed with respect to the present invention may be FETs or BJTs.

[0057] Oscillator 25 outputs digital clock signals V_CLKand V_CLKBas with the previous embodiment of FIG. 3A. Clock signals V_CLKand V_CLKBoscillate out of phase with a 50% duty cycle (and may have a blanking interval) as shown in FIG. 3B. Clock signal V_CLKcontrols the opening and closing of switch S1, and clock signal V_CLKBcontrols the opening and closing of switch S2.

[0058] In the first half of a switch cycle, V_CLKis LOW and V_CLKBis HIGH. When V_CLKBis LOW, transistor 52 is ON, transistor 53 is OFF, and switch S1 is open. When transistor 52 is ON, the output of inverter 42 and the gates of transistors 45 and 46 are HIGH (at V_IN), causing transistors 45 and 46 to be OFF. This turns OFF current mirror 55. Because V_CLKBis HIGH, transistor 50 is OFF, transistor 51 is ON, and switch S2 is closed. When transistor 51 is ON, the gates of transistors 43 and 44 are pulled down by the transconductance amplifier 49 output current I_GM, turning ON current mirror 54. Transconductance amplifier 49 sinks current I_GMthrough its output. Thus, when transistor 51 is ON, transistor 43 is ON and current I_GMflows from V_INthrough transistors 43 and 51 to ground through the output of transconductance amplifier 49. Transistor 44 is also ON when transistor 51 is ON, and current flows from V_INthrough transistor 44 charging up capacitor 8.

[0059] Because the gate width-to-length area of transistor 44 is N times the gate width-to-length area of transistor 43, the current that flows through transistor 44 equals N times the current I_GMthat flows through transistor 43. So long as transconductance amplifier 49 sinks a constant current I_GMduring a steady state load current, the current through transistors 43 and 44, and the input current I_INremains constant while switch S2 is closed. I_INis defined by the following equation when switch S2 is closed:

[0060] I_IN=I_M43+I_M44=I_GM(1+N)  (6)

[0061] where I_M43is the current through transistor 43, I_M44is the current through transistor 44, I_GMis the output current of amplifier 49, and I_M43equals I_GMwhen transistor 43 is ON.

[0062] The source of transistor 50 is coupled to the cathodes of schottky diodes 67 and 68 as shown in FIG. 4A. The anode of diode 67 is coupled to V_IN, and the anode of diode 68 is coupled to V_OUT. Thus, when transistor 50 is ON, the source of transistor 50 is coupled to the larger of V_INor V_OUTthrough diodes 67 or 68. In circuit 40, V_OUTis generally larger than V_IN, because it is a boost converter.

[0063] During the second half of a switch cycle, V_CLKis HIGH and V_CLKBis LOW. When V_CLKBis LOW, transistor 50 is ON, transistor 51 is OFF, and switch S2 is open. When transistor 50 is ON, the output of inverter 41 and the gates of transistors 43 and 44 are HIGH (at V_OUT), causing transistors 43 and 44 to be OFF. This turns OFF current mirror 54. Because V_CLKis HIGH, transistor 52 is OFF, transistor 53 is ON, and switch S1 is closed. When transistor 53 is ON, the gates of transistors 45 and 46 are pulled LOW by the transconductance amplifier 49 output current I_GM, turning ON current mirror 55. Thus, when transistor 53 is ON, transistor 45 is ON and current I_GMflows from V_INthrough transistors 45 and 53 to ground through the output of transconductance amplifier 49. Transistor 46 is also ON when transistor 53 is ON, causing current to flow from V_INthrough transistor 46 to capacitor 8, and from capacitor 8 through switch S1 to V_OUT.

[0064] Because the gate width-to-length area of transistor 46 is N times the gate width-to-length area of transistor 45, the current that flows through transistor 46 equals N times the current I_GMthat flows through transistor 45. So long as transconductance amplifier 49 sinks a constant current I_GMduring a steady state load current, the current through transistors 45 and 46, and the input current I_INremain constant while switch S1 is closed. I_INis defined by equation (7) when switch S1 is closed:

[0065] I_IN=I_M45+I_M46=I_GM(1+N)  (7)

[0066] where I_M45is the current through transistor 45, I_M46is the current through transistor 46, I_GMis the output current of amplifier 49, and I_M45equals I_GMwhen transistor 45 is ON. As shown by equations (6) and (7), current IN when switch S2 is closed equals current I_INwhen S1 is closed.

[0067] If transconductance amplifier 49 sinks a constant current I_GM, I_INremains constant when either of switches S1 or S2 are closed and conducting current. Thus, current mirrors 54 and 55 control the current through capacitor 8 and the switches during each phase of the clock signal. During the blanking interval when V_CLKand V_CLKBare LOW concurrently, and switches S1 and S2 are open, I_INis zero (without NOR gate 60 and transistors 61-64 which are discussed below). Therefore, I_INvaries between a constant value and zero every half cycle of V_CLKduring a steady state as shown, for example, in the graph of FIG. 4B. The circuit of FIG. 4A, therefore, reduces low frequency noise on the input voltage source by maintaining the input current I_INat a constant value when switches S1 and S2 are closed.

[0068] The average output current I_OUTof converter 40 (i.e., the average current through switch S1 over time) equals the load current I_Lduring a steady state. When switch S1 is open, the instantaneous output current of converter 40 equals zero. During the other half of the switching cycle, output current flows to V_OUTthrough transistor 46 when S1 is closed. Therefore, the current through transistor 46 must equal twice the load current I_L. The current through transistor 46 equals N times I_GM, as discussed above. The relationship between the load current and I_GMis shown by the following equation:

[0069] I_L=2N·I_GM  (8)

[0070] As the load current changes, I_GMcan be adjusted by amplifier 49 (discussed below) to match the load current according to equation (8).

[0071] The charge that is added to capacitor 8 from V_INwhen switch S2 is closed equals the charge that is transferred to the load when switch S1 is closed, during a steady state condition. Assuming for purposes of illustration that R_DSONof transistors 44 and 46 equals zero, V_INis applied across capacitor 8 when switch S2 is closed. When switch S1 closes, the voltage across capacitor 8 (V_IN) plus V_INis applied to V_OUT. Therefore, V_OUTequals 2V_INin the illustrative case where the R_DSONfor transistors 44 and 46 equals zero for boost converter 40. This is the maximum value for V_OUT. As R_DSONis increased above zero in a steady state, V_OUTbecomes less than twice V_IN. Thus, V_OUT<2V_IN.

[0072] The change in voltage across capacitor 8 (dV_tx) when S2 is closed equals the change in voltage across capacitor 8 (dV_ty) when S1 is closed. Setting these quantities equal to each other from equation (1) it can be seen that: $\begin{array}{cc}d{V}_{\mathrm{tX}}=d{V}_{\mathrm{tY}}=\frac{N·I_{\mathrm{GM}}}{C_8}{t}_X=\frac{N·I_{\mathrm{GM}}}{C_8}{t}_Y& \left(9\right)\end{array}$

[0073] where C₈is the capacitance of capacitor 8, I_GMis the output current of transconductance amplifier 49, t_xis the time period that switch S2 is closed in each switching cycle, and t_yis the time period that switch S1 is closed in each switching cycle. Solving equation (9), it can be seen that t_x=t_y. Therefore, the optimum duty cycle for switches S1 and S2 is 50%. Times t_xand t_yare determined by clock signals V_CLKBand V_CLK, respectively.

[0074] Circuit 40 regulates the output voltage V_OUTto a predetermined value using the feedback loop comprising resistors 47A and 47B, reference voltage source 48, and transconductance amplifier 49. Resistor divider 47A/47B outputs a voltage feedback signal at the inverting input of amplifier 49, and voltage source 48 outputs a constant reference voltage at the non-inverting input of amplifier 49. When V_OUTvaries from the predetermined value by a certain amount (e.g., due to changes in the load current), the feedback voltage at the inverting input of amplifier 49 varies proportionally to V_OUT. Amplifier 49 then varies the current I_GMand sinks it to ground in response to the changes in the feedback voltage at its inverting input.

[0075] When V_OUTincreases in response to a decrease in the load current, the output current of amplifier 49 decreases so that the current through current mirrors 43/44 and 45/46 decreases in each subsequent cycle. The output current of converter 40 is reduced in each cycle to match the load current and to maintain V_OUTat a regulated voltage. When V_OUTdecreases in response to an increase in the load current, the output current of amplifier 49 increases so that the current through current mirrors 43/44 and 45/46 increases in each subsequent cycle. The output current of converter 40 increases in each cycle to match the load current and to maintain V_OUTat a regulated voltage.

[0076] Because charge is only transferred to output capacitor 9 every half cycle of V_CLKwhen switch S1 is closed, V_OUToscillates up and down during every cycle due to the presence of equivalent series resistance 12 and the charging and discharging of capacitor 9 in the output circuit. If the switching frequency is not much higher than the pole set by output capacitor 9 and load 11, the output current of amplifier 49 also ripples up and down with the output voltage in each switching cycle. This causes a triangle shaped waveform of input current I_INwhich increases noise at the input voltage source. To reduce this ripple current effect, the output capacitor 9 or the switching frequency can be increased to reduce output voltage ripple. Reducing the output voltage ripple can provide a substantially constant input current when switches S1 or S2 are closed (during a steady state), as shown in FIG. 4B.

[0077] Charge pump DC/DC converters of the present invention may also shunt input current I_INto ground during the blanking intervals to produce a more constant IN during each cycle. An example of circuitry that may be added to a DC/DC converter of the present invention is shown in FIG. 4A. NOR gate 60 and FET transistors 61-64 may be added to charge pump 40 as shown in FIG. 4A to shunt current to ground during the blanking intervals.

[0078] Blanking intervals occur twice during each period of the clock signals when both V_CLKand V_CLKBare LOW concurrently as shown in FIG. 3B. When either V_CLKand V_CLKBare HIGH, the output of NOR gate 60 is LOW causing transistor 61 to be ON and transistor 62 to be OFF. Transistors 61 and 62 form an inverter. When p-channel transistor 61 is ON, p-channel transistors 63 and 64 are OFF, because the gates of transistors 63 and 64 are pulled HIGH. Transistors 63 and 64 form a current mirror, because their gates are coupled together. N is the current gain ratio of transistor 64 to transistor 63. Thus, N is the gate width-to-length ratio of transistor pairs 64 to 63, 44 to 43, and 46 to 45.

[0079] The source of transistor 62 is coupled to the output of transconductance amplifier 49. When both V_CLKand V_CLKBare LOW concurrently, the output of NOR gate 60 is HIGH, causing N-channel FET 62 to be ON and p-channel FET 61 to be OFF. When transistor 62 is ON, amplifier 49 sinks current to ground through transistor 62, turning transistors 63 and 64 ON. When transistor 62 is ON, I_GMflows from V_INthrough transistors 63 and 62 and to ground through the output of amplifier 49. Also, when transistor 62 is ON, current flows from V_INthrough transistor 64 to ground. Therefore, I_INis defined by the following equation during the blanking intervals with circuitry 60-64:

[0080] I_IN=I_M63+I_M64=I_GM(1+N)  (10)

[0081] where I_M63is the current through transistor 63 and I_M64is the current through transistor 64. Therefore I_INduring the blanking interval equals I_INwhen S1 is closed and when S2 is closed. Current I_INflows continuously throughout each switching cycle and is substantially constant during a steady state as shown in FIG. 4C (with circuitry 60-64). The gate capacitance of transistors 63 and 64 should not be too large so that these transistors can turn ON quickly during the relatively brief blanking intervals.

[0082] A further embodiment of the present invention is illustrated in FIG. 5A. Charge pump DC/DC converter 70 includes oscillator 25, p-channel FETs 75 and 76, resistors 71A and 71B, reference voltage source 72, transconductance amplifier 74, capacitor 8, and switches S1, S2, S3, and S4. Switches S1-S4 are coupled in a boost arrangement so that converter 70 regulates an output voltage V_OUTthat is higher than V_IN. Transistors 75 and 76 form a current mirror, because their gates are coupled together and to the output of transconductance amplifier 74. Transistor 76 conducts M times the current conducted by transistor 75, because M is the current gain ratio of transistors 76 to 75.

[0083] Switches S2 and S4 are switched out of phase with switches S1 and S3 in each switching cycle by oscillator 25 as with the previous embodiments. The time that switches S2/S4 are ON equals the time that switches S1/S3 are ON, as with the previous embodiment. Thus, switches S1-S4 each have a 50% duty cycle.

[0084] When switches S4 and S2 are closed, current flows from V_INto capacitor 8 through transistor 76 and switch S4. When switches S3 and S1 are closed, current flows from V_INto capacitor 8 through transistor 76 and switch S3, and from capacitor 8 through switch S1 to V_OUT. Input current I_INequals the current through transistor 75 plus the current through transistor 76. A continuous current flows through transistor 75 that equals the output current I_GMof transconductance amplifier 74. The current through transistor 75 is independent of the switch states of switches S1-S4. When either of switches S3 or S4 are closed, a current flows through transistor 76 from V_IN. That current equals M times the current I_GMthrough transistor 75.

[0085] The current through transistor 76 is substantially constant as long as the current I_GMthrough transistor 75 is constant, because M is a constant. Transconductance amplifier 74 sinks a constant current I_GMto ground during a steady state as long as the switching frequency is much higher than the pole caused by capacitor 9 and load 11. Therefore, the current through transistors 75 and 76 and I_INremains constant during a steady state. The current through transistor 75 is typically a small fraction (1/M) of the current through transistor 76 (e.g., M=100). Therefore, I_INequals approximately M times I_GM, except during the blanking intervals when I_INequals zero. An example I_INwaveform during a steady state is shown in FIG. 5B. Current mirror 75/76 controls the current through capacitor 8 and the four switches during each phase of the clock cycle.

[0086] The average output current I_OUTof converter 70 (i.e., the average current through switch S1 over time) equals the load current I_Lduring a steady state. When switch S1 is open, the instantaneous output current of converter 70 equals zero. During the other half of the switching cycle, output current flows to V_OUTthrough transistor 76 when S1/S3 are closed. Therefore, the average current through transistor 76 must equal twice the average output current I_OUTThe relationship between the load current and I_GMis shown by the following equation:

[0087] I_L=2M·I_GM  (11)

[0088] The maximum value for V_OUTin converter 70 equals 2V_INin the illustrative case where the R_DSONfor transistor 76 equals zero, as with the previous embodiment.

[0089] Resistors 71A and 71B form a resistor divider that outputs a voltage feedback signal proportional to V_OUTat the inverting input of transconductance amplifier 74. Reference voltage source 72 outputs a constant voltage at the non-inverting input of amplifier 74. Transconductance amplifier 74 varies the amount of current it sinks to ground through transistor 75 as the voltage feedback signal at its inverting input changes in order to regulate V_OUT.

[0090] The output current of DC/DC converter 70 varies with output current I_GMof amplifier 74 to match the load current. When V_OUTincreases, transconductance amplifier 74 decreases I_GM, causing the current through transistor 76 and the output current of converter 70 to decrease. When V_OUTdecreases, transconductance amplifier 74 increases I_GM, causing the current through transistor 76 and the output current of converter 70 to increase. Amplifier 74 causes the current through transistors 75 and 76 to increase or decrease so that the average output current of converter 70 equals the load current by monitoring the voltage feedback signal.

[0091] A further charge pump DC/DC converter is shown in FIG. 6A. Charge pump DC/DC converter 90 includes oscillator 25, current mirror transistors 75 and 76, reference voltage source 72, transconductance amplifier 74, capacitor 8, resistors 71A and 71B, and switches S5, S6, S7, and S8. Switches S5-S8 are coupled in a buck arrangement so that DC/DC converter 90 provides an output voltage V_OUTthat is lower than input voltage V_IN. Resistors 71A/71B, reference 72, transconductance amplifier 74, and mirror transistors 75 and 76 operate to regulate V_OUTas discussed above with respect to boost converter 70 in FIG. 5A. Transconductance amplifier 74 sets its output current I_GMto adjust the output current of converter 90 based on the voltage feedback signal at its inverting input.

[0092] In buck charge pump DC/DC converter 90, switches S5 and S6 are closed together while switches S7 and S8 are open in the first phase of each switching cycle, and switches S7 and S8 are closed together while switches S5 and S6 are open in the second phase of each switching cycle. Switches S5-S8 each have a 50% duty cycle. Switches S5 and S6 are closed when V_CLKis HIGH and open when V_CLKis LOW. Switches S7 and S8 are closed when V_CLKBis HIGH and open when V_CLKBis LOW. The clock signals are shown in FIG. 6B.

[0093] When switches S5 and S6 are closed, capacitor 8 is coupled to V_OUTthrough switch S5 and to ground through switch S6. Therefore, the voltage on capacitor 8 equals V_OUT. Switches S7 and S8 are closed after switches S5 and S6 open. Capacitor 8 is then coupled to the drain of transistor 76 through switch S8 and to V_OUTthrough switch S7. Current flows from V_INto capacitor 8 through switch S8 and transistor 76, and current flows from capacitor 8 through switch S7 to load 11. The voltage drop across capacitor 8 is still at V_OUTwhen switches S7 and S8 close. The voltage on the upper plate of capacitor 8 (coupled to switch S8) rises to 2V_OUT, because the lower plate of capacitor 8 is coupled to V_OUTthrough switch S7. The voltage across transistor 76 is now V_IN−2V_OUT. Therefore, the regulated value of V_OUTmust be less than or equal to one half of V_INso that current does not flow from V_OUTto V_IN(V_OUT≦V_IN/2).

[0094] The current through transistor 76 is substantially constant as long as the current through transistor 75 (I_GM) is constant, and the switching frequency is much higher than the pole caused by capacitors 9 and 11, as discussed above. Therefore, the current through transistor 76 and I_INremains constant during a steady state when S8 is closed. An example I_INwaveform during a steady state is shown in FIG. 6B. I_INis approximately zero when V_CLKBis LOW, because switch S8 is open, transistor 76 is OFF, and the current through transistor 75 is negligible (e.g., between t2 and t4).

[0095] The average output current I_OUTof converter 90 equals the load current I_Lduring a steady state. Output current flows to V_OUTfrom capacitor 8 during each half of the switching cycle when S5 is closed and when S7 is closed. The output current of converter 90 equals the current through transistor 76 when it is ON (V_CLKBHIGH). The current through transistor 76 when it is ON equals approximately M times I_GM, as discussed above. The relationship between the load current and I_GMis shown by equation (12):

[0096] I_L=M·I_GM  (12)

[0097] The feedback loop (comprising amplifier 74, resistor divider 71A/71B, and reference 72) determines the output current of converter 90 by varying output current I_GMaccording to equation (12) so that the current through transistor 76 when it is ON equals I_L.

[0098] Current mirror transistor 76 sets the amount of current that flows to capacitor 8 when switches S7 and S8 are closed, thereby providing a substantially constant current I_IN, as shown in FIG. 6B between times t1 and t2. Converter 90 therefore reduces noise at the input voltage by providing a more constant input current when switch S8 is closed.

[0099] A further embodiment of the present invention is illustrated in FIG. 7A. Charge pump DC/DC converter 110 in FIG. 7A supplies output current to load 11 to regulate output voltage V_OUT. Charge pump 110 includes resistors 71A and 71B, transconductance amplifier 74, reference voltage source 72, current mirror transistors 75 and 76, oscillator 25, capacitors 8 and 100, and switches S5, S6, S7, S8, S15, S16, S17, and S18. Switches S5-S8 and switches S15-S18 comprise two buck DC/DC converters that are coupled in parallel with each other between the drain of transistor 76 and V_OUT. In buck charge pump DC/DC converter 110, switches S5-S8, oscillator 25, transconductance amplifier 74, reference 72, and resistor divider 71A/71B operate as discussed above with respect to FIG. 6A.

[0100] Switches S15/S16 are switched out of phase with switches S5/S6, and switches S17/S18 are switched out of phase with switches S7/S8. Switches S7, S8, S15 and S16 are closed when V_CLKBis HIGH and open when V_CLKBis LOW. Switches S5, S6, S17, and S18 are closed when V_CLKis HIGH, and open when V_CLKis LOW. Switches S15-S18 each have a 50% duty cycle.

[0101] When switches S15 and S16 are closed, capacitor 100 is coupled to V_OUTthrough switch S15 and to ground through switch S16. Therefore the voltage on capacitor 100 equals V_OUT. Switches S17 and S18 are closed after switches S15 and S16 open. Capacitor 100 is then coupled to transistor 76 through switch S18 and to V_OUTthrough switch S17. Current flows from V_INto capacitor 100 through transistor 76 and switch S18, and current flows from capacitor 100 through switch S17 to load 11. Because the voltage drop across a capacitor cannot change instantaneously, the voltage drop across capacitor 100 is still V_OUTat the moment that switches S17 and S18 close. The voltage on the left plate of capacitor 100 (coupled to switch S18) rises to 2V_OUT, because the right plate of capacitor 100 is coupled to V_OUTthrough switch S17. Therefore, V_OUTmust be less than or equal to one half of the voltage of V_INfor DC/DC converter 110 to properly regulate V_OUT(V_OUT≦V_IN/2), as with converter 90.

[0102] By inspection, it can be seen that converter 110 has two charge pump DC/DC converters working in parallel: switches S5-S8 and switches S15-S18. Each converter provides one half of the required load current I_L. The current through transistor 76 (M·I_GM) charges up capacitor 8 with one half of the load current when S8 is closed (S18 open). The current through transistor 76 (M·I_GM) charges up capacitor 100 with one half of the load current when S18 is closed (S8 open). Thus, the load current is determined by the following equation: $\begin{array}{cc}{I}_L=\frac{M·I_{\mathrm{GM}}}{2}& \left(13\right)\end{array}$

[0103] The input current I_INis continuously flowing from V_INthrough transistor 76 during each half cycle except during the blanking intervals. The input current I_INis constant as long as I_GMis constant as shown by the following equation:

[0104] I_IN=(M+1)·I_GM  (14)

[0105] A graph of I_INis shown in FIG. 7B. Current mirror transistors 75/76 provide a constant input current I_INduring each phase of the switching cycle thereby reducing noise at the input voltage source.

[0106] A further embodiment of a boost charge pump DC/DC converter of the present invention is illustrated in FIG. 8A. Converter 120 in FIG. 8A includes oscillator 25, an inverter formed by P-channel FET 121 and N-channel FET 122, an inverter formed by P-channel FET 123 and N-channel FET 124, current mirror 125 that includes P-channel FETs 126 and 128, current mirror 135 that includes P-channel FETs 130, 132 and 134, capacitors 140 and 142, switches S11, S12, S13, and S14, resistors 150A and 150B, reference voltage source 152, transconductance amplifier 154, and schottky diodes 160 and 162.

[0107] Transistors 126 and 128 form a current mirror because their gates are coupled together. Transistors 130, 132, and 134 form a current mirror because their gates are coupled together. N is the current gain ratio of transistor 128 to transistor 126. N/2 is the current gain ratio of transistors 132 and 134 to transistor 130.

[0108] The source of transistor 121 is coupled to the cathodes of schottky diodes 160 and 162 as shown in FIG. 8A. The anode of diode 160 is coupled to V_IN, and the anode of diode 162 is coupled to V_OUT. Thus, when transistor 121 is ON, the source of transistor 121 is coupled to the larger of V_INor V_OUTthrough diodes 160 or 162. In circuit 120, V_OUTis generally larger than V_IN, because it is a boost converter so that transistor 121 is coupled to V_OUTwhen it conducts current.

[0109] Oscillator 25 outputs digital clock signals V_CLKand V_CLKB. Clock signals V_CLKand V_CLKBmay have a blanking interval as shown in FIG. 8B. Clock signal V_CLKcontrols the opening and closing of switches S11 and S12, and clock signal V_CLKBcontrols the opening and closing of switches S13 and S14. When V_CLKBis LOW, transistor 123 is ON, transistor 124 is OFF, and switches S13 and S14 are open. When transistor 123 is ON, the output of inverter 123/124 and the gates of P-channel transistors 130, 132, and 134 are HIGH (at V_IN), causing transistors 130, 132, and 134 to be OFF. When V_CLKis HIGH, transistor 121 is OFF, transistor 122 is ON, and switches S11 and S12 are closed. When transistor 122 is ON, the gates of transistors 126 and 128 are pulled down by the output current I_GMof transconductance amplifier 154. Thus, when transistor 122 is ON, transistor 126 is ON and current I_GMflows from V_INthrough transistors 126 and 122 to ground through the output of transconductance amplifier 154. I_GMis the output current of amplifier 154. Transistor 128 is also ON when transistor 126 is ON, causing current N·I_GMto flow from V_INthrough transistor 128 and charging up capacitors 140 and 142.

[0110] When V_CLKis LOW, transistor 121 is ON, transistor 122 is OFF, and switches S11 and S12 are open. When transistor 121 is ON, the output of inverter 121/122 and the gates of transistors 126 and 128 are HIGH (at V_OUT), causing transistors 126 and 128 to be OFF. When V_CLKBis HIGH, transistor 123 is OFF, transistor 124 is ON, and switches S13 and S14 are closed. When transistor 124 is ON, the gates of transistors 130, 132, and 134 are pulled down by the output current I_GMof transconductance amplifier 154. Thus, when transistor 124 is ON, transistor 130 is ON and current I_GMflows from V_INthrough transistors 130 and 124 to ground through the output of transconductance amplifier 154. Transistors 132 and 134 are also ON when transistor 130 is ON. A current equal to N·I_GM/2 flows from V_INthrough transistor 132 and capacitor 142 to V_OUT. A current equal to N·I_GM/2 also flows from V_INthrough transistor 134 and capacitor 140 to V_OUT.

[0111] Because the gate width-to-length ratio of transistor 128 is N times the gate width-to-length ratio of transistor 126, the current that flows through transistor 128 equals N times the current I_GMthat flows through transistor 126. So long as transconductance amplifier 154 sinks a constant current during a steady state load current, the current through transistors 126 and 128, and the input current I_INremains constant while switches S11 and S12 are closed. I_INis defined by the following equation when switches S11 and S12 are closed, where I_GMis the current through transistor 126 and I_M128is the current through transistor 128:

[0112] I_IN=I_GM+I_M28=I_GM(1+N)  (15)

[0113] Because the gate width-to-length area of transistors 132 and 134 are each N/2 times the gate width-to-length area of transistor 130, the current that flows through each of transistors 132 and 134 equals N/2 times the current I_GMthat flows through transistor 130. So long as transconductance amplifier 154 sinks a constant current during a steady state load current, the current through transistors 130, 132 and 134, and the input current I_INremain constant while switches S13 and S14 are closed. I_INis defined by equation (16) when switches S13 and S14 are closed, where I_GMis the current through transistor 130, I_M132is the current through transistor 132, and I_M134is the current through transistor 134:

[0114] I_IN=I_GM+I_M132+I_M134=I_GM(1+N)  (16)

[0115] Thus, if transconductance amplifier 154 sinks a constant current I_GM, I_INremains constant when switches S11/S12 or S13/S14 are closed.

[0116] During the blanking interval when V_CLKand V_CLKBare LOW concurrently, and switches S1 and S2 are open, I_INis zero. Therefore, I_INvaries between a constant value and zero twice during every cycle of the clock signals during a steady state as shown, for example, in the graph of FIG. 8B. The circuit of FIG. 8A, therefore, reduces low frequency noise at the input voltage source by maintaining the input current I_INat a constant value when switches S11/S12 or S13/S14 are closed.

[0117] The charge that is added to capacitor 140 from V_INwhen switches S11 and S12 are closed equals the charge that is transferred to the load when switches S13 and S14 are closed, during a steady state condition. Therefore, the change in voltage across capacitor 140 (dV_tA) when S11 and S12 are closed equals the change in voltage across capacitor 140 (dV_tB) when S13 and S14 are closed. Setting these quantities equal to each other from equation (1) it can be seen that: $\begin{array}{cc}d{V}_{\mathrm{t1}}=d{V}_{\mathrm{t2}}=\frac{N·I_{\mathrm{GM}}}{C_{140}}{t}_A=\frac{\frac{N}{2}·I_{\mathrm{GM}}}{C_{140}}{t}_B& \left(17\right)\end{array}$

[0118] where C₁₄₀is the capacitance of capacitor 140, t_Ais the time period that switches S11 and S12 are closed in each switching cycle, and t_Bis the time period that switches S13 and S14 are closed in each switching cycle. Times T_Aand T_Bare determined by clock signals V_CLKand V_CLKB, respectively, that are shown for example, in FIG. 8B. Solving equation (17), it can be seen that T_B=2T_A. Therefore, switches S13 and S14 are closed twice as long as switches S11 and S12 are closed in each switching cycle.

[0119] Assuming for purposes of illustration that the R_DSONof transistors 128, 132 and 134 equals zero, V_INis applied across capacitors 140 and 142 when switches S11 and S12 are closed. One half of V_INdrops across capacitor 140, and one half of V_INdrops across capacitor 142. When switch S13 and S14 close, the voltage across capacitor 140 (V_IN/2) plus V_INis applied to V_OUT. Also, the voltage across capacitor 142 (V_IN/2) plus V_INis applied to V_OUT. Therefore, V_OUTequals {fraction (3/2)} times V_INin the illustrative case where the R_DSONfor transistors 128, 132, and 134 equals zero for boost converter 120. This is the maximum value for V_OUT. When R_DSONis increased above zero in a steady state, V_OUTbecomes less than 3V_IN/2. Thus, V_OUT≦3V_IN/2. As the load current changes, I_GMcan be adjusted by amplifier 154 (discussed below) to maintain the same input-to-output voltage ratio.

[0120] To achieve a constant input current in each phase of the clock signal in boost converters of the present invention, the duty cycle ratio of at least one of the switches is selected to be equal to the minimum input-to-output voltage ratio. For example, minimum input-to-output voltage ratio of circuit 20 is ⅔ of that in circuit 120 of FIG. 8A. The duty cycle ratio of switches S13/S14 is also ⅔ with respect to the switching period. The duty cycle ratio of the switches may be selected to obtain a different input-to-output voltage ratio and to achieve constant input current.

[0121] The average output current I_OUTof converter 120 equals the load current I_Lduring a steady state condition. The output current of converter 120 is zero when switches S13 and S14 are open, because there is no current path to the output node. The output current of converter 120 equals N times I_GM(the current through transistor 132 plus the current through transistor 134) when switches S13 and S14 are closed. Switches S13 and S14 are closed during ⅔ of the time period of each cycle as stated above. Therefore, the load current I_Lis defined by the following equation:

[0122] I_L=⅔N·I_GM=⅔I_IN  (18)

[0123] where N is substantially larger than 1 (e.g., N=100), and thus I_INequals N times I_GM.

[0124] Circuit 120 regulates the output voltage V_OUTto a predetermined value using the feedback loop circuitry comprising resistors 150A and 150B, reference voltage source 152, and transconductance amplifier 154. The feedback loop in converter 120 operates to adjust the output current to match I_Lby varying I_GMin response to changes in V_OUTin the same fashion as the feedback loop comprising resistors 71A/71B, reference 72, and transconductance amplifier 74 in the pervious embodiments.

[0125] A further embodiment of a buck charge pump DC/DC converter of the present invention is illustrated in FIG. 9A. Converter 200 in FIG. 9A includes oscillator 25, current mirror transistors 75/76, two buck charge pumps coupled in parallel, and feedback loop circuitry that comprises resistors 71A and 71B, reference voltage source 72, and transconductance amplifier 74. The first buck charge pump comprises capacitors 210 and 212, and switches S21, S22, S23, S24, S25, S26, and S27. The second buck charge pump comprises capacitors 214 and 216, and switches S31, S32, S33, S34, S35, S36, and S37. Switches S21/S22/S23 are switched out of phase with switches S24/S25/S26/S27, and switches S31/S32/S33 are switched out of phase with switches S34/S35/S36/S37 by the clock signals. Switches S21/S22/S23 are switched out of phase with switches S31/S32/S33, and switches S24/S25/S26/S27 are switched out of phase with switches S34/S35/S36/S37. Each of switches S21-S27 and S31-S37 have a 50% duty cycle.

[0126] Oscillator 25 outputs digital clock signals V_CLKand V_CLKB. Clock signals V_CLKand V_CLKBmay have a blanking interval. Clock signal V_CLKBcontrols the opening and closing of switches S21/S22/S23 and switches S34/S35/S36/S37. Clock signal V_CLKBcontrols the opening and closing of switches S24/S25/S26/S27 and switches S31/S32/S33. Switches S21/S22/S23 and S34/S35/S36/S37 are closed when V_CLKis HIGH and open when V_CLKis LOW. Switches S24/S25/S26/S27 and S31/S32/S33 are closed when V_CLKBis HIGH and open when V_CLKBis LOW. Switches S24/S25/S26/S27 are closed during one phase of the clock signals and switches S34/S35/S36/S37 are closed during the other phase of the clock signals. Thus, the two buck charge pumps S21-S27 and S31-S37 coupled in parallel provide a constant input current I_INduring each phase of the clock signals as shown, for example, in FIG. 9B (except during the blanking intervals). Illustrative waveforms for clock signals V_CLKand V_CLKBin converter 200 are shown in FIG. 9B.

[0127] The input current through current mirror transistors 75 and 76 is constant and is set by output current I_GMof transconductance amplifier 74, as discussed above with respect to FIG. 5A. Because each charge pump S21-S27 and S31-S37 provides one half of the required load current I_L, the load current for converter 200 is defined by equation (13) during a steady state.

[0128] V_OUTis applied across capacitors 210 and 212 when switches S21, S22, and S23 are closed. One half of V_OUTdrops across capacitor 210 and one half of V_OUTdrops across capacitor 212. When switches S21-S23 open and switches S24-S27 close, capacitors 210 and 212 are both coupled between V_INand V_OUT. A voltage equal to V_OUT/2 now drops across capacitors 210 and 212 relative to V_OUT. Therefore, the voltage across transistor 76 equals V_IN−3V_OUT/2. Thus, the regulated value of V_OUTfor converter 200 must be related to V_INaccording to the following equation so that current does not flow from V_OUTto V_IN: $\begin{array}{cc}{V}_{\mathrm{OUT}}\le \frac{2V_{\mathrm{IN}}}{3}& \left(19\right)\end{array}$

[0129] Persons skilled in the art further will recognize that the circuitry of the present invention may be implemented using circuit configurations other than those shown and discussed above. For example, a variable resistance may be used in place of current mirror 75/76 in the buck embodiments of FIGS. 7A and 9A. All such modifications are within the scope of the present invention, which is limited only by the claims which follow.