Method and apparatus for controlling stages of a multi-stage circuit

[0002] I. Field of the Invention

[0003] The present invention relates to electronic circuits. More particularly, the present invention relates to a novel and improved method and apparatus for controlling stages of a multi-stage circuit such as a sigma-delta analog-to-digital converter (ΣΔ ADC).

[0004] II. Description of the Related Art

[0005] An analog-to-digital converter (ADC) is an important component in many electronic circuits, and is especially important in digital communication systems. An ADC converts a continuous analog waveform into discrete samples at evenly spaced time intervals. The samples can subsequently be processed by other digital signal processing blocks to provide enhancement, compression, and/or error detection/correction of the sampled data. Exemplary applications which require ADCs are code division multiple access (CDMA) communication system and high-definition television (HDTV).

[0006] Some important performance parameters of an ADC include linearity, DC offset, and signal-to-noise ratio (SNR). Suboptimal values for these parameters can cause degradation in the performance of a communication system. Linearity relates to the difference between an actual transfer curve (digital output versus analog input) and the ideal transfer curve. For a flash ADC, good linearity is more difficult to obtain as the number of bits in the ADC increases. The DC offset can degrade the acquisition and tracking performance of phase locked loops and the error detection/correction capability of the decoder, such as the Viterbi decoder. SNR can affect the bit-error-rate (BER) performance of the communication system because the quantization and circuit noise from the ADC results in degradation of the sampled data.

[0007] In many communication systems, the received RF signal is downconverted to baseband before quantization. Typically, the received signal is downconverted from a RF frequency to an intermediate frequency (IF) in the first downconversion stage. The first downconversion allows the receiver to downconvert signals at various RF frequencies to a fixed IF frequency where signal processing can be performed. For example, the fixed IF frequency allows for a fixed bandpass filter, such as a surface acoustic wave (SAW) filter, to remove undesirable images and spurious responses from the IF signal before the second downconversion stage. The IF signal is then downconverted to baseband where sampling is performed to provide the digitized baseband samples.

[0008] In most communication applications, an ADC is required at the receiver. In some applications, the receiver is a commercial unit where cost and reliability are important design criteria because of the number of units produced. Furthermore, in some applications, such as a CDMA mobile communication system, power consumption is critical because of the remote/portable nature of the receiver.

[0009] In the prior art, a flash ADC or a successive approximation ADC is used to sample the received signal. In the flash ADC, the input signal is compared against L-1 reference voltages, which are generated by a resistive ladder, by L-1 comparators. Flash ADCs are bulky and consume large amount of power because L-1 comparators and L resistors are required. Furthermore, flash ADCs can have poor linearity and poor DC offset characteristics, if the L resistors in the resistive ladder are not matched. However, flash ADCs are popular because of their high speed.

[0010] Successive approximation ADCs are also often used in communication systems. These ADCs minimize complexity by performing approximations of the input signal over two or more stages. However, these ADCs can also exhibit the same poor linearity and poor DC offset characteristics as exhibited by the flash ADCs. Therefore, successive approximation ADCs as well as flash ADCs are not ideal candidates for use in many communication applications.

[0011] For some applications, improved data conversion performance can be achieved with a sigma-delta ADC (ΣΔ ADC).

[0012] The present invention provides a control mechanism that can be used to control a ΣΔ ADC to provide the required level of performance while reducing power consumption. The ΣΔ ADC is designed with multiple stages (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a ΣΔ ADC that is similar to the ΣΔ ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved.

[0013] An embodiment of the invention provides a data conversion circuit that includes a ΣΔ ADC coupled to a control circuit. The ΣΔ ADC includes a number of ΣΔ stages coupled in cascade that receives an input signal and provides data samples. The control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal. The conditioning circuit couples to the detector stage(s), receives the detected signal, and provides conditioned samples. The signal processor couples to the conditioning circuit, receives the conditioned samples, and provides a control signal that selectively disables zero or more ΣΔ stages.

[0014] In an embodiment, at least one detector stage is implemented as a replica of one of the ΣΔ stages, and can be shrunken and/or biased with less current than the ΣΔ stage it replicates. The detected signal can be indicative of an amplitude of the input signal. The ΣΔ stages can be disabled based on the detected signal amplitude, and possibly based on the relative locations of the ΣΔ stages within the ΣΔ ADC. In a specific implementation, the ΣΔ ADC includes two fourth-order bandpass stages or two second-order lowpass stages. The data conversion circuit is advantageously used in a cellular (e.g., CDMA) receiver.

[0015] Another embodiment of the invention provides an electronic circuit that includes a multi-stage circuit coupled to a control circuit. The multi-stage circuit includes N signal stages coupled in a particular configuration (e.g., cascade, parallel, and others). The control circuit provides a control signal that selectively disables zero or more signal stages. The control circuit includes one or more detector stages, a conditioning circuit, and a signal processor that can be configured and operated as described above. The detector stage(s) can be implemented as replica(s) of the signal stage(s), and can be shrunken and/or biased with less current. The signal stages can be selectively disabled based on, for example, the amplitude of the input signal.

[0016] Yet another embodiment of the invention provides a control circuit for controlling a multi-stage circuit that includes a number of signal stages. The control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. At least one detector stage is implemented as a replica of one of the signal stages. The detector stage(s), conditioning circuit, and signal processor can be configured and operated as described above. The control circuit is advantageously used to control a ΣΔ ADC.

[0017] Yet another embodiment of the invention provides a method for controlling ΣΔ stages in a ΣΔ ADC. In accordance with the method, a characteristic of an ADC input signal is detected using one or more detector stages. At least one detector stage is implemented as a replica of one of the ΣΔ stages. The detected characteristic is compared against a comparison level. A control signal is generated based, in part, on the comparison. Zero or more ΣΔ stages are then selectively disabled in accordance with the control signal. The characteristic being detected can be an amplitude of the input signal, and the ΣΔ stages can be disabled based on the detected signal amplitude.

[0018] The features, nature, and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein:

[0019] FIG. 1 is a block diagram of an exemplary single-loop sigma-delta analog-to-digital converter (ΣΔ ADC) architecture;

[0020] FIG. 2 is a block diagram of an exemplary MASH ΣΔ ADC architecture;

[0021] FIGS. 3A-3D are pole-zero diagram and frequency response plot of an integrator and pole-zero diagram and frequency response plot of a bandpass resonator, respectively;

[0022] FIG. 4 is a block diagram of an exemplary two loop bandpass MASH ΣΔ ADC of the present invention;

[0023] FIGS. 5A-5E are block diagrams of a resonator within the bandpass MASH ΣΔ ADC and implementations of the resonator with a delay cell resonator, a lossless discrete integrator resonator, a Forward-Euler resonator, and a two-path interleaved resonator, respectively;

[0024] FIGS. 6A-6B are schematic diagram of a delay cell using double-sampling switched capacitor analog circuit technique and timing diagram of the required clock signals for the delay cell, respectively;

[0025] FIGS. 7A-7B are schematic diagrams of a resonator circuit within the bandpass MASH ΣΔ ADC and the feed-forward gain circuit, respectively, both of which are implemented using double-sampling switched capacitor analog circuit technique;

[0026] FIG. 8 is a block diagram of an exemplary eighth order bandpass MASH 4-4 ΣΔ ADC of the present invention;

[0027] FIG. 9 is a plot of the simulated signal-to-noise ratio (SNR) performance of the bandpass MASH 4-4 ΣΔ ADC of the present invention;

[0028] FIGS. 10A-10B are exemplary schematic diagrams of a delay cell based resonator and a Forward-Euler resonator, respectively, both implemented using single-sampling switched capacitor analog circuit technique;

[0029] FIGS. 10C-10D are exemplary schematic diagrams of a two-path interleaved resonator implemented using pseudo two-path single-sampling switched capacitor analog circuit and the timing diagram of the required clock signals for the pseudo two-path circuit, respectively;

[0030] FIGS. 10E-10F are exemplary schematic diagrams of a two-path interleaved resonator implemented using two independent path double-sampling switched capacitor analog circuits;

[0031] FIGS. 10G-10H are exemplary schematic diagrams of a double-sampled delay cell based resonator circuit and timing diagram of the required clock signals for the resonator circuit, respectively;

[0032] FIGS. 11 through 13 show simplified block diagrams of three specific embodiments of a control circuit for controlling a multi-stage circuit, which can be a ΣΔ ADC as shown in FIG. 11;

[0033] FIG. 14 shows a simplified block diagram of a specific embodiment of a control circuit that can be used as the control circuits in FIGS. 11 through 13;

[0034] FIG. 15A shows a graph of the standard deviation of the detected signal from a detector stage versus input signal amplitude;

[0035] FIG. 15B shows a graph of the distribution densities of the signal levels of the detected signal; and

[0036] FIG. 15C shows a graph of the count value from a signal processor versus detector input signal amplitude.

[0037] A high-speed sigma-delta analog-to-digital converter (ΣΔ ADC) performs analog-to-digital conversion of the input signal by making successive one-bit approximations of the change in amplitude of the input signal, since the previous sample has already been approximated, at a sampling rate which is many times higher than the bandwidth of the input signal. The output samples comprise the input signal and the quantization noise. The ΣΔ ADC can be designed such that the quantization noise is pushed (or noise shaped) to an out-of-band frequency where filtering is more easily performed.

[0038] A ΣΔ ADC can provide high signal-to-noise ratio (SNR), good linearity, and low DC offset because of the inherent structure of ΣΔ ADC. For example, high SNR can be obtained by selecting a sufficient oversampling ratio (OSR) and the appropriate noise shaping filters. Additionally, good linearity and low DC offset are obtained because of the simple one-bit quantizer within the ΣΔ ADC.

[0039] High-speed bandpass ΣΔ ADC can be used to perform the required analog-to-digital conversion of narrowband signals at an intermediate frequency (IF). Exemplary applications include CDMA communication system and HDTV. In a bandpass ΣΔ ADC, the input signal is at an IF frequency instead of baseband. Sampling at IF allows for the elimination of a downconversion stage in the communication system, thus reducing circuit complexity, decreasing cost, and improving reliability. Furthermore, the noise shaping filters within the bandpass ΣΔ ADC can be designed such that the quantization noise around the band of interest is pushed to out-of-band frequencies where filtering is more easily performed.

[0040] ΣΔ ADC samples an analog waveform in continuous time to provide discrete samples at evenly spaced time intervals. ΣΔ ADC has the following transfer function: $\begin{array}{cc}Y\left(z\right)=G\left(z\right)·X\left(z\right)+H\left(z\right)·E\left(z\right),& \left(1\right)\end{array}$

[0041] where Y(z) is the output from the ΣΔ ADC in the z-transform domain, X(z) is the input to the ADC, E(z) is the quantization noise, G(z) is the transfer function from the input to the output, and H(z) is the noise transfer function from the quantizer to the output. Thus, the ADC output Y(z) comprises the input signal X(z) that is shaped by the transfer function G(z) plus the quantization noise E(z) which is shaped by the noise transfer function H(z). To avoid distortion of the input signal X(z), the transfer function G(z) is typically designed such that it is frequency independent. For example, G(z) can be an allpass function comprising a fixed gain (A₁) and delay elements (z⁻¹), such as A₁·z^−m. The quantization noise E(z) can be shaped by the noise transfer function H(z) such that the quantization noise in the band of interest (e.g. the band where the input signal is present) is pushed out-of-band where filtering is more easily performed. The characteristics of the noise transfer function H(z) is selected based on the application for which the ΣΔ ADC is used and is designed to provide the required performance.

[0042] I. ΣΔ ADC Architectures

[0043] ΣΔ ADC can be designed using one of many architectures. A block diagram of an exemplary single-loop ΣΔ ADC 10 is shown in FIG. 1. Single-loop ΣΔ ADC 10 comprises input summer 22 that subtracts the quantized ADC output from the ADC input. The error signal from summer 22 is provided to first filter 24 that filters the error signal in accordance with the transfer function of first filter 24. The output of first filter 24 is provided to summer 26 that subtracts the quantized ADC output from the output of first filter 24. The error signal from summer 26 is provided to second filter 28 that filters the error signal in accordance with the transfer function of second filter 28. The output of second filter 28 is quantized, typically to one bit although more bits can also be used, and provided as the quantized ADC output.

[0044] FIG. 1 illustrates a single loop ΣΔ ADC with two filter sections. The filter sections determine the noise shaping characteristics of the ΣΔ ADC and is designed based on the application for which the ΣΔ ADC is used. More filter sections can be interposed between second filter 28 and quantizer 30. However, single-loop ΣΔ ADCs are typically designed with two or less filter sections because of concerns with instability of higher order single-loop ΣΔ ADCs.

[0045] A block diagram of an exemplary MASH ΣΔ ADC architecture is shown in FIG. 2. A MASH ADC can be designed with two or more loops, depending on the desired noise transfer function H(z). However, MASH ADCs with more than three loops are not typically utilized because small incremental improvement is achieved for additional loops greater than three. The MASH architecture is preferred for a higher order ΣΔ ADC since the MASH architecture is inherently stable.

[0046] As shown in FIG. 2, a MASH ADC 12 comprises three loops 40a, 40b, and 40c. Loop 40aquantizes the ADC input and provides the output Y1 to noise cancellation logic 90. The operation of noise cancellation 90 is described in detail below. A fraction of the ADC input and quantization noise (X2) from loop 40ais provided to loop 40bwhere additional noise shaping is performed. Finally, a fraction of the ADC input and quantization noise (X3) from loop 40bis provided to loop 40cwhere further noise shaping is performed. The output Y2 from loop 40band Y3 from loop 40care provided to noise cancellation logic 90 where they are combined with the output Y1 from loop 40ato produce the ADC output. In the exemplary embodiment, ADC output comprises one bit for each loop. After noise cancellation, the dynamic range, and thus the output of MASH ADC 12, can be three bits or more.

[0047] Within each loop 40, summer 42 receives the input signal and the quantizer output from quantizer 46. Summer 42 subtracts the quantizer output from the input signal and provides the error signal to loop filter 44. Loop filter 44 filters the error signal and provides the filtered output to quantizer 46 where it is quantized to one-bit values. Loop filter 44 is designed to produce the desired noise transfer function H(z) that is based on the application for which the EA ADC is used. The filtered output from loop filter 44 in all but the last loop 40cis provided to gain element 52 and scaled with a first gain. The output from quantizer 46 in all but the last loop 40cis provided to gain element 54 and scaled with a second gain. The scaled signal from gain element 54 is subtracted from the scaled signal from gain element 52 by summer 56 and the error signal is provided to gain element 56. Gain element 56 scales the error signal with a third gain and provides the scaled error signal to the subsequent loop 40. The gains of gain elements 52, 54, and 58 affect the noise transfer function H(z) of MASH ADC 12.

[0048] Each loop filter 44 can comprise one or more filter sections, depending on the desired noise transfer function. More filter sections allow for implementation of higher order ΣΔ ADC to produce the desired performance, such as high SNR. A loop filter design is described in detail below.

[0049] In this specification, a MASH ΣΔ ADC is designated in accordance with the following nomenclature. MASH A-B-C denotes three loops (A, B, and C) which are of the order designated by the values of A, B, and C. For example, MASH 4-2-2 denotes a three loop architecture, with the first loop having a fourth order filter, the second loop having a second order filter, and the third loop also having a second order filter. Overall, MASH 4-2-2 is an eighth order ΣΔ ADC. The present invention can be directed toward a MASH 2-2, MASH 4-2, MASH 4-4, MASH 4-2-2, MASH 4-4-2, MASH 4-4-4 and other orders of MASH ΣΔ ADC.

[0050] The selection of the desired ΣΔ ADC architecture, single-loop or MASH, depends on a number of factors. One important factor is the required signal-to-noise ratio (SNR). SNR is defined as the ratio of the power of the largest input signal to the power of the quantization noise. For a full-scale sinewave input, the SNR for a ΣΔ ADC can be calculated according to the following equation: $\begin{array}{cc}\mathrm{SNR}=\frac{3}{2}·\frac{2L+1}{{\pi }^{2L}}·{\left(\mathrm{OSR}\right)}^{2L+1},& \left(2\right)\end{array}$

[0051] where L is the order of the loop filter used for noise shaping and OSR is the oversampling ratio. OSR is defined as the ratio of the sampling rate over the two-sided signal bandwidth, $\mathrm{OSR}=\frac{f_s}{2f_{\mathrm{BW}}}.$

[0052] Equation (2) is based on the simple theory using only white quantization noise and a unity gain quantizer. Using equation (2) the SNR is calculated for an exemplary CDMA application wherein the 2-sided signal bandwidth 2f_BW=2.4576 MHz and the sampling rate is approximately 78.64 MHz. These frequencies produce an OSR of 32. The SNR is calculated for various loop filter order L and the results are tabulated in Table 1. The loop filter order is the summation of the order of all filters within the ΣΔ ADC. For a bandpass ΣΔ ADC, the loop filter order L is half of the overall order of the bandpass filters. An n-th order bandpass filter has an effective order of L=n/2 because the poles in the bandpass transfer function are divided evenly between the upper half of the z-plane and the lower half of the z-plane. The calculated SNR values in Table 1 represent the upper bound that can be achieved. The actual SNR may be 10 dB to 15 dB less than the calculated values due to non-ideal circuit components and limitation of the input signal to less than the full-scale value.

[0053] For the CDMA application described above, the SNR is simulated to be 70 dB for a bandpass MASH 4-2 ADC, 85 dB for a MASH 4-4, 60 dB for a sixth order single-loop bandpass ΣΔ ADC, and 62 dB for an eighth order single-loop ADC. The simulated results are also tabulated in Table 1. The simulated results assume an input signal at −10 dB below full-scale and coincident zeros (e.g. all zeros are placed at z=±j) in the noise transfer function H(z). The simulated SNR value for the sixth order single-loop ΣΔ ADC can be improved to 70 dB if the zeros are spread across the signal bandwidth. Similarly, the simulated SNR value for the eighth order single-loop ΣΔ ADC can be improved to 80 dB with zero spreading. However, zero spreading can be difficult to achieve due to non-ideal circuit components. The simulated SNR of a MASH architecture is better than that of the single-loop architecture.

[0054] In actual implementation, the MASH architecture has the additional advantages of inherent stability and ease of loop filter design. However, circuit matching is more critical for the MASH architecture because of the need to cancel the quantization noise between multiple loops. The single-loop architecture is stable for second order or lower order loops but may be unstable for higher order loops. Higher order single-loop designs can be made stable by careful circuit design and thorough simulation. However, the single-loop architecture is more tolerant to circuit mismatch. The selection of the single-loop or MASH architecture is dependent on the requirements of the application. For most applications, the MASH architecture is preferred over the single-loop architecture.

[0055] The noise transfer function H(z) of MASH ADC 12 is determined by the design of loop filters 44. For example, a baseband MASH ΣΔ ADC can be designed by implementing loop filters 44 with lowpass filters. Similarly, a bandpass ΣΔ ADC can be designed by implementing loop filters 44 with bandpass filters. The noise transfer function H(z) of the quantization noise is the inverse of the filter characteristics because the loop filters reside within the loops.

[0056] An exemplary baseband MASH ΣΔ ADC can be designed by implementing loop filters 44 with one or more integrators having the lowpass transfer function $\frac{z^{-1}}{1-z^{-1}}.$

[0057] The number of integrators within loop filters 44 depends on the desired noise transfer function H(z). As shown in FIG. 3A, the lowpass transfer function has a pole at z=+1 and a zero at the origin z=0. The frequency response of the lowpass transfer function is shown in FIG. 3B by the solid line. The lowpass filter has the highest gain at DC because of the pole at z=+1, a gain of 1.0 at fs/6, and a gain of 0.5 at fs/2 where fs is the sampling frequency. The frequency response of the noise transfer function is shown in FIG. 3B by the dashed line. The quantization noise around DC is pushed toward higher frequency.

[0058] An exemplary bandpass MASH ΣΔ ADC can be designed by implementing loop filters 44 with one or more resonators having the bandpass transfer function $\frac{-z^{-2}}{1+z^{-2}}.$

[0059] The number of resonators within loop filters 44 depends on the desired noise transfer function H(z). For example, a fourth order loop requires two resonator sections each having the bandpass transfer function as described above. A bandpass transfer function can be obtained from a lowpass transfer function by substituting z⁻¹in the lowpass transfer function with z⁻². As shown in FIG. 3C, the bandpass transfer function has a pair of poles at z=±j and two zeros at the origin z=0. The frequency response of the bandpass transfer function is shown in FIG. 3D by the solid line. The bandpass filter has the highest gain at fs/4, because of the poles at z=±j, and a gain of 0.5 at DC and at fs/2. The frequency response of the noise transfer function is shown in FIG. 3D by the dashed line. The quantization noise around fs/4 is pushed away from fs/4, the frequency band of interest, toward DC and fs/2.

[0060] II. Bandpass MASH ΣΔ ADC Architecture

[0061] A block diagram of an exemplary two loop bandpass MASH ΣΔ ADC is illustrated in FIG. 4. MASH ADC 100 comprises two loops 110aand 110b, feed forward element 150, and noise cancellation logic 160. In the exemplary embodiment, MASH ADC 100 receives an analog ADC input and produces a digital ADC output having at least two bits, at least one bit for each loop 110.

[0062] The ADC input is provided to loop 110athat produces a 1-bit output Y1 in response thereto. A fraction of the ADC input and quantization noise (X2) from loop 110ais provided to loop 110bwhere additional noise shaping is performed. The outputs Y1 and Y2 from loops 110aand 110b, respectively, are provided to noise cancellation logic 160. Noise cancellation logic 160 combines the outputs Y1 and Y2 and produces the ADC output.

[0063] Within loop 110a, summer 128areceives the ADC input and the 1-bit output Y1 from quantizer 140a. Summer 128asubtracts Y1 from the ADC input and provides the error signal to resonator 130a. Resonator 130afilters the error signal and provides the filtered output (V1) to summer 128b. Summer 128balso receives Y1 from quantizer 140aand subtracts Y1 from V1. The error signal from summer 128bis provided to resonator 130bthat further filters the error signal. The filtered output (V2) from resonator 130bis provided to quantizer 140athat produces the 1-bit output Y1 in response thereto. Loop 110bis connected in similar manner as loop 110a.

[0064] The filtered output V2 from resonator 130bis also provided to gain element 142 which scales V2 by the scaling factor 1/k₁k₂. The output Y1 from quantizer 140ais provided to gain element 144 that scales Y1 by the scaling factor h. The outputs from gain elements 142 and 144 are provided to summer 146 which subtracts the output from gain element 144 from the output from gain element 142. The error signal from summer 146 is provided to gain element 148 that scales the error signal by the scaling factor 1/G. The output from gain element 148 comprises X2 that is provided to loop 110b.

[0065] Within noise cancellation logic 160, the output Y1 is provided to delay element 172 which delays Y1 by a time interval equal to the processing delay of loop 110b. The delayed Y1 from delay element 172 is time aligned with Y2. The output Y2 is provided to gain element 162 which scales Y2 by the scaling factor G. The delayed output Y1 is provided to gain element 166 that scales the delayed Y1 by the scaling factor h-1. The outputs from gain elements 162 and 166 are provided to summer 164 that sums the two scaled outputs. The combined signal from summer 164 is provided to element 168 that filters the combined signal with the transfer function N(z). The output from element 168 and the delayed Y1 are provided to summer 170 which sums the two signals to produce the ADC output.

[0066] For a bandpass ΣΔ ADC, each resonator 130 in MASH ADC 100 is implemented with a bandpass transfer function $\frac{k_n·z^{-m}}{1+z^{-2}},$

[0067] where k_nis the gain of the n-th resonator 130 within loop 110 and m=1 or 2. Each resonator 130 comprises a pair of poles and is second order. Since each loop 110 contains two resonators 130, the order of each loop is four. Overall, MASH ADC 100 is an eighth order MASH 4-4 ADC. The transfer function N(z) within element 168 is selected based on the characteristics of the ΣΔ ADC. For a bandpass ΣΔ ADC, N(z)=(1+z⁻²)². Delay element 172 has a transfer function of z^−2m.

[0068] The gains k₁, k₂, h, and G which are reflected in the scaling factors of gain elements 142, 144, 148, 162, and 166 determine the location of the zeros of the noise transfer function H(z). The poles in resonators 130 are transformed into zeros in the noise transfer function H(z) because the resonators reside within a feedback loop. Initially, the zeros in H(z) are selected to be at z=±j for the bandpass ΣΔ ADC.

[0069] MASH ADC 100, as illustrated in FIG. 4, is a bandpass ΣΔ ADC. The same topology can be used to implement a baseband ΣΔ ADC. This can be easily achieved by substituting each resonator 130 with an integrator having the lowpass transfer function $\frac{z^{-1}}{1-z^{-1}},$

[0070] implementing element 168 with the transfer function N(z)=(1−z⁻¹⁾², and providing delay element 172 with the transfer function z⁻². With these substitutions, MASH ADC 100 is transformed into a fourth order baseband MASH 2—2 ADC.

[0071] In the exemplary embodiment, all elements of MASH ADC 100, except for noise cancellation logic 160, are implemented as analog circuits. However, the optimal implementation of an element in either analog or digital circuit may depend on the IC process used in implementing the ΣΔ ADC. Therefore, the various combinations of analog and digital circuits to synthesize the required elements within MASH ADC 100 are within the scope of the present invention.

[0072] III. Bandpass Resonator Design

[0073] A bandpass MASH 4—4 ADC can be designed by implementing resonators 130 in MASH ADC 100 with a bandpass transfer function $\frac{-z^{-2}}{1+z^{-2}}$

[0074] as described above. Thus, resonators 130a, 130b, 130c, and 130dhave the same structure. However, the gain of resonators 130aand 130cis k₁whereas the gain of resonators 130band 130dis k₂. Resonator 130 is illustrated in FIG. 5A. Resonator 130 can be implemented by many resonator structures, four of which are illustrated in FIGS. 5B-5E. Resonators 131, 132, 133 and 134 receive the input signal Rin and produce the output signal Rout.

[0075] A block diagram of an exemplary delay cell resonator 131 is shown in FIG. 5B. The input signal Rin is provided to gain element 192 that scales the input signal with the gain k_n. The scaled Rin is provided to summer 194 that also receives the output signal Rout and subtracts Rout from the scaled Rin. The error signal from summer 194 is provided to delay element 200athat delays the signal by one clock cycle of the sampling clock. The delayed error signal from delay element 200ais provided to delay element 200bwhich further delays the signal by one sampling clock cycle. The signal from de lay element 200bcomprises the output signal Rout.

[0076] A block diagram of an exemplary lossless discrete integrator (LDI) resonator 132 is shown in FIG. 5C. The input signal Rin is provided to gain element 260 that scales the input signal with the gain k_n. The scaled Rin is provided to summer 262 that also receives the scaled output signal Rout and subtracts the scaled Rout from the scaled Rin. The error signal from summer 262 is provided to filter 264 which filters the signal with the transfer function $\frac{z^{-1}}{1-z^{-1}}.$

[0077] The filtered error signal from filter 264 is provided to filter 266 that further filters the signal with the transfer function $\frac{1}{1-z^{-1}}.$

[0078] The signal from filter 266 comprises the output signal Rout. Rout is provided to gain element 268 that scales Rout with the gain β. In the exemplary embodiment, β=2 and the overall transfer function of resonator 132 is $\frac{k_n·z^{-1}}{1+z^{-2}}.$

[0079] By proper selection of β, the zeros of the noise transfer function can be spread in the signal band.

[0080] A block diagram of an exemplary Forward-Euler (FE) resonator 133 is shown in FIG. 5D. The input signal Rin is provided to gain element 270 that scales the input signal with the gain k_n. The scaled Rin is provided to summer 272athat also receives the scaled output signal Rout and subtracts the scaled output signal Rout from the scaled input signal Rin. The error signal from summer 272ais provided to filter 274athat filters the signal with the transfer function $\frac{k_n·z^{-2}}{1+z^{-2}}.$

[0081] The filtered error signal from filter 274ais provided to summer 272bthat also receives the scaled Rout and subtracts the scaled Rout from the filtered error signal. The error signal from summer 272bis provided to filter 274bthat filters the signal with the transfer function $\frac{k_n·z^{-2}}{1+z^{-2}}.$

[0082] The signal from filter 274bcomprises the output signal Rout. Rout is provided to gain element 276 that scales the output signal Rout with the gain β. In the exemplary embodiment, β=2 and the overall transfer function of resonator $\frac{k_n·z^{-2}}{1+z^{-2}}.$

[0083] A block diagram of an exemplary two-path interleaved resonator 134 is shown in FIG. 5E. The input signal Rin is provided to gain element 280 that scales the input signal with the gain k_n. The scaled Rin is provided to switches 282aand 282bwhich connects the scaled Rin to summers 284aand 284b, respectively. Summer 284 also receives the delayed error signal from delay elements 286 and subtracts the delayed error signal from the scaled Rin. The error signal from summer 284 is provided to delay element 286 which delays the error signal by one sampling clock cycle. The delayed error signal from delay elements 286aand 286bare provided to switches 288aand 288b, respectively. Switches 288aand 288bconnect together and comprise the output of resonator 134. Switches 282aand 288aare clocked by one phase of a switching clock and switches 282band 288bare clocked by a second phase of the switching clock. The clock signals are described in detail below. The overall transfer function of resonator 134 is $\frac{k_n·z^{-2}}{1+z^{-2}}.$

[0084] Resonators 131, 132, 133 and 134 can be implemented by numerous analog circuit techniques. For example, resonators 131, 132, 133 and 134 can be implemented with continuous time analog circuit techniques such as active-RC, gm-C, and MOSFET-C. Resonators 131, 132, 133 and 134 can also be implemented with sampled-data analog circuit techniques such as switched capacitor and switched current. The selection of the analog circuit technique depends on the requirement of the application for which the ΣΔ ADC is used. For an exemplary CDMA application wherein a 12-bit ΣΔ ADC operating at a sampling rate of 80 MHz, the performance of the various circuit techniques is tabulated in Table 2.

[0085] The implementation of the functions as described herein using any one of the circuit techniques listed in Table 2, or its equivalents, are within the scope of the present invention. In the preferred embodiment, resonators 131, 132, 133 and 134 are implemented with a switched capacitor circuit technique because of superior performance in SNR, accuracy, speed, and cost.

[0086] The design of resonator 131 using the switched capacitor circuit technique is described in detail below. Within resonator 131, each delay element 200 can be implemented by one of many analog circuit techniques. In the preferred embodiment, delay element 200 is implemented with a double-sampling switched capacitor delay circuit 210 as illustrated in FIG. 6A. For optimal linearity and noise performance, delay circuit 210 is implemented as a fully differential circuit, where the input comprises Rin+ and Rin− and the output comprises Rout+ and Rout−.

[0087] Within delay circuit 210, the input signal Rin+ is provided to two signal paths through switches 220aand 224a. Switch 220aconnects to one end of capacitor 228aand switch 236a. The other end of capacitor 228aconnects to switches 222aand 232a. Switch 222aalso connects to AC ground 202. Switch 232aalso connects to the inverting input of amplifier 250 and switch 236aalso connects to the non-inverting output of amplifier 250. In similar manner, switch 224aconnects to one end of capacitor 230aand switch 238a. The other end of capacitor 230aconnects to switches 226aand 234a. Switch 226aalso connects to AC ground 202. Switch 234aalso connects to the inverting input of amplifier 250 and switch 238aalso connects to the non-inverting output of amplifier 250. Delay circuit 210 is a fully differential circuit. The lower half of delay circuit 210 is a mirror image of the upper half.

[0088] AC ground 202 is implemented as a DC bias voltage with a capacitor bypass to ground. The DC bias voltage determines the mid-scale voltage of the differential signal at that node. For best linearity, the signals Rin+ and Rin− are normally biased near the operating center of amplifier 250. In some circuit design, the differential output Rout+ and Rout− can have a different optimal DC bias voltage than that of the input Rin.

[0089] Delay circuit 210 samples the input signal Rin on two phases of the switching clock. Referring to FIG. 6B, the sampling clock fs is divided by two to obtain the switching clock. In the exemplary embodiment, the clock signal CLK1 having the first clock phase ø1 is provided to the switches which are shown without the bubble (e.g. switch 224a). The clock signal CLK2 having the second clock phase ø2 is provided to the switches which are shown with the bubble (e.g. switch 220a). Each clock signal should have a duty cycle that is less than 50 percent. The minimum width of the clock signals is determined by the charging time of the capacitors which, in turn, is determined by the size of the capacitor and the ON resistance of the switches.

[0090] Referring to FIG. 6A, during the first clock phase ø1, switches 224aand 226aare switched ON and capacitor 230ais charged with the input signal Rin+. During the second clock phase ø2, switches 224aand 226aare switched OFF, switches 234aand 238aare switched ON, and the voltage across capacitor 230ais provided to the output Rout+. Capacitor 230ais charged during the first clock phase ø1 and provided to the output Rout+ during the second clock phase ø2. Therefore, the delay provided by delay circuit 210 is a half switching clock cycle, or one sampling clock cycle. Similarly, capacitor 228ais charged during the second clock phase ø2 and provided to the output Rout+ during the first clock phase ø1. The two signal paths, one through capacitor 230aand the second through capacitor 228a, operate on different clock phases and only share amplifier 250.

[0091] Using double-sampling switched capacitor circuit, the input signal Rin is provided to the output Rout on both phases of the switching clock, through two signal paths, thereby resulting in the sampling of Rin at the sampling clock frequency fs even though the switches are switched ON and OFF at half the sampling clock (fs/2). A double-sampling switched capacitor circuit allows the switches to be clocked at half the sampling frequency, thus allowing the capacitors and amplifier more time to settle to the final value. Since the operating speed of a switched capacitor circuit is determined by the settling time of the amplifier used in the circuit, using the same amplifier during both phases of the switching clock increases the sampling rate by a factor of two without requiring faster settling amplifier.

[0092] However, double-sampling switched capacitor circuits are sensitive to path mismatch. Mismatch in the first sampling stage of the ΣΔ ABC can cause degradation in the output samples. Mismatch in the subsequent stages is noise shaped and does not result in noticeable degradation. Any mismatch between the two signal paths, such as mismatch in the capacitors or mismatch due to uneven clock phases, in the first stage produces an image of the input signal to appear at the output samples. By using good circuit design rules, the capacitor mismatch can be reduced to one percent or less, thereby minimizing the amplitude of the image to −40 dB or more below the amplitude of the input signal. The switching clocks can be designed to minimize uneven clock phases. Alternatively, the first sampling stage can be clocked with a master clock, before the divide-by-two operation to obtain the switching clocks. Clock jitter can be reduced by using a clean external clock source. This topology also have faster settling time than the single-sampled topology because of less amplifier loading.

[0093] IV. Bandpass MASH 4-4 ADC Design

[0094] Referring to FIG. 4, each loop 110 comprises two resonator sections 120. Each resonator section 120 comprises summer 128 and resonator 130. Resonator 130 can be implemented as delay cell resonator 131 as shown in FIG. 5B. Each delay cell resonator 131 comprises two delay elements 200. Each delay element 200 can be implemented with double-sampling switched capacitor delay circuit 210 as show n in FIG. 6A.

[0095] A schematic diagram of double-sampling switched capacitor resonator circuit 121, which implements resonator section 120, is shown in FIG. 7A. Resonator circuit 121 comprises delay element and summer circuit 300 and delay circuit 310. Circuit 300 incorporates summer 128, gain element 192, summer 194, and delay element 200a(see FIGS. 4 and 5B). Delay circuit 310 implements delay element 200b.

[0096] Referring to FIG. 7A, within circuit 300, the input signal Vip is provided to two signal paths, the first signal path through switch 324a. Switch 324aconnects to one end of capacitor 330aand switch 314a. The other end of capacitor 330aconnects to switches 326aand 334a. Switch 326aalso connects to AC ground 202 and switch 334aalso connects to the inverting input of amplifier 350a. Switch 314aconnects to the quantizer output Ypø1 that is described below. Switches 326aand 334aconnect to one end of capacitor 318a. The other end of capacitor 318aconnects to switches 344aand 338a. Switch 338aalso connects to the non-inverting output of amplifier 350a. Switch 344aalso connects to the inverting output of amplifier 350bwithin delay circuit 310.

[0097] The operation of the first signal path in circuit 300 can be described as follows. During the first clock phase ø1, switches 324aand 326aare switched ON and capacitor 330ais charged with the input signal Vip. During the second clock phase ø2, switches 324aand 326aare switched OFF and switches 314a, 334a, and 338aare switched ON. The input signal Yxpø1 and the voltage across capacitor 330aare scaled by the ratio of capacitors 330aand 318a(Cs/Cf) and provided to the non-inverting output of amplifier 350a. Also during the first clock phase ø1, switch 344ais switched ON and the signal from the inverting output of amplifier 350bis fed back, charging capacitor 318a. The voltage across capacitor 318ais reflected at the non-inverting output of amplifier 350aduring the second clock phase ø2.

[0098] The above discussion describes the circuit connection and operation of the first signal path within circuit 300. An identical circuit is provided for the second signal path which operates in the same manner as that of the first signal path, except the switches are clocked at the alternative phase of the switching clock. Thus, the input signal Vip is provided to the output of amplifier 350aon both phases of the switching clock and results in the sampling of the input signal at the sampling rate.

[0099] Circuit 300 is a fully differential circuit. An identical circuit is provided for the inverting input signal Vin. The lower half of circuit 300 is the mirror image of the upper half.

[0100] Circuit 300 includes the functions of summer 128, gain element 192, and summer 194 (see FIGS. 4 and 5B). The function of summer 194 is provided by switches 342 and 344 which connects the output of the second delay element to capacitors 316 and 318, respectively. The voltage Von is stored in capacitor 318aduring the first clock phase ø1 and subtracted from the voltage at Vb during the second clock phase ø2. The function of summer 128 is provided by switches 312 and 314 that connect the quantizer output to capacitors 328 and 19330, respectively. The quantizer output voltage Ypø1 is provided to capacitor 330aduring the second clock phase ø2 and is added to the voltage at Vb.

[0101] Delay circuit 310 is identical to delay circuit 210 in FIG. 6A and operates in the same manner as that described above for delay circuit 210. Delay circuit 310 delays the output from circuit 300 by a half switching clock cycle, or one sampling clock cycle. The output from amplifier 350bcomprises the output of resonator circuit 121.

[0102] Resonator circuit 121 has the following transfer function from Vip to Vop $\begin{array}{cc}{H}_R\left(z\right)=\frac{C_s}{C_f}·\frac{z^{-2}}{1+z^{-2}}.& \left(3\right)\end{array}$

[0103] The transfer function from Yxpø1 to Vop is −H_R(z). In this nomenclature, Yx denotes the quantizer output from the first (x=1) or second (x=2) loop, p or n denotes a (+) or (−) signal, and ø1 or ø2 denotes the clock phase of the quantizer output. The voltage gain from Yxpø1 to Vop is −Cs/Cf, the ratio of capacitor 330ato capacitor 318a. Thus, the gain of gain element 192 can be set as k_n=Cs/Cf.

[0104] Having implemented each resonator section 120 with resonator circuit 121, MASH ADC 100 in FIG. 4 can be implemented as an eighth order bandpass MASH 4-4 ADC 101 as shown in FIG. 8. Each resonator section 120 in FIG. 4 is replaced with double-sampling switched capacitor resonator circuit 121 in FIG. 8. Within resonator circuit 121, the feedback from delay circuit 310 to circuit 300 is not shown for simplicity. Also, note that noise cancellation logic 160 in FIG. 4 is not shown in FIG. 8 for simplicity.

[0105] Quantizer 140ain FIG. 4 is implemented with quantizer 141awhich comprises two synchronous comparators 390aand 390b. Comparator 390ais clocked by CLK1 having the first phase ø1 and comparator 390bis clocked by CLK2 having the second phase ø2 (see FIG. 6B). The differential input signals to comparators 390aand 390bare provided by the output of circuit 300b. This is because quantizer 141ahas a delay of a half switching clock cycle. The input to quantizer 141ais taken before delay circuit 310bwhich also provides a delay of a half switching clock cycle. Connected in this manner, quantizer 141ais properly aligned in time. Each comparator 390 provides a differential output. Comparator 390aprovides the differential output signals Y1pø1 and Y1nø1 and comparator 390bprovides the differential output signals Y1pø2 and Y1nø2. The four quantizer outputs, collectively referred to as Y1, are provided to circuits 300a, 300b, and 151 as shown by FIGS. 4 and 8.

[0106] Referring to FIGS. 4 and 8, feed forward gain element 150 can be incorporated into circuit 300cto simplify the circuit design. Referring to FIG. 4, the gain from the output (V2) of resonator 130bto X2 is 1/k₁k₂G and the gain from the output (Y1) of quantizer 140ato X2 is −h/G. The overall transfer function of feed-forward gain element 150 can be calculated as X2=Av1·V2−Av2·Y1, where Av1=1/k₁k₂G and Av2=h/G.

[0107] The gains k₁, k₂, h, and G of bandpass MASH 4-4 ADC 101 are selected for optimal SNR and ease of circuit implementation. Using mixed analog and digital design simulation tools, the following exemplary values are selected for the gains: $\begin{array}{cc}{k}_1=0.5,k_2=0.5,h=2,G=4.& \left(4\right)\end{array}$

[0108] Other values for gains k₁, k₂, h, and G can also be utilized and are within the scope of the present invention. Using the gain values as shown in equation (4), and an oversampling ratio of 32, the SNR versus input signal level is plotted in FIG. 9. The peak SNR surpasses 90 dB.

[0109] A schematic diagram of an exemplary feed-forward gain circuit 151, which in conjunction with circuit 300cimplements feed-forward gain element 150, is illustrated in FIG. 7B. The quantizer outputs Y1pø2, Y1pø1, Ynø1, and Y1nø2 from quantizer 141a(see FIG. 8) are provided to switches 372a, 376a, 376b, and 372b, respectively. Switches 372a, 376a, 376b, and 372bconnect to one end of capacitors 380a, 382a, 382b, and 380bwhich are connected to node Va, Vb, Vc, and Vd within resonator circuit 121 in FIG. 7A, respectively. The other end of capacitors 380a, 382a, 382b, and 380b, connect to switches 374aand 384a, 378aand 386a, 378band 386b, and 374band 384b, respectively. Switches 374a, 378a, 378b, 374b, 384a, 386a, 386b, and 384balso connect to AC ground 202.

[0110] The gain values Av1 and Av2 can be calculated and incorporated into feed forward gain circuit 151. Using the values of k₁=0.5, k₂=0.5, h=2, and G=4 from equation (4), the gain values become Av1=1.0 and Av2=0.5. Referring to FIGS. 7A and 7B, the gain from the output Y1pø1 of quantizer 141ato the non-inverting output of amplifier 350ais determined by the ratio of capacitors 382aand 318a, or Av2=Cq/Cf=0.5. Therefore, the capacitance of capacitor 382ais synthesized to be half of the value of capacitor 318a. Referring to FIG. 8, the gain from the output V2p of resonator circuit 121b(corresponding to Vip in FIG. 7A) to the non-inverting output of amplifier 350ais determined by the ratio of capacitors 330aand 318a, or Av1=Cs/Cf=1.0. Thus, the value of capacitor 330ais synthesized to be the same capacitance as capacitor 318a. However, capacitors 330aand 318aalso implement gain element 192 (see FIG. 5B). In the exemplary embodiment, the gains kn=k₁=k₂=0.5 as shown in equation (4). Therefore, capacitor 330ais selected to be half the capacitance of capacitor 318a.

[0111] In the exemplary embodiment, noise cancellation circuit 160 in FIG. 4 is implemented in digital logic. For an eighth order bandpass MASH ΣΔ ADC, delay element 172 has a transfer function of z⁻⁴and can be implemented with four D flip-flops connected in cascade, the design and implementation of which are known in the art. The transfer function of element 168 is N(z)=(1+z⁻²)²which can be implemented with two summers and four sets of D flip-flops, the implementation of which is also known in the art.

[0112] As stated above, double-sampling switched capacitor circuits are sensitive to path mismatch. However, path mismatch in the stages subsequent to the first sampling stage is noise shaped and does not cause a noticeable image. Referring to FIG. 8, within delay element and summer circuit 300a, which is illustrated in FIG. 7A, only the input sampling capacitors 328 and 330 are sensitive to mismatch in capacitor values and only input sampling switches 320, 322, 324, and 326 are sensitive to uneven clock phases of the switching clocks. Path mismatch can be minimized by the use of circuit design techniques described below.

[0113] Referring to FIG. 3D, bandpass MASH 4-4 ADC 101 provides noise shaping of the quantization noise such that the spectral components around fs/4 is pushed toward DC and fs/2. For optimal performance, the input signal being sampled should be placed close to fs/4. For undersampling applications, wherein the input signal is centered at an IF which is higher than the sampling frequency and the aliasing property of sampling is used to downconvert the input signal from IF to a lower frequency, the input signal should be placed close to IF=(2n+1)·fs/4, where n is an integer greater than or equal to zero.

[0114] V. Alternative Bandpass Resonator Design

[0115] A bandpass resonator can be synthesized by various other structures, three of which are illustrated in FIGS. 5C-5E. In the exemplary embodiment, lossless discrete integrator (LDI) resonator 132 in FIG. 5C is implemented with single-sampling switched capacitor LDI resonator circuit 402 in FIG. 10A, Forward-Euler (FE) resonator 133 in FIG. 5D is implemented with single-sampling switched capacitor FE resonator circuit 403 in FIG. 10B, and two-path interleaved resonator 134 in FIG. 5E is implemented with pseudo two-path switched capacitor resonator circuit 502 in FIG. 10C and two independent path resonator circuit 503 in FIGS. 10E-10F. These are exemplary implementations of resonators 132, 133 and 134. Other implementations utilizing the circuit techniques listed in Table 2 are within the scope of the present invention.

[0116] An implementation of delay cell based resonator 132 using single-sampling switched capacitor circuit is shown in FIG. 10A. Within the first section of LDI resonator circuit 402, the input signal Vip is provided to switch 414a. Switch 414aconnects to one end of capacitor 422aand switch 418a. The other end of capacitor 422aconnects to switches 424aand 426a. Switches 418aand 424aalso connect to AC ground 202. Switches 426aand 430aand one end of capacitor 436aconnect to the inverting input of amplifier 450a. The other end of capacitor 436aconnects to switches 440aand 444a. Switch 440aalso connects to AC ground 202 and switch 444aalso connects to the non-inverting output of amplifier 450a. Switch 430aalso connects to switch 432aand one end of capacitor 434a. The other end of capacitor 434aconnects to switches 438aand 442a. Switches 432aand 438aalso connect to AC ground 202 and switch 442a also connects to the non-inverting output of amplifier 450a.

[0117] A second section identical to the first second is connected in cascade with the first section. The output of the second section is fed back to the first section. The inverting output of amplifier 450bconnects to switch 412a. Switch 412aalso connects to switch 416aand one end of capacitor 420a. Switch 416aalso connects to AC ground 202. The other end of capacitor 420aconnects to switches 424aand 426a. LDI resonator circuit 402 is a fully differential circuit. The lower half of LDI resonator circuit 402 is a mirror image of the upper half. The output of amplifier 450bcomprises the output of resonator circuit 402.

[0118] LDI resonator circuit 402 is clocked at the sampling frequency. LDI resonator circuit 402 has a resonant frequency that is a function of the sampling frequency and the capacitor ratios. The transfer function of LDI resonator circuit 402 is: $\begin{array}{cc}{H}_{\mathrm{LDI}}\left(z\right)=\frac{z^{-1}}{1+\left(2-\beta \right)z^{-1}+z^{-2}},& \left(5\right)\end{array}$

[0119] where Cs=Ch=Ci and β=Cf/Cs. By changing β, the zeros of the noise transfer function H(z) for a ΣΔ ADC utilizing LDI resonators can be spread about fs/4. LDI resonator circuit 402 is not effective for oversampling ratio of greater than 16 because of sensitivity to capacitor mismatch.

[0120] An implementation of FE resonator 133 using single-sampling switched capacitor circuit is shown in FIG. 10B. Within the first section of FE resonator circuit 403, the input signal Vip is provided to switch 472a. Switch 472aconnects to one end of capacitor 476aand switch 474a. The other end of capacitor 476aconnects to switches 478aand 482aand one end of capacitor 480a. Switches 474aand 478aalso connect to AC ground 202. Switch 482aalso connects to the inverting input of amplifier 490a. Capacitor 484aconnects to the inverting input and the non-inverting output of amplifier 490a.

[0121] A second section identical to the first section is connected in cascade with the first section. The output of the second section is fed back to the first section. The inverting output of amplifier 490bconnects to switch 488c. Switch 488cconnects to switch 486cand the other end of capacitors 480aand 480c. Switch 486calso connects to AC ground 202. FE resonator circuit 403 is a fully differential circuit. The lower half of FE resonator circuit 403 is a mirror image of the upper half. The output of amplifier 490bcomprises the output of resonator circuit 403.

[0122] FE resonator circuit 403 is clocked at the sampling frequency. FE resonator circuit 403 has a resonant frequency that is a function of the sampling frequency and the capacitor ratios. The transfer function of FE resonator circuit 403 is: $\begin{array}{cc}{H}_{\mathrm{FE}}\left(z\right)=\frac{z^{-2}}{1+\left(2-\beta \right)z^{-1}+z^{-2}},& \left(6\right)\end{array}$

[0123] where Cf1=Cf2=Cf, Cs1=Cs2=Ci1=Ci2=Ci, and β=Cf/Ci. By changing β, the zeros of the noise transfer function H(z) for a ΣΔADC utilizing FE resonators can be spread about fs/4. FE resonator circuit 403 has a faster settling time than LDI resonator circuit 402.

[0124] An implementation of two-path interleaved resonator 134 using pseudo two-path single-sampling switched capacitor circuit is shown in FIG. 10C. Within resonator circuit 502, the input signal Vip is provided to switch 512a. Switch 512aconnects to one end of capacitor 516aand switch 514a. The other end of capacitor 516aconnects to switches 518aand 520a. Switches 514aand 518aalso connect to AC ground 202. Switches 520aand 524aand one end of capacitor 534aconnect to the inverting input of amplifier 550. The other end of capacitor 534aconnects to switches 540aand 546a. Switch 540aalso connects to AC ground 202 and switch 546aalso connects to the non-inverting output of amplifier 550. Switch 524aalso connects to switches 522a, 526a, and 528a. Switch 522aalso connects to the non-inverting input of amplifier 550. Switches 526aand 528aalso connect to one end of capacitors 530aand 532a, respectively. The other end of capacitor 530aconnects to switches 536aand 542a. The other end of capacitor 532aconnects to switches 538aand 544a. Switches 536aand 538aalso connect to AC ground 202 and switches 542aand 544aalso connect to the non-inverting output of amplifier 550. Resonator circuit 502 is a fully differential circuit. The lower half of resonator circuit 502 is a mirror image of the upper half. The output of amplifier 550 comprises the output of resonator circuit 502.

[0125] Resonator circuit 502 is clocked at the sampling frequency. Resonator circuit 502 has a resonant frequency that is a function of the sampling frequency and the capacitor ratios. The advantage of resonator circuit 502 is that only one amplifier 550 is required for two delays. The disadvantages are the needs for eight clock phases and the need to operate resonator circuit 502 at the sampling frequency. The required clock signals for resonator circuit 502 are shown in FIG. 10D. The transfer function of resonator circuit 502 is: $\begin{array}{cc}{H}_{\mathrm{PTP}}\left(z\right)=\frac{C_s}{C_h}·\frac{z^{-2}}{1+z^{-2}}.& \left(7\right)\end{array}$

[0126] Two-path interleaved resonator 134 can also be implemented using two independent path single-sampling switched capacitor circuit as shown in FIGS. 10E-10F. Within resonator circuit 503a, the input signal Vip is provided to switch 562a. Switch 562aconnects to one end of capacitor 566aand switch 564a. The other end of capacitor 566aconnects to switches 568aand 570a. Switches 564aand 568aalso connect to AC ground 202. Switch 570aand one end of capacitor 578aconnect to the inverting input of amplifier 590a. The other end of capacitor 578aconnects to the non-inverting output of amplifier 590a. Switch 574aconnects to the non-inverting input of amplifier 590a. Switch 574aalso connects to switch 572 and one end of capacitor 576a. The other end of capacitor 576aconnects to switches 580aand 582a. Switches 572aand 580aalso connect to AC ground 202. Switch 582aalso connects to the non-inverting output of amplifier 590a. The non-inverting output of amplifier 590aconnects to switch 584a. The other end of switch 584acomprises the output signal Vop.

[0127] Resonator circuit 503ais a fully differential circuit. The lower half of resonator circuit 503ais a mirror image of the upper half. Resonator circuit 503acomprises one signal path of the input signal. An identical resonator circuit 503bcomprises the second signal path. Resonator circuit 503bis connected in the same manner as resonator circuit 503abut the switches operate on the alternative clock phases.

[0128] Resonator circuit 503 is clocked at half the sampling frequency. Resonator circuit 503 has a resonant frequency that is a function of the sampling frequency and the capacitor ratios. Resonator circuit 503 has a fast settling time. However, because of the two independent paths, path matching is more difficult to maintain. The transfer function of resonator circuit 503 is: $\begin{array}{cc}{H}_{\mathrm{TIP}}\left(z\right)=\frac{C_1}{C_3}·\frac{z^{-2}}{1+z^{-2}}.& \left(8\right)\end{array}$

[0129] VI. Multi-Sampling Bandpass Resonator Design

[0130] The double-sampling switched capacitor bandpass resonator circuit of the present invention can be further expanded to multi-sampling resonator circuits. A schematic diagram of an exemplary quadruple-sampling switched capacitor resonator circuit 802 is illustrated in FIG. 10G. FIG. 10G only illustrates the upper half of resonator circuit 802. The lower half, to which the Vin of the differential input is applied, is identical to the upper half and not shown for simplicity.

[0131] Within resonator circuit 802, the input signal Vip is provided to four signal paths, the first signal path through switch 820a. Switch 820aconnects to one end of capacitor 824aand switch 826a. Switch 826aconnects to the quantizer output Yxpø1. The other end of capacitor 824aconnects to switches 822aand 830aand one end of capacitor 828a. Switch 822aalso connects to AC ground 202 and switch 830aalso connects to the inverting input of amplifier 850a. The other end of capacitor 828aconnects to switches 832aand 834a. Switch 832aalso connects to the non-inverting output of amplifier 850aand switch 834aalso connects to the inverting output of amplifier 850a.

[0132] The operation of the first signal path in resonator circuit 802 can be described as follows. During the first clock phase ø1, switches 820aand 822aare switched ON and capacitor 824ais charged with the input signal Vip. During the third clock phase ø3, switches 820aand 822aare switched OFF and switches 826a, 830a, and 834aare switched ON. The signal Yxpø1 and the voltage across capacitor 824aare scaled by the ratio of capacitors 824aand 828a(Cs/Cf) and provided to the non-inverting output of amplifier 850a. Also during the first clock phase ø1, switch 832ais switched ON and the signal from the inverting output of amplifier 850ais fed back, charging capacitor 828a. The voltage across capacitor 828ais reflected at the non-inverting output of amplifier 850aduring the third clock phase ø3. The non-inverting output from amplifiers 850aand 850bcomprises the outputs Vop13 and Vop23, respectively, which are provided to the next resonator section.

[0133] The other three signal paths are connected in similar manner as shown in FIG. 10G. The other three signal paths also operate in similar manner as the first signal path. However, the switches in the other three signal paths are switched with switching clocks having different phases as shown in FIG. 10H. Thus, each switch in resonator circuit 802 is switched ON and OFF every four sampling clock cycles. This allows amplifiers 850 more time to settle to the final value. Viewed in another way, an amplifier having a specified performance can be used to implement a ΣΔ ADC which is effectively sampled at four time the switching frequency. However, path mismatch due to mismatch in capacitor values, uneven clock phases of the switching clocks, and amplifier mismatch can cause images to appear the ADC output.

[0134] VII. Other Considerations

[0135] Double-sampling switched capacitor circuits for the ΣΔ ADC of the present invention are sensitive to path mismatch which can result from mismatch in capacitor values and/or uneven phases of the switching clocks. Capacitor mismatch can be reduced to less than one percent by utilizing circuit design techniques which are known in the art, such as the common centroid layout technique.

[0136] Double-sampling switched capacitor circuits sample the signal on two phases of the switching clock. The switching clock is a divide-by-two of the sampling clock (see FIG. 6B). If the divide-by-two causes any phase asymmetry, the phase mismatch causes an image of the input signal to appear at the output. Using the master clock, e.g. the sampling clock, before the divide-by-two operation, to clock the first sampling stage (switches 320, 322, 324, and 326 in FIG. 7A) will resolve this problem.

[0137] Clock jitter in the first sampling stage is also critical. Clock jitter translates to quantization noise. Clock jitter can be reduced by clocking the first sampling stage with a clean external clock source. For undersampling application wherein the ADC is used to downconverts a signal at IF down to a lower frequency, the jitter spectral density is increased by the square of the undersampling ratio. For example, for an IF of 220 MHz and a sampling rate of 80 MHz, the phase noise is increased by 8.8 dB [20log(220 MHz/80 MHz)]. For undersampling applications, the clock jitter requirement is more stringent.

[0138] The ΣΔ ADC of the present invention has been described in detail for a bandpass MASH 4-4 ΣΔ ADC which is implemented with double-sampling switched capacitor circuits. The circuit design techniques described above can also be applied to a single-loop LA ADC architecture which is shown in FIG. 1. Thus single-loop ΣΔ ADCs are within the scope of the present invention.

[0139] A baseband ΣΔ ADC can be designed by implementing the filters in FIGS. 1-2 with a lowpass filter. For example, a baseband MASH 2—2 ADC can be designed by substituting resonators 130 in FIG. 4 with integrators having the lowpass transfer function $\frac{z^{-1}}{1-z^{-1}}.$

[0140] Thus, baseband single-loop and MASH ΣΔ ADCs are within the scope of the present invention.

[0141] The filters in the τΔ ADCs of the present invention can be implemented with various analog circuit design techniques, including active RC, gm-C, MOSFET-C, switched capacitor, and switched current. Furthermore, the switched capacitor and switched current circuits can be single-sampling, double-sampling, or multi-sampling designs.

[0142] Therefore, the various combinations and permutations of bandpass and baseband τΔ ADC implemented with single-loop and MASH architectures which are synthesized with active RC, gm-C, MOSFET-C, switched capacitor, or switched current utilizing single-sampling, double-sampling, or multi-sampling designs are within the scope of the present invention.

[0143] Some embodiments of the invention have been described with circuitry implemented using MOSFETs. The invention can also be implemented with other circuits including BJTs, FETs, MESFETs, HBTs, P-HEMTs, and others. Also, P-MOS and N-MOS can be used to implement the invention. As used herein, “transistor” generically refers to any active circuit, and is not limited to a BJT.

[0144] VIII. Minimizing Power Consumption

[0145] In many applications, such as CDMA communication system, power consumption is an important design consideration because of the portable nature of the telephone wherein the ΣΔ ADC of the present invention reside. The ΣΔ ADC can be designed to minimize power consumption by allowing for selective sections of the ΣΔ ADC to be disabled when high dynamic range is not required. In addition, the τΔ ADC can be designed to allow for adjustment of the bias current based on the signal level of the ADC input and the required performance.

[0146] In the exemplary embodiment, the ΣΔ ADC provides 12-bits of resolution. This design anticipates the worse case signal level into the ΣΔ ADC. For CDMA applications, approximately 4-bits of resolution is needed for the desired signal (e.g. the CDMA signal) and the remaining 8-bits of resolution are reserved for spurious signals of large amplitude (or jammers) and for AGC control. In the exemplary embodiment, the 12-bits of resolution is provided by a two-loop MASH 4-4 architecture. Referring to FIG. 4, loop 110aprovides high dynamic range and a low noise floor. Loop 110bprovides additional dynamic range but has a slightly higher noise floor than loop 110a. The lower noise floor of loop 110ais the result of having larger capacitors and biasing the amplifiers within loop 110awith higher bias current.

[0147] In the present invention, each loop can be selectively disabled, based on the signal level of the ADC input and the required performance, to minimize power consumption. Furthermore, the bias current of the amplifier within each resonator 130 can be adjusted based on the signal level of the ADC input and the required performance. When high dynamic range is required, the ADC input is provided to loop 110a, the bias current of all amplifiers is set high, and MASH ADC 100 operates in the manner described above. This situation may result from an ADC input comprising the CDMA signal and two large jammers at +58 dBc or an ADC input comprising the CDMA signal and one large jammer at +72 dBc. These requirements are specified by the “TIA/EIA/IS-98-A Intermodulation Spurious Response Attenuation”, hereinafter the IS-98-A standard. In practice, this situation occurs infrequently.

[0148] As the jammer amplitude decreases, high dynamic range is not required. When this occurs, loop 110bcan be disabled and the output Y1 from loop 110acomprises the ΣΔ ADC output. Alternatively, loop 110acan be disabled, the ADC input can be provided to loop 110b, and the output Y2 from loop 110bcomprises the ΣΔ ADC output. Thus, one to two loops can be enabled to provide the required dynamic range.

[0149] The bias current of the amplifier in each resonator 130 can be adjusted to minimize power consumption while providing the required performance. In the exemplary embodiment, loop 110ais designed to consume a maximum of 10 mA of bias current and second loop 110bis designed to consume a maximum of 8 mA of bias current. In the exemplary embodiment, within loop 110a, the amplifier within resonator 130ais designed to consume 6 mA and the amplifier within resonator 130bis designed to consume 4 mA. When high dynamic range is required, the bias current for each amplifier is set high. When high dynamic range is not required, the bias current can be decreased. For example, the bias current of the amplifier within resonator 130acan be decreased from 6 mA down to 2 mA and the bias current of the amplifier within resonator 130bcan be decreased from 4 mA down to 2 mA. Similarly, the bias current for the amplifiers within loop 110band be decreased accordingly when high dynamic range is not required.

[0150] Adjustment of the amplifier bias current can be performed independently of the disablement of the loops, or can be performed in conjunction with the disablement of the loops. In fact, analysis and measurements can be performed to ascertain the dynamic range of various configurations of the ΣΔ ADC. Then, based on the required dynamic range, the ΣΔ ADC can be configured accordingly. The various methods used to configure the ΣΔ ADC to minimize power consumption are within the scope of the present invention.

[0151] In the exemplary embodiment, the required dynamic range can be estimated by measuring the power level of the desire signal (e.g. the CDMA signal) and the power level of the ADC input. The power level of the ADC input can be measured by a power detector. The power detector can be implemented in the manner known in the art. The power level of the desired signal can be measured by computing the RSSI of the desired signal, after the digital signal processing to remove undesirable images and spurious signals. The RSSI measurement is described in detail in U.S. Pat. No. 5,107,225, entitled “HIGH DYNAMIC RANGE CLOSED LOOP AUTOMATIC GAIN CONTROL CIRCUIT”, issued Apr. 21, 1992, assigned to the assignee of the present invention and incorporated by reference herein. Alternatively, the required dynamic range can be determined based on the operating mode of the receiver wherein the ΣΔ ADC resides.

[0152] IX. Control Circuit

[0153] As noted above, to reduce power consumption while still provide the required data conversion performance, a control mechanism is used to selectively enable one or more loops of the ΣΔ ADC and to disable the remaining loops. The control mechanism measures one or more characteristics (e.g., signal level) of the ADC input signal, compares the measured characteristic(s) to particular threshold level(s), and controls the loops such that the desired or required performance is achieved.

[0154] Many challenges arise in designing such control mechanism. First, for a ΣΔ ADC that is used in a receiver of a communications device, the amplitude of the input signal is typically very small, even after the signal conditioning (e.g., low noise amplification, and so on). In fact, for a cellular application, the input signal amplitude can be as small as 30 mV peak-to-peak or less. Thus, a detector within the control mechanism should be able to accurately measure a small amplitude input signal.

[0155] Second, for a ΣΔ ADC that is used as a bandpass sampling converter, the input signal is centered at IF and can have high frequency components. For a specific CDMA application, the input signal can have frequency components as high as 240 MHz or more. To avoid attenuating high frequency components, the detector can be designed with components (e.g., switches, transistors, and so on) having large dimensions, which can provide low loss at high frequency. However, large-sized components increase die area and cost. Higher operating frequency also typically requires larger amounts of bias current, which is undesirable in portable applications such as cellular telephone.

[0156] Third, the ADC input signal is typically buffered by an amplifier or a buffer that can introduce a DC offset to the signal. The DC offset can be a large percentage of the input signal amplitude. For example, an input signal having an amplitude of 30 mVpp may also have a DC offset of 10 mV, or possibly more. Thus, the detector should, to an extent, be insensitive to the DC offset in the input signal. Moreover, the detector should also be insensitive to its internally generate DC offset.

[0157] As can be seen, a control mechanism that addresses the above challenges is highly desirable.

[0158] FIG. 11 shows a simplified block diagram of a specific embodiment of a control circuit 1110 for controlling a ΣΔ ADC 1120. As shown in FIG. 11, ΣΔ ADC 1120 includes two cascaded ΣΔ stages 1122aand 1122bdriven by a buffer (BUF) 1124. Each ΣΔ stage 1122 can represent a loop of a multi-loop ΣΔ ADC, such as loop 110 and it associated feed forward element 150 shown in FIG. 4. Each ΣΔ stage 1122 can also represent a filter section of a multi-section ΣΔ ADC, such as filter section 24 or 28 shown in FIG. 1. Generally, each ΣΔ stage 1122 can represent any portion of a circuit that can be selectively enabled and disabled. When a stage is disabled, internal circuitry within the stage (not shown in FIG. 11) provides a bypass path such that the signal at the input of the stage is provide to the output of the stage.

[0159] As shown in FIG. 11, within ΣΔ ADC 1120, the input signal is provided to buffer 1124 that buffers the signal. The buffered signal comprises the ΣΔ modulator input signal that is provided to the first ΣΔ stage 1122a. ΣΔ stage 1122anoise shapes and quantizes the signal in the manner described above and provides the processed signal to the second ΣΔ stage 1122b. ΣΔ stage 1122bfurther noise shapes and quantizes the signal and generates the output data samples. The outputs from ΣΔ stages 1122aand 1122bmay be combined by a noise cancellation circuit (not shown in FIG. 11) for a multi-loop ΣΔ ADC.

[0160] Within control circuit 1110, the modulator input signal is also provided to a detector ΣΔ stage 1112 that also noise shapes and quantizes the signal to generate a detected signal. The detected signal is then provided to a conditioning circuit 1114 that conditions and quantizes the signal to generate digital samples. The signal conditioning may include, for example, signal amplification, filtering, comparison, and so on. The samples are provided to a signal processor 1116 that further processes the samples to generate a control signal. The control signal is used to selectively enable and disable ΣΔ stage 1122a, and may also be used to selectively enable and disable ΣΔ stage 1122b(as shown by the dashed line). A reference generator 1118 can be included within control circuit 1110, and is used to provide one or more reference voltages to ΣΔ stages 1122, detector ΣΔ stage 1112, and conditioning circuit 1114. The elements of control circuit 1110 are further described below.

[0161] Generally, one or more ΣΔ stages 1122 in the signal path are enabled to provide the required data conversion performance, e.g., the required signal-to-noise ratio (SNR). For a cellular application, the modulator input signal includes the desired signal (e.g., the CDMA signal) and possible undesired jammers. The jammers can be much larger than the desired signal. Since a gain control mechanism is typically used to maintain the modulator input signal at a particular signal level, to avoid clipping by the ΣΔ ADC, the desired signal can be very small relative to the ΣΔ ADC input range when large amplitude jammers are present. In this situation, higher dynamic range is required to allow for quantization of the small amplitude desired signal with the required SNR. In accordance with an aspect of the invention, jammers are detected by measuring the amplitude of the modulator input signal.

[0162] Detector ΣΔ stage 1112 processes the modulator input signal in similar manner as one of ΣΔ stages 1122 in ΣΔ ADC 1120 and provides the detected signal that is indicative of the amplitude of the modulator input signal. In an embodiment, for a cellular application, if the amplitude of the modulator input signal is determined to be less than a particular signal level, one of ΣΔ stages 1122 can be disabled since jammers are not present (or are at low signal levels) and high dynamic range is not required. Alternatively, if the amplitude of the modulator input signal is determined to be greater than the particular signal level, one or more large amplitude jammers are presumed to be present in the input signal. Both ΣΔ stages 1122 are then enabled to provide high dynamic range such that the required SNR is maintained. Specifically, the high dynamic range allows ΣΔ ADC 1120 to quantize the desired signal with the required SNR even in the presence of large amplitude jammers.

[0163] As noted above, each ΣΔ stage 1122 can be a loop of a multi-loop ΣΔ ADC or a filter section of a multi-section ΣΔ ADC. The ΣΔ stages can be implemented with different orders (e.g., a fourth order in cascade with a second order). In a specific embodiment, each ΣΔ stage 1122 is a second order lowpass modulator for a baseband ΣΔ ADC and a fourth order bandpass modulator for a bandpass ΣΔ ADC. When the ΣΔ stages are the same order, the second ΣΔ stage 1122bcan be implemented as a “shrunken” replica of the first ΣΔ stage 1122a, as described above. The first ΣΔ stage 1122acan be designed with larger-sized components (e.g., switches, capacitors, and so on) and biased with greater current to provide enhanced noise performance, when enabled. The second ΣΔ stage 1122bcan be designed with smaller-sized components and biased with less current since high dynamic range is not required when the input signal amplitude is larger.

[0164] Detector ΣΔ stage 1112 can be implemented as a “shrunken” replica of the second ΣΔ stage 1122b, and can be designed with even smaller-sized components and biased with even less current. Detector ΣΔ stage 1112 is used to measure signal amplitude, and high dynamic range or high SNR is typically not required.

[0165] FIG. 12 shows a simplified block diagram of a specific embodiment of a control circuit 1210 for controlling a multi-stage circuit 1220. Multi-stage circuit 1220 can be a multi-loop ΣΔ ADC, a multi-section ΣΔ ADC, or other circuits having multiple stages that can be selectively enabled and disabled (and possibly bypassed). An example of such multi-stage circuit is an amplifier having a set of cascaded amplification stages.

[0166] As shown in FIG. 12, within multi-stage circuit 1220, the input signal is provided to a buffer (BUF) 1224 that buffers the signal. The buffered signal is provided to a high performance stage 1222athat is enabled when high performance (e.g., high dynamic range) is required. The output from stage 1222ais provided to a medium performance stage 1222bthat is enabled when medium performance (e.g., medium dynamic range) is required. The signal from stage 1222bis provided to a low performance stage 1222cthat provides a low level of performance (e.g., low dynamic range). In an embodiment, only stage 1222cis enabled when low dynamic range is required, stages 1222band 1222care enabled when medium dynamic range is required, and all three stages 1222athrough 1222care enabled when high dynamic range is required. Stages 1222aand 1222binclude MUXes 1226aand 12226b, respectively. Each MUX 1226 selects either the processed signal or the bypassed signal and provides the selected signal to the output of the stage. The bypassed signal is selected when the stage is disabled.

[0167] Each stage 1222 can be implemented independently from other stages. For example, for a ΣΔ ADC, each stage 1222 can have a different order. In a specific embodiment, each stage 1222 is a second order lowpass modulator for a baseband HA ADC and a fourth order bandpass modulator for a bandpass ΣΔ ADC. In this embodiment, stage 1222bcan be implemented as a shrunken replica of stage 1222a, and stage 1222ccan be implemented as a shrunken replica of stage 1222b.

[0168] As shown in FIG. 12, within control circuit 1210, the buffered signal is provided to two detection paths. In the first detection path, a low performance detector stage 1212aprocesses the buffered signal and provides a first detected signal to a conditioning circuit/signal processor 1214a. Circuit/processor 1214aconditions, quantizes, and further processes the detected signal to generate a first control signal that is used to selectively enable and disable high performance stage 1222aand medium performance stage 1222b. In the second detection path, a medium performance detector stage 1212bprocesses the buffered signal and provides the processed signal to a low performance detector stage 1212c. Detector stage 1212cfurther processes the signal and provides a second detected signal to a conditioning circuit/signal processor 1214b. Circuit/processor 1214bconditions, quantizes, and further processes the detected signal to generate a second control signal that is used to selectively enable and disable high performance stage 1222a.

[0169] In an embodiment, each of low performance detector stages 1212aand 1212cis implemented as a replica of low performance stage 1222c, and medium performance detector stages 1212bis implemented as a replica of medium performance stage 1222b. The replicas can be implemented using smaller-sized components and can also be operated using less bias current.

[0170] In the embodiment shown in FIG. 12, the stage(s) to be disabled are controlled by a control signal from a detection path that includes the replica(s) of the stage(s) that are enabled. For example, high performance stage 1222aand medium performance stage 1222bare controlled by the first control signal from the detection path that includes a replica of low performance stage 1222c. Similarly, high performance stage 1222ais controlled by the second control signal from the detection path that includes the replicas of the low and medium performance stages 1222aand 1222b. In an embodiment, the detector stage(s) in each detection path measure the amplitude of the buffered signal.

[0171] In an embodiment, the stages in the signal path are enabled based on the detected signal amplitude (e.g., to provide higher dynamic range when the signal amplitude is large). For example, stages 1222athrough 1222ccan be enabled if the input signal amplitude is greater than a first signal level, stages 1222band 1222ccan be enabled if the input signal amplitude is between the first signal level and a second signal level, and stage 1222ccan be enabled if the input signal amplitude is less than the second signal level. The stages can also be enabled based on other detected signal characteristics, and can also be enabled in different order and configurations.

[0172] FIG. 13 shows a simplified block diagram of a specific embodiment of a control circuit 1310 for controlling a multi-stage circuit 1320. Similar to multi-stage circuit 1220, multi-stage circuit 1320 can be a multi-loop ΣΔ ADC, a multi-section ΣΔ ADC, or other circuits having multiple stages that can be selectively enabled and disabled (and possibly bypassed). Each stage (possibly with the exception of the last stage 1322n) includes a MUX 1326 that selects either the processed signal or the bypassed signal and provides the selected signal to the output of the stage. The bypassed signal is selected when the stage is disabled.

[0173] As shown in FIG. 13, multi-stage circuit 1320 includes a number of stages 1322athrough 1322nand a buffer (BUF) 1324. The input signal is provided to buffer 1324 that buffers the signal and provides the buffered signal to the first stage 1322a. Each stage 1322 processes the signal and provides the processed signal to a subsequent stage. The output from the n-th stage 1322n comprises the output from circuit 1320.

[0174] In an embodiment, each stage (again, possibly with the exception of the last stage 1322n) can be selectively enabled and disabled. A sufficient number of stages is enabled to provide the required performance (e.g., the required dynamic range or the required SNR), and remaining stages are disabled to conserve power. In a specific embodiment, the highest dynamic range is provided when all stages are enabled, the next highest dynamic range is provided when all but one stage (e.g., first stage 1322a) are enabled, and the lowest dynamic range is provided when only one stage (e.g., n-th stage 1332n) is enabled. In a specific embodiment, the stages are disabled in accordance with their relative location in the circuit. As an example, the first stage 1322ais disabled first, the second stage 1322bis disabled next, and the (n−1)-th stage is disabled last. In an embodiment, the n-th stage 1322nis enabled at all times, or whenever circuit 1320 is turned on. In other embodiments, the stages can be enabled in different configurations and disabled in different orders, and this is within the scope of the invention. For example, the first stage (instead of the last stage) can be enabled at all times.

[0175] Within control circuit 1310, the buffered signal is provided to a set of one or more detector stages 1312. Detector stage(s) 1312 process the buffered signal and provide a detected signal to a conditioning circuit 1314 that conditions and quantizes the signal to generate digital samples. The samples are provided to a signal processor 1316 that processes the samples and generates a set of control signals. The control signals are used to selectively enable and disable the stages of multi-stage circuit 1320. A reference generator 1318 can also be included within control circuit 1310 to provide one or more reference voltages to stages 1322, detector stage(s) 1312, and conditioning circuit 1314.

[0176] In an embodiment, each of detector stage(s) 1312 in the detector path is implemented as a replica of a stage 1322 in the signal path. Again, the replica(s) can be shrunken to reduce die area and can also be operated with less bias current to conserve power.

[0177] FIG. 14 shows a simplified block diagram of a specific embodiment of a control circuit 1410 that can be used as the control circuits in FIGS. 11 through 13. Control circuit 1410 includes detector stage(s) 1412, a conditioning circuit 1414, and a signal processor 1416 coupled in series. Detector stage(s) 1412 receive and process the input signal (e.g., the modulator input signal from buffer 1124 in FIG. 1). Signal processor 1416 provides the control signal that is used to enable/disable one or more stages of a multi-stage circuit. A reference generator 1418 couples to detector stage(s) 1412 and conditioning circuit 1414 and provides the necessary reference signals to these circuit elements.

[0178] For clarity, control circuit 1410 will now be described for used in conjunction with the specific two-stage ΣΔ ADC design shown in FIG. 11. In a specific embodiment, ΣΔ ADC 1120 is an eight order bandpass MASH 4—4 ADC, and each ΣΔ stage 1122 comprises a fourth order bandpass modulator. As noted above, ΣΔ stage 1122bprovides a particular dynamic range and noise performance, and ΣΔ stage 1122aprovides additional dynamic range and enhanced noise performance when enabled. The enhanced noise performance of ΣΔ stage 1122acan be provided with larger-sized components and greater bias current.

[0179] In an embodiment, detector stage 1412 is a “shrunken” replica of one of the ΣΔ stages (i.e., ΣΔ stage 1122aor 1122b), and is also a fourth order bandpass modulator. For example, the components of detector stage 1412 can be implemented at one tenth of the size of the components in ΣΔ stage 1122a. In another embodiment, detector stage 1412 is a lower order (e.g., second order) modulator, which may be adequate for detecting the input signal amplitude while utilizing less complex circuitry. Detector stage 1412 noise shapes and quantizes the input signal in similar manner as the ΣΔ stage it replicates. The differential output, Op and On, from detector stage 1412 is provided to conditioning circuit 1414.

[0180] Generally, a ΣΔ modulator's analog output amplitudes are indicative of its input signal level. For some designs, the ΣΔ modulator has tendency to become unstable as the input signal amplitude exceeds the reference voltage. In fact, it can be shown that the ΣΔ modulator's analog output amplitudes grow significantly as the input signal amplitude exceeds the reference voltage (i.e., the peak-to-peak signal amplitude exceeds the difference between the high and low reference voltages). When the ΣΔ modulator becomes unstable, the standard deviation of its analog output signal is much larger than that of the ΣΔ modulator when it is stable. In accordance with an aspect of the invention, these characteristics are used detect the amplitude of the modulator input signal.

[0181] FIG. 15A shows a graph of the standard deviation of the detected signal from detector stage 1412 versus input signal amplitude. FIG. 15A includes a set of plots for various input signal frequencies. In FIG. 15A, the standard deviation on the vertical axis and the input signal amplitude on the horizontal 35 axis are normalized to the detector reference voltage (i.e., V_DECPand V_DECNin FIG. 14). When the frequency of the input signal (e.g., 0.58 MHz) is within the bandwidth of the ΣΔ modulator (e.g., 0.70 MHz), as exemplified by a plot 1510a, the standard deviation of the detected signal increases sharply as the input signal amplitude approaches a normalized value of 1.0. A normalized value of 1.0 corresponds to the point where the peak-to-peak amplitude of the input signal equals the difference between V_DECPand V_DECN. It can be seen that the standard deviation increases from less than 1.0 to greater than 20 (a twenty-plus fold increase) when the input signal amplitude increases from 0.9 to 1.0 (an eleven-plus percent increase).

[0182] However, when the frequency of the input signal (e.g., 15.4 MHz) greatly exceeds the bandwidth of the ΣΔ modulator (e.g., 0.70 MHz), as exemplified by a plot 1510k, the standard deviation of the detected signal increases slowly as the amplitude of the input signal increases past a normalized value of 1.5. The plots 15athrough 15kin FIG. 15A indicate that higher frequency components are filtered by the ΣΔ modulator. The lowpass characteristic of the ΣΔ modulator reduces the impact due to high frequency components.

[0183] In the embodiment shown in FIG. 14, conditioning circuit 1414 includes a comparator 1438 that compares the detected signal from the detector stage against a comparison signal (or a voltage) and provides the comparison result to signal processor 1416. Within conditioning circuit 1414, the outputs, Op and On, from detector stage(s) 1412 are provided to one end of switches 1432band 1432c, respectively. Comparison voltages, V_COMPPand V_COMPN, are provided to one end of switches 1432aand 1432d, respectively. The other ends of switches 1432aand 1432bcouple together and to one end of a capacitor 1434a, and the other ends of switches 1432cand 1432dcouple together and to one end of a capacitor 1434b. The other end of capacitor 1434acouples to one end of a switch 1436aand to a non-inverting input of comparator 1438. Similarly, the other end of capacitor 1434bcouples to one end of a switch 1436band to an inverting input of comparator 1438. The other ends of switches 1436aand 1436bcouple to an input common-mode voltage V_ICM, which is the mid-scale or common-mode voltage of the detector outputs, Op and On. Switches 1432b, 1432c, 1436a, and 1436bare controlled by a clock signal having a first clock phase ø1, and switches 1432aand 1432dare controlled by a clock signal having a second clock phase ø2.

[0184] During the first clock phase 41, switches 1432b, 1432c, 1436a, and 1436bare closed and the outputs Op and On from detector stage 1412 charge capacitors 1434aand 1434b, respectively. During the second clock phase 42, switches 1432aand 1432dare closed and the voltage captured on capacitors 1434aand 1434bare respectively compared against the high and low comparison voltages, V_COMPPand V_COMPN, by comparator 1438. Capacitors 1434aand 1434bthus respectively sample the detector outputs, Op and On, during the first clock phase ø1, and respectively sample the comparison voltages, V_COMPPand V_COMPN, during the second clock phase 02. Comparator 1438 generates a one (i.e., logic high) when the detector output exceeds the comparison voltage and a zero (i.e., logic low) otherwise.

[0185] FIG. 14 shows a specific embodiment of conditioning circuit 1414. Other conditioning circuits can be designed and are within the scope of the invention.

[0186] FIG. 15B shows a graph of the distribution densities of the signal levels of the detected signal. FIG. 15B includes plots 1520aand 1520bfor two input signal amplitudes, A1 and A2, respectively. The detected signal has a density shown by plot 1520awhen the input signal has an amplitude of A1, and a density shown by plot 1520bwhen the input signal has an amplitude of A2, where A2 is greater than A1. As shown in FIG. 15B, the density distributions are approximately Gaussian, and the standard deviation of the Gaussian distribution increases with larger input signal amplitude. When the detected signal exceeds the comparison voltage V_COMP, as indicated by shaded areas 1524aand 1524b, the conditioning circuit outputs a one. The comparison voltage thus affects the percentage of ones and zeros from conditioning circuit 1414. By decreasing the comparison voltage, the percentage of ones increases, and a faster control mechanism may be obtained. Alternatively, by increasing the comparison voltage, a more accurate detection may be obtained, which may reduce the likelihood of false detection. The distribution bi-nodal when the ΣΔ modulator oscillates.

[0187] In an embodiment, signal processor 1416 receives the digital samples from comparator 1438 and counts the number of ones within a particular time period. As shown in FIG. 15A, the comparison voltage V_COMPcan be expressed on the vertical axis. The number of ones (i.e., the number of times a particular plot exceeds V_COMP) is small when the standard deviation of the detected signal is below the comparison voltage V_COMPand is large when the standard deviation of the detected signal exceeds the comparison voltage V_COMP.

[0188] FIG. 15C shows a graph of the count value from signal processor 1416 versus detector input signal amplitude. FIG. 15C includes a set of plots 1530athrough 1530kfor various comparison voltages V_COMP. As noted above, the digital samples from conditioning circuit 1414 are provided to signal processor 1416 that counts the number of ones within a particular time period. The number of ones increases noticeably as the input signal amplitude increases from a normalized value of 0.9 to 1.0. The comparison voltage V_COMP, effects the count value when the input signal amplitude is between the normalized values of 0.9 and 1.0 but has less impact when the input signal amplitude exceeds the normalized value 1.0. When the comparison voltage is low, as indicated by plot 1530a, the count value saturates when the input signal amplitude reaches the normalized value of 0.95. However, when the comparison voltage is higher, as indicated by plot 1530k, the count value does not saturate until the input signal amplitude reaches the normalized value of 1.0. When the input signal amplitude exceeds a normalized value of approximately 1.0, the count value saturates at a particular count value.

[0189] In an embodiment, signal processor 1416 compares the count value with a count threshold. If the count value exceeds the count threshold (e.g., 6000 in a specific implementation), the input signal amplitude is deemed to be greater than a particular percentage (e.g., 95%) of the detector reference voltage V_DEC, and the control signal is configured to enable one or more additional ΣΔ stages in the ΣΔ ADC.

[0190] Signal processor 1416 can be implemented with an accumulator that counts the number of ones from comparator 1438 and is reset at the start of each counting interval. The accumulator value at the end of the counting interval is compared against the count threshold. If the accumulator value exceeds the count threshold, the detector stage is presumed to be in oscillation and the amplitude A_Vinof the detector input signal is deemed to have exceeded a particular percentage of the detector reference voltage V_DEC(e.g., A_Vin>0.95 V_DEC)

[0191] The counting interval can be adjusted based on system requirements. Generally, a longer counter interval provides increased accuracy. However, a shorter counting interval can provide a faster response time.

[0192] In an embodiment, the ΣΔ stages are enabled and disabled based on the detected input signal amplitude. If the detected input signal amplitude exceeds an particular signal level, high dynamic range is required and additional 2, stage(s) are enabled. Alternatively, if the detected input signal amplitude is below the particular signal level, high dynamic range is not required and zero or more ΣΔ stages can be disabled.

[0193] In an embodiment, the input signal amplitude is determined by adjusting the detector reference voltage V_DECand monitoring the count value. As the detector reference voltage is adjusted, if the count value noticeably changes in value, the input signal amplitude is determined as a percentage (e.g., 95%) of the detector reference voltage V_DEC. Alternatively, as the detector reference voltage is adjusted, if the count value exceeds a particular amount (e.g., 6000), the input signal amplitude is determined to be greater than a particular percentage (e.g., 95%) of the detector reference voltage V_DEC.

[0194] In some applications, it is not necessary to determine the input signal amplitude with a great deal of precision. Rather, it is only necessary to determine whether the input signal amplitude exceeds particular signal levels. The signal levels can correspond to, for example, the levels at which the stages in the multi-stage circuit are to be enabled/disabled. For example, for a three-stage circuit, the detector stage can be designed with two detector reference voltages (e.g., a high and a low detector reference voltage). If the count value is high for the high detector reference voltage, the input signal has a large amplitude and all three stages may be enabled to provide the required performance. If the count value is low for the low detector reference voltage, the input signal has a small amplitude and one stage may be adequate to provide the required performance. The remaining stages may then be disabled to conserve power. And if the count value is low for the high detector reference voltage but high for the low detector reference voltage, the input signal has a medium amplitude and two stages may be enabled. The high and low detector reference voltages can be selected to correspond to signal levels at which the stages are enabled/disabled.

[0195] In another embodiment, the input signal amplitude can be determined by adjusting the gain of the detector stage. The detector stage can be designed with multiple gain settings. The gain settings can correspond to, for example, the levels at which the stages in the multi-stage circuit are to be enabled/disabled. For example, for a three-stage circuit, the detector stage can be designed with two gain settings (e.g., a high and a low gain setting). If the count value is high at the low gain setting, the input signal has a large amplitude and all three stages may be enabled to provide the required performance. If the count value is low at the high gain setting, the input signal has a small amplitude and one stage may be adequate to provide the required performance. And if the count value is low at the low gain setting but high at the high gain setting, the input signal has a medium amplitude and two stages may be required. The high and low gain settings can thus be selected to correspond to signal levels at which the stages are enabled/disabled.

[0196] For clarity, the invention has been described for a particular (e.g., cellular) application in which the input signal may include large amplitude jammers. The control mechanism described above presumes that large amplitude jammers are present when the input signal amplitude is high, and additional ΣΔ stage(s) are enabled to provide increased dynamic range. For other applications, large spurious signals may not be present in the input signal and the reverse could be true. That is, the ΣΔ stages can be disabled as the input signal amplitude increases. The large signal amplitude could indicate a desired signal having a higher SNR and requiring less dynamic range. Thus, the control mechanism is designed based, to an extent, on the characterization of the input signal.

[0197] Also for clarity, the invention has been mainly described for a specific application to ΣΔ ADC. However, the invention can be adopted for use with many other multi-stage circuits. Generally, the multi-stage circuit includes a number of signal stages, some of which can be selectively enabled and disabled. In an embodiment, the control circuit includes one or more detector stages, with each detector stage being a replica of one of the signal stages. The detector stage(s) are used to measure a particular signal characteristic (e.g., signal amplitude). The measured signal characteristic is then used to control the signal stages. The multi-stage circuit can be, for example: (1) an amplifier having multiple gain stages, (2) a power amplifier having multiple output drivers (e.g., coupled in parallel), (3) an active filter having multiple filter sections, and other circuits. The signal stages can be coupled in series or in parallel, or a combination thereof. The detector stages are typically coupled in a similar configuration as the signal stages.

[0198] The control mechanism described above provides many advantages. The detector stage receives the same input signal that is provided to the multi-stage circuit. Extra circuitry is not required to generate a signal especially for the control mechanism. In addition, the control mechanism described above is particularly advantageous when used for controlling a ΣΔ ADC. These additional benefits are described below.

[0199] First, the detector stage models the signal stage that is enabled and provides a measurement that more accurately indicates the actual amplitude of the input signal. As note above, the ΣΔ modulator filters the input signal such that higher frequency components (i.e., relative to the center frequency) are attenuated more than lower frequency components. Since the detector stage is implemented as a replica of one of the stages, the input signal is attenuated by the detector stage in a similar manner (i.e., with a similar frequency response). The detector stage thus provides a detected signal having spectral components approximately matching that of the stage in the signal path.

[0200] The detector stage is particularly accurate in measuring jammers in a cellular application. High frequency jammers are attenuated by the detector stage in similar manner as the enabled stage(s) in the signal path. Thus, even though the amplitude of the jammer may be high, the detected signal could be small if the jammer frequency is sufficiently high. In this case, a low dynamic range setting may be adequate since the jammers are similarly filtered by the stage in the signal path. In contrast, a detector employing a flat frequency response may falsely declare a high input signal amplitude for large out-of-band jammers and erroneously turn on additional signal stages that may not be required.

[0201] Second, in some embodiment, the detector stage is a “shrunken” replica of the stage in the signal path. Thus, the detector stage can be implemented with components (e.g., switches and capacitor) having dimensions that are a fraction of those of the stage in the signal path. For example, the scaling for the detector stage can be a tenth of the size of the stage being replicated.

[0202] Third, the detector stage can be operated at a fraction of the bias current of the stage its replicates. The detector stage is generally used to detect signal amplitude, and high dynamic range or high SNR is typically not required. The bias current for the detector stage can thus be substantially reduced.

[0203] Fourth, the detector reference voltage V_DECcan be adjusted (e.g., in small and accurate increments) to allow for accurate determination of the input signal amplitude, if necessary or desired. Accurate detector reference voltages can be readily generated using, for example, a bandgap reference and a DAC in a manner known in the art.

[0204] Fifth, the comparator in the conditioning circuit can be designed to detect large signal amplitudes from the detector stage rather than the small amplitude of the input signal. The detected signal from the detector stage typically has several hundreds of millivolts of peak-to-peak swing when the detector is driven unstable. The comparator reference voltage V_COMPcan thus be set at a much higher level (e.g., one half volt differential) rather than the small (e.g., 30 mV) differential level of the input signal being measured. The large comparator reference voltage enables a control circuit design that is more tolerant to offset in the detector stage and the reference generator.

[0205] Sixth, for a bandpass ΣΔ ADC, the detector stage also downconverts the IF input signal to baseband or other low output frequencies. Thus, the subsequent circuitry (e.g., the switches within the conditioning circuit) can be implemented with smaller sizes.

[0206] The foregoing description of the preferred embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the inventive faculty. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.