Method of controlling junction recesses in a semiconductor device

[0002] 1. Field of the Invention

[0003] The present invention is generally directed to semiconductor processing, and, more particularly, to a method of controlling junction recesses in a semiconductor device.

[0004] 2. Description of the Related Art

[0005] There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, etc. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, the size of many components of a typical field effect transistor, e.g., channel length, source/drain junction depths, gate dielectric thickness, etc., are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.

[0006] Modern integrated circuit devices are comprised of millions of transistors formed above a semiconducting substrate. In order to perform their intended function, the various semiconductor devices, e.g., transistors, must be electrically coupled to one another. In most modern integrated circuit devices this is accomplished by forming a plurality of conductive interconnections, i.e., conductive lines and conductive plugs, above the substrate. Typically, these conductive lines and conductive plugs are formed in alternating layers above the substrate. Such conductive interconnections allow signals to propagate throughout the integrated circuit device thereby enabling the device to perform its intended function.

[0007] By way of background, FIG. 1 depicts an illustrative transistor 10 for purposes of explaining one or more problems that may be solved or reduced by the present invention. As shown in FIG. 1, the transistor 10 is formed in an active area 12 that is defined in the semiconducting substrate 14 by isolation structures 16 formed therein. The transistor 10 is comprised of a gate insulation layer 18, a gate electrode 20, a sidewall spacer 24, and a plurality of source/drain regions 28. The transistor 10 is also comprised of metal silicide layers 29 formed above the source/drain regions 28 and the gate electrode 20. All of the various components of the transistor 10 depicted in FIG. 1 may be formed using a variety of known processing techniques and they may be comprised of a variety of materials. For example, the gate insulation layer 18 may be comprised of a thermally grown layer of silicon dioxide, the gate electrode 20 may be comprised of polysilicon, the sidewall spacer 24 may be comprised of silicon dioxide, and the metal silicide regions 29 may be comprised of, for example, cobalt silicide or titanium silicide.

[0008] Also depicted in FIG. 1 is a conductive interconnection 11 formed above one of the source/drain regions 28 of the transistor 10. Please note that, for purposes of clarity and explanation, only one such conductive interconnection 11 is depicted in FIG. 1, although such a conductive interconnection will be applied to both of the source/drain regions 28, as well as the gate electrode 20. The conductive interconnection 11 may take a variety of forms, e.g., a strap that would extend over the isolation region 16 to connect to another source/drain region (not shown) of a separate transistor (not shown). Alternatively, the conductive interconnection 11 may extend vertically upward to additional conductive interconnections, e.g., a conductive line formed on the integrated circuit device. Moreover, the conductive interconnection 11 may take a variety of shapes or forms, e.g., straps or generally cylindrical contacts, that may have an oval or circular cross-sectional configuration when viewed from above, etc.

[0009] The isolation structure 16 is typically comprised of an insulating material, such as silicon dioxide, or other like material. The isolation structure 16 may be constructed by forming a trench in the substrate 14, filling the trench with an appropriate insulating material, e.g., silicon dioxide, and, thereafter, performing a chemical mechanical polishing operation to remove any excess material.

[0010] After the isolation structure 16 is formed, many additional processing steps must be performed to form the transistor 10. Those process steps, at times, tend to erode or consume portions of the isolation structure 16, particularly at the interface between the source/drain region 28 and the isolation structure 16, thereby resulting in the recess 25 depicted in FIG. 1. There are a vast variety of process steps that may cause erosion of the isolation structures 16. For example, the surface of the substrate 14 is frequently cleaned to remove native oxides, and the sidewall spacers 24 are formed by depositing a layer of material, e.g., silicon dioxide, and, thereafter, performing an etching process, etc. Of course, as those skilled in the art will recognize, the recess 25 depicted in FIG. 1 is only schematic in nature, i.e., any such recess may take a variety of shapes. The depth and extent of the recess 25 may also vary.

[0011] Undesirable consumption of the isolation structure may also occur when conductive interconnections, such as the conductive interconnection 11, are formed above the source/drain regions 28. In some situations, the conductive interconnection 11 would ideally be positioned entirely over the source/drain region 28, i.e., it will be located between the isolation structure 16 and the sidewall spacer 24. Such a conductive interconnection, such as a generally cylindrical conductive contact (not shown), may be formed by forming a layer of insulating material, and, thereafter, performing one or more etching processes to define an opening in the insulating layer where the conductive contact will be formed. However, in situations where the opening in the insulating layer is misaligned, i.e., where the opening extends over a portion of the isolation structure 16, the isolation structure 16 may be subjected to the etching process that is used to form the opening in the insulation layer.

[0012] As a result of all of these various process steps, portions of the isolation structure 16 may be consumed or eroded away to form the recess 25 that exposes a portion of the sidewall 27 of the source/drain region 28. This recess 25 allows the conductive interconnection 11 to be formed on the exposed surface 27 of the source/drain region 28, thereby effectively reducing the junction depth of the device in that local area. As a result, the device may exhibit increased off-state leakage currents and increased power consumption, both of which are undesirable characteristics in modern integrated circuit devices.

[0013] The present invention is directed to a method that solves or reduces some or all of the aforementioned problems.

[0014] The present invention is directed to a method of forming a transistor. In one illustrative embodiment, the method comprises providing a substrate that is doped with a first type of dopant material, forming a transistor above the substrate in an active area of the substrate as defined by an isolation structure, and performing at least one ion implantation process to implant dopant atoms in the substrate adjacent the gate electrode of the transistor. The method further comprises performing at least two angled ion implant processes on the transistor with a dopant material that is of an opposite type to the first type of dopant material and performing at least one anneal process.

[0015] The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:

[0016] FIG. 1 depicts an illustrative prior art transistor;

[0017] FIG. 2 depicts a partially formed semiconductor device wherein an ion implantation process is performed to form the source/drain extensions of the device;

[0018] FIG. 3 depicts the device of FIG. 2 after a sidewall spacer has been formed adjacent the gate electrode of the device and a source/drain implant process has been performed on the device;

[0019] FIG. 4 depicts the device shown in FIG. 3 after at least two angled ion implant processes have been performed to form implanted regions adjacent the substrate/isolation structure interface; and

[0020] FIG. 5 depicts the device of FIG. 4 after it has been subjected to one or more anneal processes to activate the implanted dopant ions and to repair the damage to the lattice structure of the silicon substrate occasioned by the various implantation processes described above.

[0021] While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

[0022] Illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

[0023] The present invention will now be described with reference to FIGS. 2-5. Although the various regions and structures of a semiconductor device are depicted in the drawings as having very precise, sharp configurations and profiles, those skilled in the art recognize that, in reality, these regions and structures are not as precise as indicated in the drawings. Additionally, the relative sizes of the various features depicted in the drawings may be exaggerated or reduced as compared to the size of those features or regions on fabricated devices. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present invention. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of technologies, e.g., NMOS, PMOS, CMOS, etc., is readily applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc.

[0024] In general, the present invention is directed to a method of controlling junction recess problems in semiconductor devices adjacent the interface between the source/drain region and the isolation structure using an angled ion implantation process. This angled ion implantation process will be performed using a doping material that is of the same type, e.g., N-type or P-type, as that of the source/drain regions for the device. That is, the angled implant process disclosed herein will be performed using a dopant material that is of a type opposite the nominal substrate doping, or well doping for CMOS devices. One illustrative process flow in which the present invention may be used is described below. As will become clear to those skilled in the art upon a complete reading of the present application, the present invention may be used in a vast variety of process flow schemes. Thus, the particular details of the process flow described herein should not be considered a limitation of the present invention unless such details are specifically set forth in the appended claims.

[0025] FIG. 2 depicts a partially formed semiconductor device 30 comprised of a gate electrode 40 and gate insulation layer 38. In general, the particular materials and techniques used to form the various components or layers of the transistor 30 depicted in FIG. 2, e.g., the gate insulation layer 38 and the gate electrode 40, are matters of design choice, and, thus, should not be considered a limitation of the present invention. For example, the gate insulation layer 38 may be comprised of silicon dioxide, and it may be formed by, for example, a thermal growth process or a deposition process. Similarly, the gate electrode 40 may be comprised of polysilicon, and it may be formed by, for example, a physical vapor deposition (“PVD”) or a chemical vapor deposition (“CVD”) process. In one illustrative embodiment, the gate electrode 40 is comprised of a layer of polysilicon having a thickness ranging from approximately 1000-3000 Å that is formed by a CVD process. The substrate 31 may be comprised of a variety of semiconducting materials, such as silicon, and it may be doped with 10 an N-type or a P-type dopant material.

[0026] One or more ion implantation processes may be performed using a dopant type that is opposite to that of the substrate to form source/drain regions for the device. For example, as indicated in FIG. 2, an ion implantation process, as indicated by arrows 51, may be performed on the device to form doped regions 51A in the semiconducting substrate 31 adjacent the gate electrode 40. This ion implantation process 51 is used to form the source/drain extensions of the completed device. This implantation process 51 is performed at a relatively low energy level and at a relatively high concentration of dopant atoms. For example, the concentration of dopant atoms in the ion implantation process 51 may vary from approximately 1×10¹⁴to 2-10¹⁵ions/cm²of the appropriate dopant atoms, e.g., arsenic (Ar) or phosphorous (P) for NMOS technology, boron (B) or boron difluoride (BF₂) for PMOS technology, etc. The energy level for the ion implantation process 51 will vary depending upon the dopant material used in the process. For example, in one illustrative embodiment for forming the source/drain extension implants in an NMOS device, the ion implantation process 51 is performed using arsenic as the dopant atoms at a concentration ranging from approximately 1×10¹⁴to 2×10¹⁵ions/cm²and at an energy level ranging from approximately 2-20 keV. For a PMOS device, a small sidewall spacer (not shown) may be formed adjacent the gate electrode 40 prior to performing the implant step 51. This spacer is used in PMOS devices due to the increased diffusivity of the dopant atoms that may be implanted, e.g., boron.

[0027] Next, as indicated in FIG. 3, a sidewall spacer 44 is formed adjacent the gate electrode 40. The sidewall spacer 44 is formed by depositing a layer of spacer material above the surface of the device and thereafter performing an anisotropic etching process to define the spacer 44. The layer of spacer material may be comprised of a variety of materials, such as silicon dioxide, silicon oxynitride, or other like materials. Moreover, it may be formed by any of a variety of techniques for forming such layers, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0028] Thereafter, as indicated in FIG. 3, an ion implantation process 55 is performed to form the doped regions 55A in the substrate adjacent the gate electrode 40. Note that the ion implantation process 55 is generally self-aligned with respect to the sidewall spacer 54. Moreover, the ion implantation process 55 is normally considered to be the source/drain implant in modern semiconductor manufacturing operations. For example, the concentration of dopant atoms in the ion implantation process 55 may vary from approximately 5×10¹⁴to 5×10¹⁵ions/cm²of the appropriate dopant atoms, e.g., arsenic or phosphorous for NMOS technology, boron for PMOS technology, etc. The energy level for the ion implantation process 55 will vary depending upon the dopant material. For example, in one illustrative embodiment for forming the source/drain regions in an NMOS device, the ion implantation process 55 is performed using arsenic as the dopant atoms at a concentration of approximately 5×10¹⁴to 5×10¹⁵ions/cm²and at an energy level ranging from approximately 40-70 keV.

[0029] Also note that the isolation structures 36 are depicted as having been eroded at this point in the process flow so as to result in a recess 45 in the isolation structure 36 adjacent what will become the source/drain region of the device. The extent and shape of the recess 45 will vary depending upon the materials of construction of the transistor 30, as well as the particular process flow used to construct the transistor 30.

[0030] Next, as shown in FIG. 4, after the formation of the sidewall spacer 44, the device is subjected to at least two angled ion implantation processes 57. The angled implant processes 57 may be performed either before or after the source/drain implant process 55. The implant processes 57 may be performed at an angle ranging from approximately 20-50 degrees with respect to a line perpendicular to the surface 33 of the substrate 31. The angled implant processes 57 may be performed using a variety of known implant tools useful for performing such operations. Moreover, the substrate 31 may be tilted at an angle with respect to a fixed source of ions in such a tool, or the source of the ions within the tool may be tilted at an angle with respect to a fixed substrate 31. The angled implant processes 57 result in the angled implant regions 57A indicated in FIG. 4. Note that, due to the erosion of the isolation structure 36, atoms implanted during the angled implant processes 57 are allowed to be implanted through the exposed sidewall 47 of the substrate 31. To the extent that there is no erosion of the isolation structure 36, the angled ion implant processes 57 are performed at such a concentration so as not to adversely impact the device performance.

[0031] When focusing on a single transistor 30, only two angled implant processes 57 need to be performed, i.e., once on each side of the transistor 30. However, as a practical matter, the device 30 may be subjected to four angled ion implant processes 57, each performed after the substrate has been rotated 90 degrees. This particular implant process flow, i.e., four implants spaced 90 degrees relative to one another, may be performed in situations, which are frequent, wherein many transistors formed above the substrate 31 are oriented 90 degrees relative to one another.

[0032] Each of the angled implant processes 57 may be performed at a concentration level ranging from approximately 5×10¹³to 1×10¹⁵ions/cm²of the appropriate dopant atoms, e.g., arsenic or phosphorous for NMOS technology, boron, boron difluoride for PMOS technology, etc. That is, the angled implant processes 57 are performed using a dopant material that is of a type opposite to the dopant material used to dope the substrate. The energy level for the angled ion implantation process 55 will vary depending upon the dopant material. For example, in one illustrative embodiment for forming the source/drain regions in an NMOS device, the ion implantation process 55 is performed using arsenic as the dopant atoms at a concentration of approximately 5×10¹³to 1×10¹⁵ions/cm²and at an energy level ranging from approximately 50-80 keV. For PMOS devices, boron difluoride may be implanted at approximately the same dopant concentration level and at an energy ranging from approximately 50-80 keV.

[0033] Next, as shown in FIG. 5, one or more thermal anneal processes is performed to activate the dopant atoms introduced into the substrate during various ion implantation processes described above, and to repair the damage to the lattice structure of the semiconducting substrate resulting from the ion implantation processes. In one embodiment, this anneal process may be at a temperature ranging from approximately 1000-1050° C. for a duration of approximately 5-20 seconds in a rapid thermal anneal chamber. Note that during this process, the previously implanted dopant atoms migrate, or move, from their original implanted position. This migration of the dopant atoms is generally isotropic in direction.

[0034] Although the various implant regions 51A, 55A and 57A are depicted in the drawings as having very precise and distinct boundaries, in practice at least portions of these regions will tend to merge together as a result of the implant processes and subsequent anneal processes performed on the device. Nevertheless, the drawings indicate these regions as being very precise and defined for purposes of explaining the present invention.

[0035] Through use of the angled implant process described herein, a doped region 57A is formed in the substrate adjacent the isolation structure 36 interface. See FIG. 5. As a result, semiconductor devices may be formed that exhibit lower leakage currents than prior art devices. This in turn will lead to devices with enhanced performance capability and the performance of integrated circuit devices comprised of such semiconductor devices.

[0036] The present invention is directed to a method of forming a transistor. In one illustrative embodiment, the method comprises providing a substrate 31 that is doped with a first type of dopant material, forming a transistor 30 above the substrate 31 in an active area 32 of the substrate 31 as defined by an isolation structure 36, and performing at least one ion implantation process 51, 55 to implant dopant atoms in the substrate 31 adjacent the gate electrode 40 of the transistor 30. The method further comprises performing at least two angled ion implant processes 57 on the transistor 30 with a dopant material that is of an opposite type to the first type of dopant material and performing at least one anneal process.

[0037] The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.