US 6,406,949 B1Grant
Thin film transistor-liquid crystal display and manufacturing method therefor
Issue Date:2002-06-18
•5 Claims
•8 Drawing Sheets
Abstract
This invention relates to a TFT-LCD and a manufacturing method therefor which etches triple layer patterns in a single process step. As a result, the number of masking processes is reduced and a high quality device is produced with less defects. The method comprises the steps of: depositing a gate metal on a substrate; forming and a gate pad a gate electrode by etching the gate metal; forming an insulating layer on both the gate metal and the gate pad; depositing an amorphous silicon layer on the insulating layer; depositing an n+ amorphous silicon layer on the amorphous silicon layer; depositing a source/drain on the n+ amorphous silicon layer; etching the amorphous silicon, the n+ amorphous silicon layer and the source/drain to form a triple layer pattern; etching the n+ amorphous silicon layer and the source/drain to form a source/drain electrode; depositing a passivation layer; etching a passivation layer to expose both a portion of the source/drain electrode and a portion of the gate pad; depositing a pixel electrode layer on the passivation layer; and etching the pixel electrode layer to form a pixel electrode.
Metadata
Assignee
- Samsung Electronics Co., Ltd.
Inventor
- Dong-Gyu Kim
Application Information
Application Number:US 08/600,132
Filing Date:1996-02-12
Priority Date:1995-02-11
Art Unit:7
Classifications
IPC:
H01L 2100H01L 2184
Field of Search:
438 30438158438159438160438161257 59349 42349 43349149349151349152
Patent Drawings (8 sheets)
Description
Background of the Invention
[0002] 1. Field of the Invention
[0003] The present invention relates to a thin film transistor-liquid crystal display (hereinafter referred to as a TFT-LCD) and a manufacturing method therefor. More particularly, this invention relates to a TFT-LCD and a manufacturing method therefor which etches multi-layer patterns in a single process step.
[0004] 2. Description of the Related Art
[0005] A conventional TFT-LCD is disclosed in Society for Information Display '94 DIGEST, page 263, the content of which is hereby expressly incorporated by reference herein in its entirety. That TFT-LCD will now be described with reference to FIGS. 1, 2A-2H, and 3A-3H.
[0006] In FIG. 1, a conventional TFT-LCD is depicted which comprises: a substrate 1, a gate electrode 2, an anodic oxidation layer 3, an insulating layer 4, an amorphous silicon layer 5, an n+ amorphous silicon layer 6, a source/drain electrode 9, a passivation layer 10, and a pixel electrode layer 13.
[0007] FIGS. 2A-2H show several cross-sectional views depicting different stages of a fabrication sequence for the conventional TFT-LCD shown in FIG. 1. FIGS. 3A-3H show cell. views of layouts corresponding to the steps illustrated in FIGS. 2A-2H, respectively. Some layers are omitted from the cell layout views of FIGS. 3A-3H for purposes of simplification. Referring to those figures, a conventional method for fabricating a TFT-LCD generally comprises the steps of:
[0008] forming a gate pad 21, a gate electrode 2, and a gate line by depositing and etching a metal layer on a substrate 1;
[0009] forming a anodic oxidation layer 3 on both the gate electrode 2 and a portion of the gate pad 21;
[0010] depositing an insulating layer 4;
[0011] depositing an amorphous silicon layer 5 on the insulating layer 4;
[0012] depositing an n+ amorphous silicon layer 6 on the amorphous silicon layer 5;
[0013] etching both the amorphous silicon layer 5 and the n+ amorphous silicon layer 6 to form an active island 56;
[0014] partially etching the insulating layer 4 on the gate pad 21;
[0015] forming both a source/drain electrode 9 and a data line by depositing and etching a metal layer;
[0016] forming a passivation layer 10 having a contact hole 12 by depositing and etching an insulating material; and
[0017] forming a pixel electrode 13 by depositing and etching a transparent conductive material.
[0018] The above-described conventional TFT-LCD has many problems.
[0019] First, it reduces production yield. In addition, the etchants used during the etching process steps cause defects in the resulting TFT-LCD.
[0020] Moreover, it is more costly because many etching processes are employed in its fabrication.
Summary of the Invention
[0021] An objective of the present invention is to provide a TFT LCD and a manufacturing method therefor which etches multi-layer patterns in a single process step. Accordingly, the present invention not only reduces the number of masking processes but also produces a high quality device with less defects.
[0022] In order to achieve this objective, a method is provided for manufacturing a TFT-LCD according to the present invention, which comprises the steps of:
[0023] depositing a gate metal on a substrate;
[0024] forming a gate electrode and a gate pad by etching the gate metal;
[0025] depositing an insulating layer;
[0026] depositing an amorphous silicon layer;
[0027] depositing an n+ amorphous silicon layer on the amorphous silicon layer.
[0028] depositing a source/drain layer on the n+ amorphous silicon layer;
[0029] etching the source/drain layer, the n+ amorphous silicon layer, and the amorphous silicon layer to form a triple layer pattern in a single process step;
[0030] etching the source/drain layer and the n+ amorphous silicon layer to form a source/drain electrode pattern;
[0031] depositing a passivation layer;
[0032] etching a passivation layer to expose both a portion of the source/drain electrode and a portion of the gate pad;
[0033] depositing a pixel electrode on the passivation layer; and
[0034] etching the pixel electrode;
[0035] A TFT-LCD according to the present invention includes: a gate electrode and a gate pad that are formed on a substrate; an insulating layer having a contact hole exposing the gate pad; an amorphous silicon layer which is formed on the insulating layer; a source/drain electrode which is formed on the amorphous silicon layer; a passivation layer, having contact holes which are formed on both the source/drain electrode and the gate pad; and a pixel electrode layer formed on the passivation layer.
Brief Description of the Drawings
[0036] The present invention will now be described more specifically with reference to the attached drawings, wherein:
[0037] FIG. 1 shows a conventional TFT-LCD;
[0038] FIGS. 2A-2H show cross sectional views depicting a fabrication sequence for producing a conventional TFT-LCD.
[0039] FIGS. 3A-3H show cell layout views depicting the steps as illustrated in FIGS. 2A-2H respectively.
[0040] FIG. 4 shows a TFT-LCD according to a preferred embodiment of the present invention;
[0041] FIGS. 5A-5G are cross sectional views showing sequential steps of a method of producing the TFT-LCD of FIG. 4; and
[0042] FIGS. 6A-6G are cell layout views of the steps as illustrated in FIGS. 5A-5G.
Description of the Preferred Embodiment
[0043] A preferred embodiment of the present invention will become apparent from a study of the following detailed description, when viewed in light of the accompanying drawings.
[0044] FIG. 4 shows a TFT-LCD according to a preferred embodiment of the present invention. A gate electrode 22 and a gate pad 21 are provided, each formed on a substrate 20. An anodic oxidation layer 23 is provided which is formed on both the gate electrode 22 and the gate pad 21. An insulating layer 24 is deposited on the anodic oxidation layer 23, and comprises a contact hole exposing the gate pad 21. An amorphous silicon layer 25 is formed on the insulating layer 24. A source/drain electrode 29 is formed on the amorphous silicon layer 25. A passivation layer 30 made of insulating material is formed on the source/drain electrode 29 and has a contact hole exposing the gate pad 21.
[0045] A manufacturing method for producing a TFT-LCD according to a preferred embodiment of the present invention is shown in FIGS. 5A-5H and 6A-6H. FIGS. 5A-5H show cross-sectional side views of the device during various fabrication stages, and FIGS. 6A-6H show corresponding cell layout views. Some layers are omitted from the cell layout views of FIGS. 6A-6H for purposes of simplification.
[0046] As shown in FIGS. 5A and 6A, a gate metal is deposited on a substrate 20. Then, the gate electrode 22 and the gate pad 21 are formed by etching the gate metal.
[0047] As shown in FIG. 5B and FIG. 6B, an anode oxidation layer 23 is formed on both the gate electrode 22 and the gate pad 21.
[0048] As shown in FIG. 5C and FIG. 6C, an insulating layer 24 is then deposited on the anode oxidation layer 23. Then an amorphous silicon layer 25 is deposited on the insulating layer 24. Then an n+ amorphous silicon layer 26 is deposited on the amorphous silicon layer 25. Then a source/drain electrode metal 29 is deposited on the n+ amorphous silicon layer 25.
[0049] As shown in FIG. 5D and FIG. 6D, the source/drain 29, the n+ amorphous silicon layer 26 and the amorphous silicon 25 are etched to form a triple layer pattern.
[0050] As shown in FIG. 5E and FIG. 6E, the-source/drain 29 and the n+ amorphous silicon layer 26 are etched to form a source/drain pattern, partially exposing amorphous silicon layer 25.
[0051] As shown in FIGS. 5F and 6F, a passivation layer 30 is deposited on the source/drain 29 and the gate pad 21. Then, the passivation layer 30 is etched, together with portions of anode oxidation layer 23 and insulating layer 24, to expose both a portion of the source/drain 29 and a portion of the gate pad 21.
[0052] At this time, when both the insulating layer 24 and the anodic oxidation layer 23 on the gate pad 21 are partially etched, portions of the insulating layer 24 and the anodic oxidation layer 23 which are on the gate electrode 22 are protected from the etchant because they are covered with the source/drain layer 29.
[0053] As shown in FIG. 5G and FIG. 6G, a pixel electrode 31 is deposited on the passivation layer 30. Then a pixel electrode pattern is etched.
[0054] As described above, this invention not only reduces steps of the masking process but also producing a high quality device with less defects.
[0055] It is understood that various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of this invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein, but rather that the claims be construed as encompassing all the features of patentable novelty that reside in the present invention, including all features that would be treated as equivalents thereof by those skilled in the art which this invention pertains.
Claims
What is claimed is:
1. A method for manufacturing a thin film transistor-liquid crystal display, comprising the steps of:
depositing a gate metal on a substrate;
forming a gate electrode by etching said gate metal;
depositing an insulating layer on said gate electrode;
depositing an amorphous silicon layer on said insulating layer;
depositing an n+ amorphous silicon layer on said amorphous silicon layer;
depositing a source/drain metal layer on said n+ amorphous silicon layer;
simultaneously etching the three layers of said source/drain metal layer, n+ amorphous silicon layer and said amorphous silicon layer until said insulating layer is exposed to form a triple layer pattern;
etching said source/drain electrode metal layer and n+amorphous silicon layer to form a separated source/drain electrode pattern and expose a portion of said amorphous silicon layer between the source and drain electrodes; and
depositing a passivation layer covering said exposed portion of said amorphous silicon layer and said exposed portion of said insulating layer.
2. A method according to claim 1, further comprising the step of forming an anode oxidation layer between said gate electrode and said insulating layer.
3. A method according to claim 1, wherein said step of etching said source/drain layer, n+ amorphous silicon layer and said amorphous silicon layer comprises a single photolithography process of concurrently etching said source/drain layer, n+ amorphous silicon layer and said amorphous silicon layer.
4. The method as defined in claim 1, further comprising the steps of:
etching said passivation layer to expose at least a portion of said source/drain electrode;
depositing a pixel electrode layer on said passivation layer; and
etching said pixel electrode layer to form a pixel electrode electrically contacted to a portion of said exposed source/drain electrode.
5. The method as defined in claim 4, further comprising the step of forming a gate pad along with said gate electrode, wherein said passivation layer is etched on said gate pad along with said insulating layer when etching said passivation layer.
Patent Citations (12)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US5045485(A) | 1991-09-01 | Tanaka et al. | Examiner |
| US5054887(A) | 1991-10-01 | Kato et al. | Examiner |
| US5166085(A) | 1992-11-01 | Wakai et al. | Examiner |
| US5366912(A) | 1994-11-01 | Kobayashi | Examiner |
| US5397719(A) | 1995-03-01 | Kim et al. | Examiner |
| US5422293(A) | 1995-06-01 | Konya | Examiner |
| US5478766(A) | 1995-12-01 | Park et al. | Examiner |
| US5483082(A) | 1996-01-01 | Takizawa et al. | Examiner |
| US5496749(A) | 1996-03-01 | Nasu et al. | Examiner |
| US5580796(A) | 1996-12-01 | Takizawa et al. | Examiner |
| US5705411(A) | 1998-01-01 | Yamanobe et al. | Examiner |
| JP6-118444 | 1994-04-01 | Examiner |