Sigma-delta modulator with improved gain accuracy

[0002] The invention relates to a sigma-delta modulator for converting an analog input signal into a digital output signal, comprising:

[0003] an input network comprising a first gain stage for providing an amplified input signal in response to the analog input signal;

[0004] means for providing a difference signal in response to a comparison of the amplified input signal with an amplified feedback signal;

[0005] means for filtering the difference signal and for providing a filtered difference signal;

[0006] means for sampling and quantizing the filtered difference signal and having an output for providing the digital output signal;

[0007] a feedback network comprising a digital-to-analog converter for converting the digital output signal to an analog feedback signal and a second gain stage for providing the amplified feedback signal in response to the analog feedback signal.

[0008] Such a sigma-delta modulator (SDM) is generally known and described in books such as: Rudy van de Plassche, “Integrated analog-to-digital and digital-to-analog converters”, Kluwer Academic Publishers, 1994, Chapter 11. Sigma-delta modulation is a technique in which an analog input signal is converted into a digital output signal having high resolution and low quantisation noise with the aid of oversampling by quantisation means having a low resolution and a high quantisation noise. The digital signal is reconverted to an analog feedback signal by means of a digital-to-analog converter having the same low resolution and is subtracted from the analog input signal in a subtracting stage. The difference between the two signals is filtered in an analog loop filter and applied to the quantisation means. The use of a sufficiently high loop gain for baseband frequencies of the analog signal achieves that in the digital output signal the quantisation noise within the baseband is low at the expense of a higher quantisation noise above this baseband. By means of digital filter techniques, however, noise above the baseband can be suppressed effectively, for example, by means of a decimating filter that converts the oversampled SDM digital output signal into a higher resolution (more bits) digital signal at the desired lower sampling rate.

[0009] FIG. 1 shows a block diagram of the SDM. The analog input signal X is amplified or buffered in an input network, the gain of which is represented by a first gain stage having a gain a. An analog feedback signal is subtracted from the input signal and the difference is filtered in a low-pass loopfilter G(f), sampled at a sampling rate f_sand quantized by a quantizer Q, which may have a 1-bit or multi-bit resolution. In a feedback network the digital output signal Y_sis reconverted to an analog feedback signal by means of a digital-to-analog converter DAC having the same resolution as the quantizer Q. The analog gain of the feedback network is represented as a second gain stage having a gain d. As will be shown hereinafter, for low frequency inputs (that is for frequencies much smaller than the sampling rate f_s) the signal gain is a/d. The quantization noise is “shaped” by the inverse of the loop-filter characteristic G(f).

[0010] For some uses, for example in instrumentation, the exact gain a/d of the SDM is important. However, due to mismatch between the gains of gain stages a and d the overall gain is not accurate and may deviate from the desired value, and the gaines may contain certain offsets, which differ from each other, so that the difference signal may have offset and distortion.

[0011] It is an object of the invention to provide an SDM with improved accuracy. To this end, the sigma-delta modulator as defined in the opening paragraph is characterized in that the sigma-delta modulator further comprises:

[0012] means for regularly interchanging the first gain stage and the second gain stage.

[0013] By regularly interchanging (“chopping”) the first and second gain stages a and d the differences and further mismatches between both gain stages are modulated on the chopping frequency. The effective value of both gain stages becomes the average value of a and d so that the gain of the SDM is exactly unity. A high frequency ripple, at the chopping frequency, is present in the difference signal but the chopping frequency may be chosen outside the frequency band of interest, so that this ripple is of no importance.

[0014] Further improvements are obtained by using fully differential circuitry, preferably by using differential transconductors in the first and second gain stages. The subtraction of the input signal and the feedback signal can then easily be effected by interconnecting the opposite differential output signals of the transconductors.

[0015] The above and other features and advantages of the invention will be apparent from the following description of exemplary embodiments of the invention with reference to the accompanying drawings, in which:

[0016] FIG. 1 is a circuit diagram of a conventional sigma-delta modulator;

[0017] FIG. 2 is a circuit diagram of a linear model of the sigma-delta modulator of FIG. 1;

[0018] FIG. 3 is a circuit diagram of a conventional sigma-delta modulator using fully differential transconductors in the input network and the feedback network;

[0019] FIG. 4 is a circuit diagram of a first embodiment of a sigma-delta modulator according to the invention;

[0020] FIG. 5 is a circuit diagram of a second embodiment of a sigma-delta modulator according to the invention; and

[0021] FIG. 6 is a circuit diagram of a part of a third embodiment of a sigma-delta modulator according to the invention.

[0022] Like reference symbols are employed in the drawings and in the description of the preferred embodiments to represent the same or very similar item or items.

[0023] FIG. 1 shows a circuit diagram of a conventional sigma-delta modulator (SDM). An analog input signal X is amplified or buffered in an input network, the gain of which is represented by a first gain stage 2 having a gain a. In a subtracter 4 an analog feedback signal is subtracted from the amplified or buffered input signal and the difference is filtered in a low-pass loopfilter 6 having a transfer characteristic G(f), is sampled by a sampler 8 at a sampling rate f_sand is quantized by a quantizer 10, which may have a 1-bit or multi-bit resolution, and is output as a digital output signal Y_s. In a feedback network the digital output signal Y_sis reconverted to an analog feedback signal by means of a digital-to-analog converter (DAC) 12 having the same resolution as the quantizer 10. The analog gain of the feedback network is represented as a second gain stage 14 having a gain d.

[0024] The SDM of FIG. 1 is usually modelled as shown in FIG. 2. The quantizer 10, which may have a 1-bit or multibit resolution, is modelled by a gain stage 16 having gain c and an additive white noise source N_s. The feedback DAC 12 can be modelled as a hold stage 18 and the gain stage 14 having a gain d. Note that the system of FIG. 2 is a mixed continuous-time/discrete-time system. Discrete-time signals are indicated by an index s, such as the digital output signal Y_sand the additive noise N_s. The sampler 8 transforms its input signal from the continuous-time to the discrete-time domain. The frequency spectrum of the sampler output signal repeats with the sampling frequency. The hold function of hold stage 18 transforms its input signal from the discrete-time to the continuous-time domain. In the frequency domain the hold function is represented by a sinc filter GH(f), which has a low-pass characteristic with notches at multiples of the sampling frequency f_s. The digital output signal Y_sof the SDM of FIG. 2 can be written as: $\begin{array}{cc}{y}_s\left(f\right)=\frac{a·\mathrm{cG}\left(f\right)}{1+\mathrm{cdG}\left(f\right)G_H\left(f\right)}X\left(f\right)+\frac{1}{1+\mathrm{cdG}\left(f\right)G_H\left(f\right)}·N_s\left(f\right)& \left(1\right)\end{array}$

[0025] For low frequencies the hold function G_H(f) has approximately unity gain, and since the loop filter G(f) is a low-pass filter so that cdG(f) >>1, equation (1) simplifies to $\begin{array}{cc}{Y}_s\left(f\right)\approx \frac{a}{d}X\left(f\right)+\frac{1}{\mathrm{dG}\left(f\right)}·N_s\left(f\right)& \left(2\right)\end{array}$

[0026] For low frequency inputs, that is for frequencies much smaller than the sample rate f_s, the signal gain is. $\frac{a}{d}.$

[0027] The noise is “shaped” by the inverse of the loop filter characteristic G(f).

[0028] For some uses, for example in instrumentation, the exact gain $\frac{a}{d}$

[0029] of the SDM is important. In order to obtain optimum matching of the gains a and d on an actual silicon implementation, it is wise to choose a as an integral multiple of d, or the other way around.

[0030] FIG. 3 shows an implementation where the first gain stage 2 and the second gain stage 14 are implemented by a fully differential input transconductor 20 and a fully differential feedback transconductor 22 having an equal transconductance G_m, so that the signal gain of the SDM is unity. The transconductor 20 has a positive input terminal 36 and a negative input terminal 38, a positive output terminal 24 and a negative output terminal 26, and the transconductor 22 has a positive input terminal 40, a negative input terminal 42, a positive output terminal 28 and a negative output terminal 30. The subtraction of the analog input signal and the feedback signal can now easily be effected by interconnecting, in a first node 32, the positive output terminal 24 of the input transconductor 20 to the negative output terminal 30 of the feedback transconductor 22, and by interconnecting, in a second node 34, the negative output terminal 26 of the input transconductor 20 to the positive output terminal 28 of the feedback transconductor 22. The resulting difference current flowing through the first and second nodes 32 and 34 forms the input current of the loop filter 6:

[0031] I_in,ftr=G_m(V_in-V_DAC)  (3)

[0032] wherein V_inis the differential analog input signal at the differential input terminals 36 and 38 of the input transconductor 20 and V_DACis the differential feedback signal at the differential input terminals 40 and 42 of the feedback transconductor 22.

[0033] Due to a mismatch of the transconductors 20 and 22 the gain may deviate from unity. They may further contain certain offsets, which differ from each other, so that the difference current I_in,ftrhas offset and even harmonic distortion. Furthermore, asymmetry between the transconductors 20 and 22 is introduced if the input transconductor 20 has a single ended input signal (with the other input terminal connected to a reference voltage), whereas the feedback transconductor 22 is used differentially. This also creates offset and even harmonic distortion.

[0034] FIG. 4 shows the same SDM configuration of FIG. 3, but extended with a switching circuit 44. The switching circuit 44 has a positive input terminal 46 and a negative input terminal 48 for receiving the differential input voltage V_in, and output terminals 50 and 52 connected to, respectively, the positive input terminal 36 and the negative input terminal 38 of the input transconductor 20. The switching circuit 44 further has a positive input terminal 54 and a negative input terminal 56 for receiving the differential feedback voltage V_DAC, and output terminals 58 and 60 connected to, respectively, the positive input terminal 40 and the negative input terminal 42 of the feedback transconductor 22.

[0035] By regularly interchanging (“chopping”) the transconductors 20 and 22 by means of the switching circuit or chopper 44, the differences between both transconductors are modulated on the chopping frequency. The effective value of the transconductance of both transconductors becomes the average value G_m,aand G_m,b, so that the gain of the SDM is exactly unity. A high frequency ripple (at the chopping frequency) is present in the difference current I_in,ftr, but the chopping frequency may be chosen outside the frequency band of interest, so that this ripple is of no importance. Because a subtraction has to be performed the output terminals of the transconductors 20 and 22 are crosscoupled in the same manner as shown in FIG. 3.

[0036] In order to preserve the correct phase of the difference current I_in,ftr, the chopping has to be performed in the following way:

[0037] During the first half of the chopping clock period, the positive input terminal 46 is connected to output terminal 50, the negative input terminal 48 to the output terminal 52, the positive input terminal 54 to the output terminal 58 and the negative input terminal 56 to the output terminal 60.

[0038] During the second half of the chopping clock period, the positive input terminal 46 is connected to the output terminal 60, negative input terminal 48 to the output terminal 58, the positive input terminal 54 to the output terminal 52 and the negative input terminal 56 to the output terminal 50.

[0039] In order to reduce offsets, and even harmonic distortion and flicker noise, the chopping process can be extended by adding a second chopper 62 between the nodes 32 and 34 and the input terminals 64 and 66 of the loop filter 6. This is shown in FIG. 5. The second chopper 62 interchanges the subtracted output signals of the transconductors 20 and 22. In order to preserve the correct phase of the difference current I_in,ftr, the chopping has to be performed in the following way in this case:

[0040] During the first half of the chopping clock period, the positive input terminal 46 is connected to the output terminal 50, the negative input terminal 48 to the output terminal 52, the positive input terminal 54 to the output terminal 58 and the negative input terminal 56 to the output terminal 60. Furthermore, by means of the second chopper 62, the first node 32 is connected to the input terminal 64 and the second node 34 is connected to the input terminal 66.

[0041] During the second half of the chopping clock period, the positive input terminal 46 is connected to the output terminal 58, the negative input terminal 48 to the output terminal 60, the positive input terminal 54 to the output terminal 50 and the negative input terminal 56 to the output terminal 52. Furthermore, by means of the second chopper 62, the first node 32 is connected to the input terminal 66 and the second node 34 is connected to the input terminal 64.

[0042] By adding one or more further transconductors having the same transconductance G_mwith parallel to the feedback transconductor 22 an overall gain other than unity can be obtained. FIG. 6 shows an example in which a second feedback transconductor 68 is added. The corresponding output terminals of the transconductors 22 and 68 are interconnected, thus providing a total transconductance 2G_min the feedback network. Both transconductors 22 and 68 receive the differential feedback voltage V_DACfrom the DAC 12. The switching circuit 44 is extended with a further set of positive and negative input terminals connected to the differential feedback voltage V_DACand with a further set of output terminals connected to the input terminals of the second feedback transconductor 68. The chopping period is now divided in three periods in which the three transconductors 20, 22 and 68 are cyclically interchanged. Alternatively it is possible to add one or more transconductors in parallel with the input transconductor 20.