Method for in-situ fabrication of a landing via and a strip contact in an embedded memory

[0002] The present invention relates to a method for integrating the process of manufacturing an embedded memory and the process of manufacturing a landing via and a strip contact in the embedded memory, and more particularly, to a method for decreasing the occupied space of a strip contact in a memory device.

[0003] Due to continued improvement in process integration, it is the present trend of the semiconductor industry to fabricate semiconductor integrated circuits that integrate both a memory cell array and high-speed logic circuit elements onto a single chip to form an embedded memory. The embedded memory simultaneously combines the memory arrays and logic circuits to greatly reduce the circuit area and to increase signal processing speed. To avoid short-circuiting of various devices in the embedded memory, after the formation of MOS transistors an insulation layer is formed and covers the surface of the semiconductor wafer. Then, a photo-etching-process (PEP) is used to form a plurality of contact holes. A conductive layer is filled into the contact holes to allow for electrical connection of each metal-oxide-semiconductor (MOS) transistor with the circuit.

[0004] Please refer to FIG. 1 to FIG. 11. FIG. 1 to FIG. 11 are cross-sectional diagrams of a prior art method for manufacturing a metal-oxide-semiconductor (MOS) transistor of an embedded memory on a semiconductor wafer 10. As shown in FIG. 1, the surface of the silicon substrate 12 is divided into a memory array area 14 and a periphery circuit region 16. The memory array area 14 contains a cell well 18, and the periphery circuit region 16 contains at least one N-well 20 and at least one P-well 22. Each region is separated by several shallow trench isolation structures 23.

[0005] The prior art method first involves forming a gate oxide layer 21, a polysilicon layer 24, a polycide layer 26 and a cap layer 28 composed of silicon nitride, respectively, on the surface of the semiconductor wafer 10. Then, as shown in FIG. 2, a photoresist layer 30 is formed above the cap layer 28 followed by the use of a lithographic process to simultaneously define gate patterns of the memory array area 14 and the periphery circuit region 16 in the photoresist layer 30. Thereafter, the patterned photoresist layer 30 is used as a mask layer to perform an etching process for removing the cap layer 28, the polycide layer 26 and the polysilicon layer 24 down to the surface of the gate oxide layer 21 so as to simultaneously form a plurality of gates 32 above the cell well 18 of the memory array area 14 and a plurality of gates 34 above both the N-well 20 and the P-well 22 of the periphery circuit region 16.

[0006] As shown in FIG. 3, the photoresist layer 30 above the cap layer 28 is completely removed followed by performing an ion implantation process to form a doped region (not shown) on the surface of the silicon substrate 12 adjacent to the gates 32, 34. Thereafter, a rapid thermal process (RTP) is performed to drive dopants in the doped region into the silicon substrate 12 so as to form lightly doped drains (LDD) 36 of each MOS transistor.

[0007] As shown in FIG. 4, a silicon nitride layer (not shown) is deposited on the semiconductor wafer 10 followed by the use of an an-isotropic etching process to etch back portions of the silicon nitride layer to form a spacer 38 around each gate 32, 34 of the memory array area 14 and the periphery circuit region 16, respectively. Then, an ion implantation process is performed to form a source and drain of each MOS transistor in the periphery circuit region 16. A photoresist layer (not shown) is first formed to cover the memory array area 14 and gates 32, 34 of the N-well 20. Then, N-type dopants are used to implant the surface of the P-well 22 so as to form a doped region 42, followed by the removal of the photoresist layer. Next, another photoresist layer (not shown) is formed to completely cover the memory array area 14 and the gate 34 of the P-well 22. Then, P-type dopants are used to implant the N-well 20 of the periphery circuit region 16 so as to form a doped region 40. Thereafter, a rapid thermal process is used to drive dopants of each doped region 40, 42 into the silicon substrate 12 so as to form the source and the drain of each MOS transistor in the periphery circuit region 16.

[0008] As shown in FIG. 5, a salicide block (SAB) layer 44 is formed on the silicon substrate 12 of the memory array area 14. Then, a self-aligned silicide process is performed in the periphery circuit region 16 for forming a salicide layer 46 on the surface of each source and drain so as to finish the process of manufacturing a MOS transistor of an embedded memory according to the prior art.

[0009] After the formation of the MOS transistor of an embedded memory, a landing via and a local interconnection of the embedded memory are formed on the semiconductor wafer 10. As shown in FIG. 6, a dielectric layer 48, such as a silicon oxide layer, is first formed on the surface of the semiconductor wafer 10. A photolithographic process is then used to define a landing via hole 50 and contact holes 51a,51bin the dielectric layer 48, as shown in FIG. 7. The contact hole 51aconnects to the gate of MOS transistor 34 and the contact hole 51bconnects to a source or drain of another MOS transistor. Therefore, contact holes 51a,51bare not located on the same vertical cross section.

[0010] As shown in FIG. 8, a glue layer or barrier layer 52 and a metal layer 54 are formed, respectively, on the silicon substrate 12 and fill both the landing via hole 50 and the contact holes 51a,51b.The glue layer or barrier layer 52 and the metal layer 54 are, respectively, composed of titanium, or titanium nitride and tungsten metal. Thereafter, as shown in FIG. 9, the dielectric layer 48 is used as an etching stop layer for chemical mechanical polishing (CMP) of the metal layer 54 so as to form a landing via 55 and contact plugs 56a,56b.Next, as shown in FIG. 10, a metal conductor layer 57 is formed on the semiconductor wafer 10, followed by the formation of a patterned photoresist layer 58 on the metal conductor layer 57 to define patterns of metal conductors. The metal conductor layer 57 is composed of aluminum (Al), copper (Cu) or aluminum copper alloy. Finally, as shown in FIG. 11, an etching process is performed to remove the metal conductor layer 57 not covered by the photoresist layer 58 so as to form metal conductors 59a,59bconnecting to the landing via 55 and contact plugs 56a,56b,respectively. The metal conductor 59b,electrically connects the gate of the MOS transistor 34 with a source or drain of another MOS transistor, and together with the contact plugs 56a,56bforms a local interconnection.

[0011] However, in the disclosure of the prior art method for fabricating an embedded memory, in order to simultaneously form gates in both the periphery circuit region and the memory array area, the electrical properties of the periphery circuit region is taken into account whereby a polycide layer is directly deposited on the polysilicon layer for reducing the resistance of the gate structure in the periphery circuit region. A self-aligned silicide operation is also used to form a salicide layer on each source and drain for reducing the contact interface resistance of the MOS transistors. Generally speaking, the polycide layer formed by deposition has a greater resistivity than that of the salicide layer. Hence, the electrical performance of the gate structure composed of both the polycide layer and a cap layer in the periphery circuit region differs with that of the gate structure composed of the salicide layer in the conventional periphery circuit region to result in the unfitness of the cell library established by logic circuits. Secondly, after the formation of the MOS transistor of an embedded memory according to the prior art method, the landing via and local interconnection of the embedded memory are fabricated separately. Thus, at least four photomasks are needed in the prior art process, leading to a costly and complicated process.

[0012] It is therefore a primary objective of the present invention to provide a method for integrating the process of manufacturing an embedded memory and the process of manufacturing a landing via and a strip contact in the embedded memory, to simplify the complexity and decrease the cost of the process. As well, the strip contact of the present invention efficiently reduces the occupied space in the memory cell, to therefore reduce the volume of the unit memory.

[0013] The method of the present invention involves first defining a memory array region and a periphery circuit region on the semiconductor wafer. Then, a plurality of gates and lightly doped drains (LDD) are formed in the memory array region and periphery circuit region. Next, silicon nitride is deposited to cover the surface of each gate in the memory array region, followed by the formation of a spacer adjacent to each gate in the periphery circuit region. A dielectric layer is then formed on the surface of the semiconductor wafer and a landing via hole and a strip contact hole are formed in the dielectric layer in the memory array region and the periphery circuit region, respectively. Finally, a conductive layer is filled into each hole to simultaneously form each landing via and strip contact.

[0014] The present invention method integrates the process of manufacturing an embedded memory and the sequential process of forming a landing via and a strip contact in the embedded memory, so the complexity and the cost are significantly decreased. Moreover, the present invention combines the area connecting a gate and the area connecting a source or drain in the strip contact of the periphery circuit region to form a single conductive line. Thus, the occupation of space by the strip contact is largely reduced to increase integration.

[0015] These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.

[0016] FIG. 1 to FIG. 11 are schematic diagrams of fabricating an embedded memory according to the prior art.

[0017] FIG. 12 to FIG. 26 are schematic diagrams of fabricating a landing via and strip contact in an embedded memory according to the present invention.

[0018] Please refer to FIG. 12 to FIG. 26. FIG. 12 to FIG. 26 are schematic diagrams of in-situ fabricating a landing via and strip contact of an embedded memory on a semiconductor wafer 60 according to the present invention. As shown in FIG. 12, a semiconductor wafer 60 has both a memory array region 62 and a periphery circuit region 64 defined on the surface of a silicon substrate 72. The memory array region 62 comprises at least a cell-well 66, and the periphery circuit region 64 comprises at least a N-well 68 and at least a P-well 70. Several shallow trench isolation (STI) structures 61 are formed to separate each region.

[0019] The present invention involves first forming a first dielectric layer 74, an undoped polysilicon layer 76, and a dielectric layer 78, respectively, on the surface of the semiconductor wafer 60. Then, as shown in FIG. 13, a mask layer 80 is formed on the dielectric layer 78 in the periphery circuit region 64. An N-type ion implantation process is performed on the undoped polysilicon layer 76 in the memory array region 62 to subsequently become an N-type doped polysilicon layer 82.

[0020] Thereafter, as shown in FIG. 14, an etching process is performed to completely remove the dielectric layer 78 in the memory array area 62, as well as to etch the doped polysilicon layer 82 down to approximately half the total depth of the undoped polysilicon layer 76, or about 1000˜1900 Å. As shown in FIG. 15, after removing the mask layer 80 on the periphery circuit region 64, a silicide layer 84, a silicon-oxy-nitride (SiO_xN_y) layer 86, a silicon nitride layer 88, and a photoresist layer 90 are formed, respectively, on the surface of the semiconductor wafer 60. The silicide layer 84 is formed to reduce the contact interface resistance of the doped polysilicon layer 82, the silicon-oxy-nitride (SiO_xN_y) layer 84 is an anti-reflection coating (ARC) layer, and the silicon nitride layer 88 serves as a protection layer.

[0021] A photolithographic process is performed so as to define a pattern of plurality of gates 91 in the photoresist layer 90 above the cell-well 66 of the memory array region 62. As shown in FIG. 16, the pattern of the photoresist layer 90 is used as a hard mask to etch the silicon nitride layer 88, the silicon-oxy-nitride layer 86, the silicide layer 84, and the doped polysilicon layer 82 positioned in the memory array area 62 down to the surface of the dielectric layer 74. Thus, a plurality of MOS transistor gates 91 are formed in the memory array area 62. An in-situ etching of the silicon nitride layer 88, the silicon-oxy-nitride layer 86 and the silicide layer 84 in the periphery circuit region 64 is performed down to the surface of the dielectric layer 78.

[0022] Then, as shown in FIG. 17, an ion implantation process is performed to form lightly doped drains (LDD) 92 for each MOS transistor in the memory array region 62, followed by the removal of the photoresist layer 90. As shown in FIG. 18, after removing the photoresist layer 90, the dielectric layer 78 in the periphery circuit region 64 is also removed. A photoresist layer 94 and a silicon-oxy-nitride layer (not shown) are formed on the surface of the semiconductor wafer 60. The silicon-oxy-nitride layer serves as an anti-reflection coating (ARC) layer. As shown in FIG. 19, a photolithographic process is then performed to define a pattern of a plurality of gates in the photoresist layer 94 above the P-well 70 and the N-well 68 of the periphery circuit region 64. Next, the pattern of the photoresist layer 94 is used as a hard mask to etch the undoped polysilicon layer 76 in the periphery circuit region 64 down to the surface of the dielectric layer 74 so as to form gates 93, 95 for each MOS transistor in the periphery circuit region 64.

[0023] As shown in FIG. 20, an ion implantation process is performed to form lightly doped drains (LDD) 92 for each MOS transistor in the periphery circuit region 64. After removing the photoresist layer 94, a silicon nitride layer 97 is formed on the surface of the semiconductor wafer 60 to cover the surface of each gate 91, 93 and 95, as shown in FIG. 21. Then, as shown in FIG. 22, a photoresist layer (not shown) and a photolithographic process are used to define the mask pattern. The mask pattern is used to etch portions of the silicon nitride layer 97 around each gate 93, 95 in the periphery circuit region 64 so as to form spacers 96. Next, an ion implantation process is performed to form sources 98 and drains 100 of the MOS transistor in the periphery circuit region 64.

[0024] After the formation of the sources 98 and the drains 100 of each MOS transistor in the periphery circuit region 64, a metal layer (not shown), made of Co, is formed on the surface of the semiconductor wafer 60, as shown in FIG. 23. The metal layer covers the surfaces of the sources 98, the drains 100, and the gates 93, 95 in the periphery circuit region 64. Then, a first rapid thermal process (RTP) is performed at a temperature between 400° C. and 600° C. for a duration of 10 to 50 seconds. As a result, a salicide layer 102 is formed on the surfaces of each source 98, drain 100 and gates 93, 95 in the periphery circuit region 64. A wet etching process is performed to remove the portions of the metal layer that do not react with the surface on the semiconductor wafer 60. Finally, a second rapid thermal process (RTP) is performed at a temperature between 600° C. to 800° C. for a duration of 10 to 50 seconds, leading to the Co₂Si and CoS of the salicide layer 102 to react to form CoSi₂, which has a lower resistance. Co can also be replaced by other metals such as Ti, Ni, or Mo to form the metal layer.

[0025] As shown in FIG. 24, a dielectric layer 104 and a photoresist layer 106 are formed, respectively, on the surface of semiconductor wafer 60. A photolithographic process is then performed to define a pattern of a landing via and strip contact in the photoresist layer 106. Then, the pattern of the photoresist layer 106 is used as a hardmask to etch the dielectric layer 104. Thus, a landing via hole 108 is formed in the dielectric layer 104 in the memory array region 62, and a strip contact hole 110 is formed in-situ in the dielectric layer 104 in the periphery circuit region 64, as shown in FIG. 25. Since the strip contact hole 110 is connected to the gate 95 and source or drain of another MOS transistor, the strip contact hole 110 and gate 95is thus located in different vertical planes. Finally, as shown in FIG. 26, a conductive layer 112 fills into the landing via hole 108 and the strip contact hole 110 to form in-situ each landing via 114 and strip contact 116.

[0026] In contrast to the prior art method for fabricating a landing via and strip contact of an embedded memory, the fabricating method according to the present invention integrates the process of manufacturing an embedded memory and the sequential process of forming a landing via and a strip contact in the embedded memory. Both a landing via and a strip contact are in-situ formed so as to reduce the complexity and the cost of the process. Moreover, the strip contact of the present invention uses a conductive line to connect the neighboring gate with the source or drain, to largely decrease the occupied space of the strip contact and reduce the volume of the memory device and increase integration.

[0027] Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.