Auto aggregation method for IP prefix/length pairs

[0002] This invention relates generally to data communications networks, and more particularly, to an auto aggregation method for IP prefix/length pairs.

[0003] Unicast Internet protocol (IP) subnets are described by an IP prefix and a subnet mask. With the introduction of classless inter-domain routing (CIDR), subnet masks must be contiguous, which allows consistent hierarchical addressing. This allows state requirements for Internet devices to be scalable, as large groups of addresses can be summarized into one entry. Because of the CIDR requirement for contiguous subnet masks, they can be described as an integer, which is the length of the mask.

[0004] In certain situations, such as a border gateway protocol (BGP) border, administrators usually configure a summarization of a set of IP subnets to be advertised. This is typically accomplished through manual configuration by an administrator. It is desirable to be able to automatically generate a summary of IP prefix/length pairs for auto-configuration. Situations where this is useful are generally on borders where summarization occurs. Example situations include borders within a given routing protocol, such as open shortest path first (OSPF) area border routers; borders between routing protocols, such as an OSPF or routing information protocol (RIP) border router; borders between autonomous systems, such as BGP-4 border router announce, and special cases such as BGP-4 border router “black-hole” routes.

[0005] The hard-coded aggregation state of manual configuration typically does not allow optimal path selection in certain scenarios where routes that are part of a summary have gone away. Therefore, there is a need for a way to automatically generate the largest possible set of aggregates given an set of IP prefix/length pairs.

[0006] The present invention provides a method, apparatus and article of manufacture for aggregating a sorted list of IP prefix pairs. A prefix pair in the list is compared to a lowest IP length subnet boundary. The prefix pair is added to a final list if the prefix pair is not on the lowest IP length subnet boundary and the prefix pair is not a first in pair. The prefix pair is moved to a next lower length list if the prefix pair is on the lowest IP length subnet boundary and the prefix pair is a next expected pair. A next higher list is selected, and the method is repeated until there are no more lists.

[0007] The present invention is illustrated by way of example and may be better understood by referring to the following description in conjunction with the accompanying drawings, in which like references indicate similar elements and in which:

[0008] FIG. 1 shows system diagram which shows a computer hardware environment compatible with the present invention;

[0009] FIG. 2 shows an IP agregation example compatible with the present invention;

[0010] FIG. 3 shows flowchart for aggregating a sorted list of IP prefix pairs compatible with the present invention.

[0011] In the following description of a preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

[0012] The present invention provides way of aggregating a sorted list of IP prefix pairs. A prefix pair in the list is compared to a lowest IP length subnet boundary. The prefix pair is added to a final list if the prefix pair is not on the lowest IP length subnet boundary and the prefix pair is not a first in pair. The prefix pair is moved to a next lower length list if the prefix pair is on the lowest IP length subnet boundary and the prefix pair is a next expected pair. A next higher list is selected, and the method is repeated until there are no more lists.

[0013] The ability of the present invention to auto-aggregate prefix, length pairs provides the following advantages:

[0014] Reduced configuration time required by an administrator;

[0015] Reduced liklihood that some possible aggregates will be omitted;

[0016] If subnets are moved from area to area, no router re-configuration is needed;

[0017] Elimintaion of suboptimal routing that may occur because of “hard-coded” aggregates.

[0018] In any situation where multiple routing protocol domains are connected, a border is formed which may or may not be an AS border. It is often desirable to aggregate prefixes from one domain to the next. The present invention can be used on a RIP/OSPF Border Router to aggregate the routes from one protocol before importing the routes into the other.

[0019] The Internet is loosely arranged as a hierarchy of domains. Stub domains connect to regional providers which then connect to backbone providers. At each border, summarization of routes typically occurs. It is useful in certain circumstances to use the present invention to allow a router to auto-aggregate prefixes.

[0020] Another BGP-4 circumstance exists where auto-aggregation is useful for an internal state that a router keeps. Often at a border router, a prefix is advertised but not every part of the advertised address space is used. If a default route also exists at the border router, then loops may occur if a packet arrives on the interface where the aggregate is advertised. This happens because a packet from an unknown internal subnet arrives, which is then sent towards the default route back in the direction from where the packet originated. To prevent this problem, administrators may configure “black-hole” static routes for subnets not yet in use. The present invention can be used to find the largest used blocks and automatically install these black hole routes.

[0021] FIG. 1 illustrates one embodiment of a computer system 100 which implements the principles of the present invention. Computer system 100 comprises a processor 105, a storage device 110, and a bus 115. The processor 105 is coupled to the storage device 110 by the bus 115. In addition, a number of user input/output devices, such as a keyboard 120 and a display 125, are also coupled to the bus 115. The processor 105 represents a central processing unit of any type of architecture, such as CISC, RISC, VLIW, or hybrid architecture. In addition, the processor 105 could be implemented on one or more chips. The storage device 110 represents one or more mechanisms for storing data. For example, the storage device 110 may include read only memory (ROM), random access memory (RAM), magnetic disk storage mediums, optical storage mediums, flash memory devices, and/or other machine-readable mediums. The bus 115 represents one or more buses (e.g., AGP, PCI, ISA, X-Bus, VESA, etc.) and bridges (also termed as bus controllers). While this embodiment is described in relation to a single processor computer system, the invention could be implemented in a multi-processor computer system.

[0022] In addition to other devices, one or more of a network 130, a TV broadcast signal receiver 131, a fax/modem 132, a digitizing unit 133, a sound unit 134, and a graphics unit 135 may optionally be coupled to bus 115. The network 130 and fax modem 132 represent one or more network connections for transmitting data over a machine readable media (e.g., carrier waves). The digitizing unit 133 represents one or more devices for digitizing images (i.e., a scanner, camera, etc.). The sound unit 134 represents one or more devices for inputting and/or outputting sound (e.g., microphones, speakers, magnetic storage devices, optical storage devices, etc.). The graphics unit 135 represents one or more devices for generating 3-D images (e.g., graphics card).

[0023] FIG. 1 also illustrates that the storage device 110 has stored therein data 135 and software 136. Data 135 represents data stored in one or more of the formats described herein. Software 136 represents the necessary code for performing any and/or all of the techniques described with reference to FIGS. 3-6. It will be recognized by one of ordinary skill in the art that the storage device 110 preferably contains additional software (not shown), which is not necessary to understanding the invention.

[0024] FIG. 1 additionally illustrates that the processor 105 includes decode unit 140, a set of registers 141, and execution unit 142, and an internal bus 143 for executing instructions. It will be recognized by one of ordinary skill in the art that the processor 105 contains additional circuitry, which is not necessary to understanding the invention. The decode unit 140, registers 141 and execution unit 142 are coupled together by internal bus 143. The decode unit 140 is used for decoding instructions received by processor 105 into control signals and/or microcode entry nodes. In response to these control signals and/or microcode entry nodes, the execution unit 142 performs the appropriate operations. The decode unit 140 may be implemented using any number of different mechanisms (e.g., a look-up table, a hardware implementation, a PLA, etc.). While the decoding of the various instructions is represented herein by a series of if/then statements, it is understood that the execution of an instruction does not require a serial processing of these if/then statements. Rather, any mechanism for logically performing this if/then processing is considered to be within the scope of the implementation of the invention.

[0025] The registers 141 represent a storage are on processor 105 for storing information, including control/status information, integer data, floating node data, and packed data. It will be understood by one of ordinary skill in the art that one aspect of the invention is the described instruction set for operating on packed data. According to this aspect of the invention, the storage area used for storing the packed data is not critical. The term data processing system is used herein to refer to any machine for processing data, including the computer systems(s) described with reference to FIG. 1.

[0026] IPv4 subnets are typically described by a 32-bit IP address and an associated 32-bit subnet mask, which represents contiguous ones and thus can also be described as an integer. The subnet mask describes the number of bits in the IP address that represent the subnet portion of the address. A logical AND operations can be performed on the mask and the address to determine the IP subnet number.

[0027] With the introduction of CIDR, a hierarchical addressing model can be implemented, because all subnet masks are contiguous and thus can be aggregated. Every two blocks of a given length that fall on a subnet boundary or are adjacent to each other can be aggregated to the next level of length. An example of aggregation is shown in FIG. 2. As shown in FIG. 2, prefixes with their associated mask lengths are shown with the range of addresses that they represent. Two sets of two of prefix length 27 are aggregated to prefix length 26.

[0028] The present invention takes any number of IP prefix and length pairs and returns a set of the greatest set of aggregated IP prefix/length pairs. The following constraints must be observed in implementing the invention:

[0029] 1. Aggregation must begin at the longest length. This is because it is impossible to predict future aggregations without first performing aggregations at the lowest end of the hierarchy.

[0030] 2. Given any two prefix/length pairs, it is desirable to be able to quickly tell if they are “adjacent”.7

[0031] 3. If two pairs are adjacent, it must be determined if they lie on a length boundary. If both conditions exist, then they can be aggregated. From the example above in FIG. 2, it will be noted that 192.1.1.64/26 and 192.1.1.128/26 are adjacent, but do not fall on a length boundary.

[0032] 4. The present invention may be implemented recursively such that formed aggregates may be aggregated further.

[0033] A sorting operation based on IP prefix is typically required for implementing the invention. This allows a linear time complexity operation for moving through the list to find possible aggregates.

[0034] A flow chart of an embodiment of the present invention is show in FIG. 3. At step 301, a sorted linked list is created per prefix length, sorting based on the IP prefix. This operation will end with a list per prefix length in which the list is sorted per IP prefix. This can be performed with no copying, by using pointer manipulation. At step 303, a current length list pointer is set to the next highest length list. At step 305, starting with the current length list, the list is searched. At step 307, for each prefix, it is determined whether the prefix lies on the next lowest IP length subnet boundary. If so, it is a potential “first in pair”. If not, and there is no current “first in pair”, then it is not possible to aggregated the pair and the pair is placed on a “final list”. At step 309, if the prefix pair is the next expected prefix from the “first in pair”, then the prefix pair can be aggregated, and at step 311 the prefix pair is moved to the next lowest length list. At step 313, the list pointer is incremented to the next highest list. If at step 315 there are more lists, control returns to step 303.

[0035] For the purpose of explanation when analyzing the time complexity of the present invention, it is assumed that there are n prefixes to summarize, with k prefixes in each length. The first step of the present invention involves sorting n prefixes into k sub-lists. It is typical that this sorting operation can be performed in nlog(n) time using a logarithmic sorting algorithm. The remaining steps of the present invention involve traversing all sub-lists and finding aggregates which are repositioned into “lower” prefix lists. If no summaries are found at all, this step is bounded by O(n). If the maximal amount of summaries are found at every length, then the worst case is O(n+(n/2)−1). Therefore, the execution speed of the present invention is bounded by nlog(n).

[0036] Using the present invention with an OSPF Area Border Router minimizes configuration in routers where interfaces are configured into areas. Because of the possible overhead in implementing the present invention in border routers, several implementation switches may optionally be provided.

[0037] OSPF summary LSA's are generated by OSPF area border routers and sent into the backbone for all Router and Network LSA's within attached areas. The principle behind OSPF hierarchical routing is to reduce both the flooding and state required of routers. An implementation of the present invention in OSPF may optionally have the following switches for each backbone interface:

[0038] Turn auto-aggregation on or off;

[0039] Configure auto-aggregation to occur periodically or dynamically;

[0040] Configure a holddown timer for subtraction;

[0041] Configure a method to use for announcing a metric. This may be, but is not limited to, highest, lowest or reset and announce one;

[0042] Periodic aggregation means that the present invention runs periodically (e.g. every 30 minutes). Additional LSA's from attached areas are flooded individually into the backbone until the next run, after which they are flushed. If LSA's from an area are flushed, then there are two options: immediately run the algorithm and originate a set of most summarized routes, or start a holddown timer before running the algorithm.

[0043] Dynamic aggregation means that the present invention runs every time a new LSA or a flushed LSA is received. This keeps summarized LSA's always representative of what is reachable. The disadvantage of doing so is increased computation cost.

[0044] When an OSPF border router learns a new route in an attached area, it may either run the auto-aggregation algorithm to immediately see if the aggregate can be added into a area summary or it can perform the calculation at a later time when resources are available.

[0045] When an OSPF border router receives (or originates) a new LSA in an attached area, it performs the following if configured for immediate addition:

[0046] 1. Run auto-aggregation algorithm to see if new route (i.e. subnet range) “fits” into existing summary for area

[0047] 2. If yes, then announce new summary LSA (for area)

[0048] 3. If no, announce separate summary for newly learned route

[0049] When an OSPF border router receives (or originates) a new LSA in an attached area, it performs the following if configured for delayed addition:

[0050] 1. Announce new route (LSA) as separate summary LSA

[0051] 2. Mark new LSA

[0052] 3. When resources are available, run auto-aggregation algorithm on marked LSAs to see if these ranges “fit” into existing summary

[0053] 4. If yes, then announce a new summary LSA and withdraw initially announced separate summary LSA (for new route)

[0054] 5. If no, do nothing

[0055] When an OSFP border router receives (or originates) a withdraw for an LSA in an attached area, it may either:

[0056] 1. Immediately re-run the algorithm to re-summarize routes in the area

[0057] 2. Do nothing

[0058] In the second case, if the deleted subnet is moved to another area, it will by definition not fit into the summary range of another area and will be announced separately. Because a separate more specific route will exist to this subnet in the backbone, no harm will be done. The first case requires that the algorithm be run more frequently. However, the first case will generally present a less confusing view of the network to the administrator.

[0059] An example source code listing for an embodiment of the present invention is given below.

[0060] While the invention is described in terms of preferred embodiments in a specific system environment, those of ordinary skill in the art will recognize that the invention can be practiced, with modification, in other and different hardware and software environments within the spirit and scope of the appended claims.