Methods of forming field effect transistors and related field effect transistor constructions

[0002] This is a divisional application of U.S. patent application Ser. No. 08/968,085 filed Nov. 12, 1997, entitled “Methods of Forming Field Effect Transistors and Related Field Effect Transistor Constructions”, naming Zhiqiang Wu and Paul Hatab as inventors, and which is now U.S. Pat. No. 6,025,232, the disclosure of which is incorporated by reference.

[0003] This application relates to methods of forming field effect transistors and related field effect transistor constructions.

[0004] Transistors find use in a wide range of integrated circuits. One type of transistor is the metal-oxide-semiconductor field effect transistor or MOSFET. Typical MOSFETs include source/drain diffusion regions which are disposed within a substrate and a conductive gate which overlies a channel region intermediate the source/drain diffusion regions. In some MOSFETs, placement of a desired voltage on the conductive gate enables a channel to be formed between the source/drain diffusion regions. With the channel being formed, current can be made to flow between the source and the drain. There are a number of different types of MOSFETs such as NMOS and PMOS field effect transistors.

[0005] NMOS field effect transistors are typically formed on a p-type substrate or p-well. The channel in an NMOS transistor is usually formed through provision of a positive gate voltage on the transistor which attracts minority electrons within the p-type substrate into the channel region. PMOS field effect transistors are typically formed on an n-type substrate or n-well. The channel in PMOS transistors is typically formed through provision of a negative gate voltage on the transistor gate which attracts minority holes from the n-type substrate into the channel region to form the channel. CMOS (Complementary Metal Oxide Semiconductor) transistors utilize both NMOS and PMOS devices.

[0006] An important parameter in MOS transistors is the threshold voltage V_t, which is the minimum gate voltage required to induce the channel. In general, the positive gate voltage of an n-channel device (NMOS) must be larger than some value V_tbefore a conducting channel is induced. Similarly, a p-channel device (PMOS) requires a gate voltage which is more negative than some threshold value to induce the required positive charge in the channel. A valuable tool for controlling threshold voltage is ion implantation. Because very precise quantities of impurity can be introduced into the substrate by this method, it is possible to maintain close control of V_t. For example, introduction of a p-type impurity into a p-channel PMOS device can make V_tless negative. This is because the channel region is made more p-type and therefor a lower magnitude of negative voltage is required to induce holes within the channel region.

[0007] As MOS transistors are made smaller and smaller, they become susceptible to so-called short channel effects. Short channel effects can be divided into (a) those that impact V_t, (b) those that impact subthreshold currents, and (c) those that impact I-V behavior beyond threshold. Short channel effects include punch through which normally occurs as a result of the widening of the drain depletion region when the reverse-bias voltage on the drain is increased. The electric field of the drain may eventually penetrate into the source region and reduce the potential energy barrier of the source-to-body junction. When this occurs, more majority carriers in the source region have enough energy to overcome the barrier, and an increased current then flows from the source to the body, some of which is collected by the drain. One way of reducing the electric field of the drain and hence the risk of punch through is to form so-called halo regions proximate the source/drain regions of a transistor. Halo regions are described in more detail in the texts which are incorporated by reference below.

[0008] One type of MOS transistor is a buried channel PMOS. Buried channel PMOS transistors typically have a p-diffusion region disposed within the substrate underneath the gate and between the source/drain diffusion regions. The elevational thickness of the p-diffusion region within the substrate is referred to as gamma-j. One goal in the design of buried channel PMOS transistors is to reduce gamma-j to improve control over current leakage. It is also desirable to provide the p-region as close to the gate as possible to provide for more gate control.

[0009] For a more detailed treatment of short channel effects and other relevant semiconductor processing concerns, the reader is referred to two texts: Wolf, Silicon Processing for the VLSI Era,Volume 2, Chapters 5 and 6; and Streetman, Solid State Electronic Devices,Fourth Edition, both of which are expressly incorporated by reference herein.

[0010] This invention arose out of concerns associated with improving the methodology through which MOS devices are fabricated, and improving the resultant MOS structures.

[0011] Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are provided into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

[0012] Preferred embodiments of the invention are described below with reference to the following accompanying drawings.

[0013] FIG. 1 is a diagrammatic sectional view of a semiconductor wafer fragment undergoing processing in accordance with one embodiment of the present invention.

[0014] FIG. 2 is a view of the FIG. 1 wafer fragment at a different processing step.

[0015] FIG. 3 is a view of the FIG. 1 wafer fragment at a different processing step.

[0016] FIG. 4 is a view of the FIG. 1 wafer fragment at a different processing step.

[0017] FIG. 5 is a view of the FIG. 1 wafer fragment at a different processing step.

[0018] FIG. 6 is a view of the FIG. 1 wafer fragment at a different processing step.

[0019] FIG. 7 is a view of the FIG. 1 wafer fragment at a different processing step.

[0020] FIG. 8 is a view of the FIG. 1 wafer fragment at a different processing step.

[0021] FIG. 9 is a view of the FIG. 1 wafer fragment at a different processing step.

[0022] FIG. 10 is a view of the FIG. 1 wafer fragment at a different processing step.

[0023] FIG. 11 is a view of the FIG. 1 wafer fragment at a different processing step.

[0024] FIG. 12 is a view of the FIG. 1 wafer fragment at a different processing step.

[0025] FIG. 13 is a view of the FIG. 1 wafer fragment at a different processing step.

[0026] FIG. 14 is a view of a wafer fragment undergoing processing in accordance with an alternate embodiment of the present invention.

[0027] FIG. 15 is a view of the FIG. 14 wafer fragment at a different processing step

[0028] This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).

[0029] Referring to FIG. 1, a semiconductor wafer fragment in process is shown generally at 20 and includes semiconductive substrate 22. Substrate 22 comprises a first conductivity type which is preferably n-type. Such substrate can constitute an n-well which is suitable for use in forming CMOS circuitry. A pair of isolation oxide regions 24, 26 are received within substrate 22 and define therebetween an active area within which a transistor is to be formed. In the illustrated example, regions 24, 26 are formed through shallow trench isolation techniques.

[0030] Referring to FIG. 2, a masking layer 28 is formed over substrate 22. An exemplary material for layer 28 is oxide such as that formed through decomposition of tetraethylorthosilicate (TEOS). A first opening 30 is formed through masking layer 28 and defines a substrate area over and within which a field effect transistor gate and channel region respectively are to be formed. The opening includes a pair of sidewalls 32, 34 which face one another.

[0031] Referring to FIG. 3, dopant comprising the first conductivity type, e.g., n-type, is provided through opening 30 and into substrate 22. In the illustrated example the dopant is provided through multiple doping steps and comprises a first dopant 36 and a second dopant 38. First dopant 36 is implanted into substrate 22 at a first energy level or acceleration voltage and defines a first average elevational dopant level L₁within the substrate. Second dopant 38 is implanted into the substrate through a second implant conducted at a second energy level or acceleration voltage which is different from the first energy. Accordingly, a second average elevational dopant level L₂is defined within substrate 22 which is different from first level L₁. In the illustrated example, the first energy which is utilized to implant first dopant 36 is lower than the second energy which is utilized to implant dopant 38. First dopant 36 comprises dopant or impurity which will ultimately serve as one component of the lightly doped drain regions of a transistor; and second dopant or impurity 38 comprises dopant which will ultimately provide halo doping regions for the transistor. Exemplary first and second dopants comprise arsenic and phosphorus respectively.

[0032] An exemplary energy or accelerating voltage for first dopant 36 is about 50 keV; although a range from between about 10-70 keV is sufficient. An exemplary dose for first dopant 36 is about 3.5×10¹²cm⁻²; although a range from between about 1×10¹²cm⁻²to 5×10¹²cm⁻²is sufficient. An exemplary second energy or accelerating voltage for second dopant 38 is about 100 keV; although a range from between about 50-200 keV would be sufficient. An exemplary dose is about 5×10¹²cm⁻²; although a dose from between 2×10¹²cm⁻²to 1×10¹³cm⁻²would be sufficient. First and second dopants 36, 38 include respective portions 37, 39 which extend outwardly of the substrate area within which the channel region is to be formed. Alternatively, dopant of the first conductivity type can be provided into substrate 22 through an angled ion implant which is conducted at a suitable angle away from vertical to at least form portions 37 outwardly of the area in which the channel region is to be formed.

[0033] Referring to FIG. 4, an optional sacrificial oxide layer 40 can be formed over substrate 22 within opening 30. An exemplary thickness for layer 40 is around 90 Angstroms. Additionally, such layer can be formed prior to provision of first and second dopants 36, 38.

[0034] Referring to FIG. 5, a layer 42 comprising an insulative material is formed over substrate 22 within opening 30 and over sacrificial oxide layer 40. An exemplary material for layer 42 comprises a suitable nitride material. Layer 42 can also comprise material which ultimately forms a conductive portion of a transistor gate. An exemplary material is polysilicon.

[0035] Referring to FIG. 6, layer 42 is selectively etched relative to sacrificial oxide layer 40 to form sidewall spacers 44, 46 over sidewalls 32, 34 respectively. Sidewall spacers 44, 46 define a second opening 31 which is smaller in dimension than first opening 30.

[0036] Referring to FIG. 7, third dopant 48 of a second conductivity type is provided through opening 30 and into substrate 22. In the illustrated example, third dopant 48 defines third average elevational dopant levels L₃, L₄within substrate 22 which can be different from first and second average elevational dopant levels L₁, L₂. Third dopant 48 comprises p-type dopant at least a portion of which is an enhancement dopant to compensate for n-type arsenic which is disposed within the channel region. At least some of third dopant 48 is provided inwardly of substrate portions over which sidewalls 44, 46 are disposed.

[0037] In the illustrated example, third dopant 48 comprises two doped regions 50, 52. An exemplary dopant for doped region 50 comprises BF₂which is provided into substrate 22 at an energy or acceleration voltage of about 25 keV; although a range from between about 10-35 keV will suffice. An exemplary dose for the BF₂dopant is about 8×10¹²cm⁻²; although doses from between about 3×10¹²cm⁻²to 2×10¹³cm⁻²will suffice. An exemplary material for doped region 52 comprises boron which is provided at an energy or acceleration voltage of about 18 keV; although energies from between about 5-25 keV will suffice. An exemplary dose for the boron is about 5×10¹²cm⁻²; although a range from between 2×10¹²cm⁻²to 1×10¹³cm⁻²will suffice.

[0038] Referring to FIG. 8, sacrificial oxide layer 40 between sidewall spacers 44, 46 is removed. FIG. 8 also shows a resultant doping profile a within the substrate as a result of the doping steps described above.

[0039] Referring to FIG. 9, a gate oxide layer 54 is formed over substrate 22 and between sidewall spacers 44, 46.

[0040] Referring to FIG. 10, a conductive layer 56 is formed over substrate 22 and between sidewall spacers 44, 46. An exemplary material comprises conductively-doped polysilicon which defines a transistor gate layer. In one embodiment, the conductive layer 56 comprises conductively doped, n-type polysilicon. A refractory metal layer can be formed over as substrate 22 and reacted with layer 56 to form a silicide layer 58 over transistor gate layer 56.

[0041] Referring to FIG. 11, layers 56, 58 are planarized relative to masking layer 28 to form a transistor gate 60. An exemplary planarization technique comprises mechanical abrasion as by chemical-mechanical polishing. Transistor gate 60 is formed within opening 30 proximate or adjacent sidewall spacers 44, 46 and is formed over the channel region. The transistor gate can, however, be formed prior to formation of sidewall spacers 44, 46.

[0042] Referring to FIG. 12, masking layer 28 is stripped or otherwise removed to outwardly expose transistor gate 60.

[0043] Referring to FIG. 13, source/drain diffusion regions 62, 64 are formed by providing impurity of the second conductivity type, e.g., p-type, into substrate 22. Accordingly, the impurity is disposed proximate transistor gate 60 and on either side thereof. Diffusion regions 62, 64 are also disposed operably proximate the halo doping impurity and lightly doped drain impurity which was previously provided. An exemplary p-type impurity is BF₂which can be provided into the substrate at an energy or accelerating voltage of about 20 keV; although a range from between about 5-30 keV is sufficient. An exemplary dose is about 2×10¹⁵cm⁻²; although a range from between about 5×10¹⁴cm⁻²to 4×10¹⁵cm⁻²will suffice. Subsequently, the substrate can be annealed sufficiently to diffuse the provided impurity within the substrate and form lightly doped drain regions 66, 68 and halo regions 70, 72 operably proximate source/drain diffusion regions 62, 64. Specifically, during the annealing of the substrate, some p-type source/drain dopant diffuses laterally outwardly and into a substrate portion having the illustrated n- and n-regions (FIG. 12). The net result of the diffusion between the p-type dopant and the n- and n-dopant is a compensation effect in which p-LDD regions 66, 68, and n-halo regions 70, 72 are formed. Exemplary temperature and time conditions for annealing the substrate are about 875° C. for a duration of around 40 minutes. Optionally, prior to the provision of the source/drain regions, sidewall spacers can be formed over spacers 44, 46 respectively.

[0044] Referring to FIGS. 14 and 15, an alternate embodiment is described. Like numbers from the above-described embodiment have been utilized where appropriate with differences being indicated by the suffix “a” or with different numerals. Accordingly, a masking layer 28ais formed over substrate 22 and comprises polysilicon which is doped with a p-type impurity. A layer 74 is formed over masking layer 28aand comprises an insulative material such as an oxide. An opening 31ais provided through layers 28aand 74 and is defined in part by sidewall spacers 44a, 46a.

[0045] Referring to FIG. 15, a transistor gate layer 56aand a silicide layer 58aare formed over substrate 22 and within opening 31a. Layers 56a, 58aare sufficiently etched to leave at least some material of the layers overlapping with masking layer 28a.

[0046] Portions of masking layer 28aand layer 74 which are disposed laterally outwardly of opening 31aare removed to leave behind a pair of spaced-apart blocks 76, 78. The portions of masking layer 28awhich are removed comprise portions which are not overlapped with conductive material of transistor gate 60a. Substrate 22 is exposed to conditions which are effective to outdiffuse p-type dopant from masking layer 28ainto the substrate. Accordingly, such outdiffusion forms source/drain diffusion regions 62a, 64a, respectively.

[0047] Individual blocks 76, 78 have respective outwardly facing sidewalls 80, 82, and 84, 86. A generally planar block top 81 extends between sidewalls 80, 82; and a generally planar block top 85 extends between sidewalls 84, 86. Sidewalls 82, 86 face one another and define an opening which corresponds to first opening 30. Sidewall spacers 44a, 46aare disposed over respective sidewalls 82, 86 and define a second opening 31a. Source/drain diffusion regions 62a, 64aare received within substrate 22 beneath blocks 76, 78 respectively, and comprise individual bottommost portions 88, 90. The diffusion regions also comprise respective side portions 89, 91 which are joined with the respective bottommost portions and face one another. In the illustrated example, side portions 89, 91 define an area A therebetween and halo regions 70a, 72aare joined with respective side portions 89, 91 and are disposed entirely with area A. Transistor gate 60aincludes a pair of extensions 92, 94 which are disposed over block 76, 78 respectively. Silicide layer 58aincludes portions which are disposed over the extensions and comprise a portion thereof.

[0048] The above-described methodologies and structures provide reliable lightly doped drain regions and punch through implants, especially for buried channel PMOS transistors. Lower source/drain junction capacitances are provided which increases the transistor's operating speed. The ability to provide compensated lightly doped drain regions provides increased control over the overlap between the gate and the p+ source/drain diffusion regions. Improved control over leakage current is provided by having a shallow gamma-j parameter. Uniform enhancement is provided across the channel region with little if any encroachment by the halo region. Localization of the halo region reduces the source/drain junction capacitances which, as mentioned above, increases the operating speed of the transistor. Additionally, the artisan will appreciate that the above-described methodologies can be utilized in the context of CMOS fabrication which includes both NMOS and PMOS devices. Moreover, such devices can be formed through utilization of the inventive methodologies in a manner which can permit formation of transistor devices with independent gate oxide thicknesses.

[0049] In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.