Method of silicide formation by silicon pretreatment

[0002] 1. Field of the Invention

[0003] This invention relates generally to semiconductor processing, and more particularly to methods of fabricating a silicide structure.

[0004] 2. Description of the Related Art

[0005] The interconnections between circuit structures in a semiconductor device frequently require the fabrication of contact structures. Where the circuit structures are implemented in silicon, as is commonly the case for impurity regions or gate electrodes, the interfaces between such circuit structures and the contacts typically exhibit relatively high series sheet resistances. The resistances can lead to undesirably high power consumption and lower circuit performance in integrated circuits. One method in use for years to reduce the series resistance of these types of structural interfaces involves the fabrication of metal-silicide layers on sources and drains, and on gate electrodes where polysilicon is the material of choice. Self-aligned silicidation (“salicidation”) is perhaps the most common application of this method.

[0006] In conventional salicidation, a metal capable of reacting with silicon, such as titanium or cobalt, is deposited on the gate, the sidewall spacers, if any, and the impurity or source/drain regions. A one or two step anneal is performed to react the metal with the polysilicon of the gate and the silicon of the source and drain regions to form silicide. Following the anneal, an etch is performed to remove any unreacted metal.

[0007] The improvements in sheet resistance due to silicidation are dependent upon the quality of the silicide film. Film quality is, in-turn, largely a function of film geometry. Wider and thicker silicide films generally have lower resistance. Moreover, wider silicide films lessen the chances that a misaligned contact structure will fail to make contact directly with the underlying silicon or polysilicon. Titanium silicide reactions tend to be self-limiting in the vertical direction. Thus, titanium-silicide films often form to a shallower depth in a silicon substrate than desired. Lateral titanium silicide growth on polysilicon gates is similarly limited. In many cases, a titanium silicide film will only form on two thirds of the width of a poly gate. Cobalt exhibits fewer growth kinetics limitations than titanium. With either material, higher anneal temperatures can lessen the growth kinetics limitations, but at a cost in terms of thermal budget consumption. Furthermore, higher temperatures can cause localized deep silicide penetration that can lead to pn junction penetration.

[0008] One limitation on growth kinetics is thought to arise from the topography of the silicon-to-refractory metal interface. If the surface area of the underlying silicon or polysilicon structure could be increased, the silicide reaction rate should increase and result in more extensive silicide films.

[0009] The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.

[0010] In accordance with one aspect of the present invention, a method of fabricating a silicide film is provided that includes providing a silicon surface and etching the silicon surface at between isotropic and anisotropic etching conditions to define a plurality of oblique surfaces thereon and thereby increase the surface area of the silicon surface. A silicide-forming material is deposited on the plurality of oblique surfaces and the silicon surface is heated to react the silicide-forming material therewith and form silicide.

[0011] In accordance with another aspect of the present invention, a method of fabricating a circuit device is provided that includes providing a silicon surface, forming a gate electrode stack on the substrate and forming sidewall spacers adjacent to the gate electrode stack. The silicon surface is etched at between isotropic and anisotropic etching conditions to define a plurality of oblique surfaces thereon and thereby increase the surface area of the silicon surface. A silicide-forming material is deposited on the plurality of oblique surfaces and the silicon surface is heated to react the silicide-forming material therewith and form silicide.

[0012] In accordance with another aspect of the present invention, a method of fabricating a circuit device is provided that includes providing a silicon surface, forming a gate electrode stack on the silicon surface and forming a first pair of sidewall spacers adjacent to the gate electrode stack. A second pair of sidewall spacers is formed adjacent to the first pair of sidewall spacers. The silicon surface is etched at between isotropic and anisotropic etching conditions to define a plurality of oblique surfaces thereon and thereby increase the surface area of the silicon surface. A silicide-forming material is deposited on the plurality of oblique surfaces and the silicon surface is heated to react the silicide-forming material therewith and form silicide.

[0013] The foregoing and other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:

[0014] FIG. 1 is a cross-sectional view of an exemplary embodiment of a transistor device fabricated on a semiconductor substrate in accordance with the present invention;

[0015] FIG. 2 is a cross-sectional view of the substrate of FIG. 1 depicting fabrication of the transistor device and pre-silicidation substrate surface roughening in accordance with the present invention;

[0016] FIG. 3 is a magnified view of a portion of FIG. 2 in accordance with the present invention; and

[0017] FIG. 4 is a cross-sectional view like FIG. 2 depicting deposition of a silicide-forming material on the substrate in accordance with the present invention.

[0018] In the drawings described below, reference numerals are generally repeated where identical elements appear in more than one figure. FIG. 1 is a cross-sectional view of an exemplary embodiment of a transistor device 10 fabricated on a semiconductor substrate 12 in accordance with the present invention. The transistor 10 includes a gate dielectric layer 14 fabricated on the substrate 12 and a gate electrode 16 fabricated on the gate dielectric layer 14. The gate electrode 16 and the gate dielectric layer 14 are bracketed by respective pairs of insulating sidewall spacers 18 and 20. Source/drain regions 22 and 24 are provided in the substrate 12. The source/drain region 22 consists of a source/drain extension region 26 and an overlapping impurity region 28. The source/drain region 24 similarly consists of a source/drain extension region 30 and an overlapping impurity region 32. Enhanced ohmic contact to the source/drain regions 22 and 24 and the gate electrode 16 is provided by a silicide layer 34. As described below, the silicide layer 34 is provided through an improved process in accordance with the present invention. Device isolation is provided by isolation structures 36.

[0019] An exemplary method for fabricating the transistor 10 including the silicide film 34 in accordance with the present invention may be understood by referring now to FIGS. 2, 3 and 4 and initially to FIGS. 2 and 3. The transistor 10 may be fabricated using well-known techniques and materials for semiconductor device fabrication. It should be understood that the transistor 10 may be implemented as a field effect transistor as shown, or, optionally as any of a myriad of other types of circuit devices that may benefit from ohmic contact improvement through salicidation. For the purpose of illustration, the process will be described in the context of a n-channel device.

[0020] The isolation structures 36 may be shallow trench isolation, field oxide, or other isolation structures. In an exemplary embodiment, the structures 36 are shallow trench isolation structures and may be composed of silicon dioxide, silicon nitride or other suitable isolation materials, and may be formed using well-known damascene etching and fill techniques.

[0021] The gate insulating or dielectric layer 14 is formed on the substrate 12 by oxidation, blanket CVD or the like. As used herein, the terms “formed on,” “disposed on” or “positioned on” should be construed to include the possibility that a given layer or structure may be formed on another given layer or structure with a third or other intervening layers or structures disposed between the two. The layer 14 is advantageously composed of suitable gate dielectric materials, such as, for example, silicon dioxide, silicon nitride, Ta₂O₅, laminates of these or the like. In an exemplary embodiment, the layer 14 is composed of silicon dioxide formed by thermal oxidation to a thickness of about 15 to 50 Å. A rapid thermal anneal (“RTA”) with an oxygen containing ambient at about 800 to 1050° C. for about 10 to 30 seconds may be used. Optionally, a furnace process may be used for about 10 to 30 minutes.

[0022] The gate electrode 16 is fabricated by initially depositing a layer of conducting material on the gate insulating layer 14 and subsequently patterning the layer into the desired shape for the gate 16 by etching. The gate electrode 16 may be composed of a variety of conducting materials, such as, for example, polysilicon, amorphous silicon, aluminum, tantalum or the like. In an exemplary embodiment, the gate electrode 16 is composed of polysilicon. Well-known techniques for applying polysilicon, such as CVD, may be used to deposit the gate electrode 16. In an exemplary embodiment, the polysilicon is deposited at or above about 625° C. to a thickness of about 750 to 2000 Å. Reactive ion etching (“RIE”), chemical plasma etching or the like may be used in conjunction with a variety of etchant species suitable for anisotropically etching polysilicon, such as, for example, CF₄/O₂. The width of the gate electrode 16 will typically be the minimum feature size available with the prevailing lithographic patterning system, although larger geometries are possible. Later implants for the source\drain regions 22 and 24 will render the gate electrode 16 conductive. S Optionally, the gate 16 may be supplied with impurities prior to etch definition.

[0023] The first set of sidewall spacers 18 is fabricated to provide an initial lateral separation between the edges of the gate electrode 16 and the later-formed source/drain extensions. Fabrication may be by oxidation of the gate sidewalls or by blanket deposition of a variety of suitable dielectric sidewall spacer materials, such as, for example, silicon nitride, silicon dioxide, silicon oxynitride or the like. In an exemplary embodiment, the spacers 18 are composed of oxide fabricated by blanket deposition using low pressure or plasma enhanced CVD to a thickness of about 100 to 300 Å followed by an anisotropic etch selective to the substrate 12 to yield the completed spacers 18. Again, the etch may be by RIE, chemical plasma etching, or other suitable anisotropic etching techniques utilizing a chemistry suitable for anisotropically etching oxide, such as CF₄.

[0024] The source/drain regions 22 and 24 may be established by ion implantation or diffusion, and may be single or multi-graded as desired. In the illustrated embodiment, the source/drain regions 22 and 24 are multi-graded and established by ion implantation. Initially, an implant is performed to establish the source/drain extensions 26 and 30 self-aligned to the gate electrode 16. A variety of n-type impurity species 37 may be used, such as, for example, arsenic, phosphorus or the like. In an exemplary embodiment, arsenic may be implanted with an energy of about 5 to 30 keV and a dosage of about 5E14 to 3E15 cm⁻². The implant may be on or off-axis as desired. The relatively low implant energy establishes initially shallow junctions for the extensions 26 and 30.

[0025] The sidewall spacers 20 are fabricated in anticipation of an additional source/drain implant. Again, oxidation formation or blanket deposition of a variety of suitable dielectric sidewall spacer materials, such as, for example, silicon nitride, silicon dioxide, silicon oxynitride or the like. In an exemplary embodiment, the spacers 20 are composed of silicon nitride and may be fabricated by blanket deposition using low pressure or plasma enhanced CVD to a thickness of about 100 to 1500 Å followed by an anisotropic etch selective to the substrate 12 to yield the completed spacers 20. Again, the etch may be by RIE, chemical plasma etching, or other suitable anisotropic etching techniques utilizing a chemistry suitable for anisotropically etching silicon nitride, such as CF₄/O₂.

[0026] A second implant is performed to form the overlapping impurity regions 28 and 32 of the source/drain regions 22 and 24 using a n-type dopant specie 37 of the type described above. In an exemplary embodiment, arsenic is implanted with a dosage of about 1E15 to 1E16 cm⁻²and an energy of about 10 to 40 keV. The implant may again be on or off-axis. Activation of the source/drain regions 22 and 24 may be by RTA at about 900 to 1100° C. for about 10 to 60 seconds.

[0027] Prior to salicidation, the upper surface 38 of the substrate 12 and the upper surface 40 of the gate electrode 16 undergo a pretreatment process. The goal of the pretreatment is to roughen the upper surfaces 38 and 40 so that their respective surface areas are increased beyond that ordinarily provided through conventional salicidation. As shown in FIG. 3, which is a magnified view of a small portion of FIG. 2 circumscribed generally by the dashed oval 42, the upper surface 38 is roughened so that the orderly lattice structure of the substrate 12 is disrupted down to a depth D and an average peak-to-trough height H. The average peak-to-trough height H is the average height H between the peaks 44 and troughs 46 for the surface topography. The regions between adjacent peaks 44 define a plurality of oblique surfaces 47. The values for the depth of roughening and the average peak-to-trough height H are largely matters of design discretion. In an exemplary embodiment, the depth D is about 200 Å and the average peak-to-trough height H is about 300 Å.

[0028] The surface 38 is advantageously roughened by performing a plasma etch. In an exemplary embodiment, a fluorocarbon etch specie, such as, for example, CF₄, CHF₃, C₃F₈, combinations of these or the like are used to bombard the surface 38 in a plasma ambient. The etch parameters are tailored to attack the surface 38 directionally. Purely isotropic or anisotropic etching will generally yield relatively smooth surfaces. Etching somewhere between isotropic and anisotropic conditions will yield a relatively rougher surface. Implant damage in the source/drain regions 22 and 24 and the grain structure of the polysilicon gate 16 will facilitate the roughening. Accordingly, the plasma etch is advantageously performed at conditions favoring anisotropic but not completely anisotropic etching to provide a better surface roughness, that is, larger oblique surfaces 47 and an average peak-to-trough height H than a purely anisotropic etch. The substrate 12 may be biased if desired although it is anticipated that a little or no substrate bias may be used. An exemplary etch treatment process is given by the following table:

[0029] The helium and oxygen are included primarily for backside cooling of the substrate 12. The oxygen further serves to scavenge hydrogen that may be present in the etch chamber.

[0030] Referring now to FIG. 4, a metal layer 48 is blanket deposited on the substrate 12. The metal layer 48 may be composed of a cobalt-containing material, such as relatively pure cobalt or cobalt combined with a small amount of another constituent or constituents, such as platinum or the like. Optionally, the layer 48 may be composed of other metallic materials suitable for silicide formation, such as, for example, platinum, palladium, nickel, tungsten, tantalum, molybdenum or the like. In an exemplary embodiment, the layer 48 is composed of relatively pure cobalt and may be deposited by physical vapor deposition (“PVD”) to a thickness of about 50 to 300 Å.

[0031] The substrate 12 and the metal layer 48 are heated to initiate a silicide-forming reaction. The heating step may be performed at about 400 to 600° C. for about 30 to 120 seconds in an RTA with an inert ambient of argon or nitrogen. This first heating step establishes the silicide layer 34 on the source/drain regions 22 and 24 and the gate electrode 16. As the silicide reaction is consumptive of silicon and polysilicon, the layer 34 partially invades the source/drain regions 22 and 24 and the gate electrode 16 as shown in FIG. 1. The silicide reaction will not occur at the gate 16 where the gate 16 is composed of a material other than amorphous or polycrystalline silicon.

[0032] Any unreacted metal remaining after the silicide reaction is removed by wet etching. For example, a HCl-peroxide dip with about a 3:1 ratio by volume, or a H₂SO₄-peroxide dip with about a 3:1 ratio by volume may be used.

[0033] A second anneal is performed to transform the silicide layer 34 into a final low ohmic phase. In an exemplary embodiment wherein the silicide layer 34 is composed substantially of cobalt silicide, the second anneal step may be performed at about 600 to 900° C. for about 10 to 60 seconds in an RTA process.

[0034] The plasma pre-treatment yields a roughened silicon or polysilicon surface with a greater surface area than a conventionally processed substrate. Silicide formation is more aggressive, resulting in thicker, less resistive films.

[0035] While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.