Double layer electrode and barrier system on hemispherical grain silicon for use with high dielectric constant materials and methods for fabricating the same

[0002] This application is a divisional of U.S. patent application Ser. No. 09/386,833, filed Aug. 31, 1999, now U.S. Pat. No. 6,281,543 B1 issued Aug. 28, 2001.

[0003] 1. Field of the Invention

[0004] The present invention relates to a semiconductor memory device and method of fabricating same. More particularly, the present invention relates to capacitor fabrication techniques applicable to dynamic random access memories (“DRAMs”) utilizing high dielectric constant (“HDC”) materials with hemispherical grain (“HSG”) silicon and utilizing a double layer electrode having a useful barrier system during the fabrication of the same.

[0005] 2. State of the Art

[0006] A widely utilized DRAM (Dynamic Random Access Memory) manufacturing process utilizes MOS (Metal Oxide Semiconductor) technology to produce DRAM circuits which comprise an array of unit memory cells, each including one capacitor and one transistor, such as a field effect transistor (“FET”). In the most common circuit designs, one side of the transistor is connected to external circuit lines called the bit line and the word line, and the other side of the capacitor is connected to a reference voltage that is typically one-half the internal circuit voltage. In such memory cells, an electrical signal charge is stored in a storage node of the capacitor connected to the transistor which charges and discharges circuit lines of the capacitor.

[0007] Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. The advantages of increased miniaturization of components include: reduced-bulk electronic equipment, improved reliability by reducing the number of solder or plug connections, lower assembly and packaging costs, and improved circuit performance. In pursuit of increased miniaturization, DRAM chips have been continually redesigned to achieve ever higher degrees of integration which has reduced the size of the DRAM. However, as the dimensions of the DRAM are reduced, the occupation area of each unit memory cell of the DRAM must be reduced. This reduction in occupied area necessarily results in a reduction of the dimensions of the capacitor, which, in turn, makes it difficult to ensure required storage capacitance for transmitting a desired signal without malfunction. However, the ability to densely pack the unit memory cells while maintaining required capacitance levels is a crucial requirement of semiconductor manufacturing technologies if future generations of DRAM devices are to be successfully manufactured.

[0008] In addition to the need for smaller components, there has also been a growing demand for devices having lower power consumption. In the manufacture of transistors, these trends have led the industry to refine approaches to achieve thinner cell dielectric and conductive layers. These trends have also added to the difficulty of ensuring storage capacitance for transmitting a desired signal without malfunction.

[0009] In order to minimize such a decrease in storage capacitance caused by the reduced occupied area of the capacitor, the capacitor should have a relatively large surface area within the limited region defined on a semiconductor substrate. The drive to produce smaller DRAM circuits has given rise to a great deal of capacitor development. However, for reasons of available capacitance, reliability, and ease of fabrication, most capacitors are stacked capacitors in which the capacitor covers nearly the entire area of a cell and in which vertical portions of the capacitor contribute significantly to the total charge storage capacity. In such designs, the side of the capacitor connected to the transistor is generally called the “storage node” or “storage poly” since the material out of which is it formed is doped polysilicon, while the polysilicon layer defining the side of the capacitor connected to the reference voltage mentioned above is called the “cell poly.”

[0010] One method used for increasing the surface area of a capacitor involves forming rough or irregular storage node or electrode surfaces. Commonly owned U.S. Pat. Nos. 5,494,841, 5,407,534, 5,340,765, 5,340,763, 5,338,700, hereby incorporated herein by reference, each teach forming a rough surface on the capacitor storage node by depositing a hemispherical grain polysilicon on the capacitor storage node, then blanket etching the hemispherical grain polysilicon (or similar technique), which forms a roughened layer of polysilicon that increases the overall surface area in a given unit area over a normally smooth surface. With the increased surface area caused by the roughened surface, a higher storage capacitance can be achieved.

[0011] Another method of increasing the capacitance capability of a capacitor is through the use of high dielectric constant materials. The “dielectric constant” is a value characteristic of a material which is proportional to the amount of charge that can be stored in the material when it is interposed between two electrodes. HDC materials generally have dielectric constant values greater than 50 at the normal semiconductor device operating temperatures. High dielectric constant materials which can be used in capacitor fabrication include perovskite, Ba_xSr_(z-x)TiO₃[“BST”], Sr_(z-x)TiO₃[“ST”], BaTiO₃, SrTiO₃, PbTiO₃, Pb(Zr,Ti)O₃[“PZT”], (Pb,La,Zr,Ti)O₃[“PLZT”], (Pb,La)TiO₃[“PLT”], KNO₃, and LiNbO₃. Unfortunately, most high dielectric constant materials are incompatible with existing processes and cannot be simply deposited on a polysilicon electrode as are presently utilized dielectric materials, such as Si₃N₄, SiO₂, and Si₃N₄/SiO₂composite layers. The incompatibility is a result of the O₂-rich ambient atmosphere present during high dielectric constant material deposition or during annealing steps. The O₂oxidizes portions of the material used for the storage node plate. Thus, barrier layers must be used to prevent oxidation. U.S. Pat. No. 5,381,302, issued Jan. 10, 1995 to Sandhu et al., teaches methods for fabricating capacitors compatible with high dielectric constant materials wherein a storage node electrode is provided with a barrier layer, such as titanium nitride, which prohibits diffusion of atoms.

[0012] Various metals and metallic compounds, and typically noble metals, such as platinum (“Pt”), and conductive oxides, such as ruthenium dioxide (“RuO₂”), have been proposed as the electrodes for use with HDC materials. However, there are several problems with the materials in standard thin film applications. For example, platinum, which is unreactive with respect to the HDC material, is difficult to use as an electrode, because platinum generally allows oxygen to diffuse through it, which renders neighboring materials susceptible to oxidization. Additionally, platinum also does not normally stick very well to traditional dielectrics, such as silicon dioxide or silicon nitride, and platinum can rapidly transform into platinum silicide at low temperatures. Thus, a tantalum or a titanium nitride layer has been suggested as an adhesion layer under the platinum electrode. However, during the deposition or annealing of the HDC material, oxygen can diffuse through the platinum and oxidize the adhesion layer and make the adhesion layer less conductive. Further, the substrate, such as a silicon-containing material, can become undesirably oxidized during the deposition of the HDC material when a platinum electrode is used.

[0013] Conductive oxides, such as ruthenium dioxide, may also exhibit problems in standard thin film structures. For example, the electrical properties of the structures formed using these oxides are usually inferior to those formed using platinum. Many thin film applications require small leakage current density in addition to a large capacitance per unit area. The leakage current is sensitive to many variables such as thickness, structure, electrode geometry, and material composition. For example, the leakage current of the HDC material, lead zirconium titanate (PZT), using ruthenium dioxide electrodes is several orders of magnitude larger than the leakage current of PZT using platinum electrodes.

[0014] U.S. Pat. No. 5,696,018, entitled Method of Forming Conductive Noble Metal Insulator Alloy Barrier Layer for High Dielectric Constant Material Electrodes, issued Dec. 9, 1997 to Summerfelt et al. (“the '018 patent”), discloses a barrier layer in conjunction with an HDC material electrode. The '018 patent discloses the use of a noble metal insulator alloy barrier to inhibit diffusion of oxygen to an underlying oxidizable layer during the formation of the HDC layer.

[0015] Therefore, it would be advantageous to develop improved methods and apparatus of a HDC capacitor having the properties of high surface area and which prevents oxidization of the material used for the storage node plate, while using inexpensive, commercially available, widely practiced semiconductor device fabrication techniques and equipment without requiring complex processing steps.

[0016] The present invention relates to a method of forming a high surface area capacitor, such as is generally used in DRAMs. According to one embodiment of the present invention, a high surface area capacitor comprises a double metal layer, comprising an electrode metal and barrier material, deposited on hemispherical grain silicon, wherein a HDC material is deposited over the double metal layer. The high surface area capacitor is complete with an upper cell plate electrode deposited over the HDC material.

[0017] The double metal layer preferably comprises a noble metal, such as platinum or palladium, for the electrode metal and an oxidizable metal, such as ruthenium, iridium, or molybdenum, for the barrier metal. Most preferably, the metal combination for the double metal layer electrode is selected from the pairs of platinum/ruthenium, platinum/iridium, platinum/molybdenum, palladium/ruthenium, and palladium/molybdenum. The noble metal, such as platinum metal, alone would normally allow oxygen to diffuse into and oxidize any adhesion layer (making the adhesion layer less conductive) and/or undesirably oxidize any silicon-containing material during the deposition of the HDC material. Thus, the barrier metal is used to form a conducting oxide layer or other conductive layer which substantially stops the oxygen diffusion.

[0018] HSG silicon provides an enhanced surface roughness that boosts cell capacitance. The HDC material, preferably BST or the like, is also used to boost cell capacitance. There are several advantages to using the combination of HSG silicon with a high dielectric constant material such as BST. First, the use of HSG silicon effectively doubles the capacitance value for a given area. Second, HDC materials, such as BST, have K constant values about twice that of commonly used dielectrics, such as tantalum oxide. Thus, the combination of HSG silicon with HDC materials results in about a four-fold increase in capacitance over a capacitor utilizing the same surface area with HDC material. For example, even at a reduced size, BST has the same leakage current limitations as tantalum oxide. Thus, in a 0.25 square micron area, BST on HSG silicon provides the same capacitance level as tantalum oxide alone in a 1 square micron area. This allows a tremendous reduction in the overall area of the capacitor cell without sacrificing capacitance.

[0019] While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:

[0020] FIGS. 1-13 are side cross-sectional views of a method of forming a memory cell capacitor according to the present invention.

[0021] FIGS. 1-13 illustrate a technique for forming a high dielectric constant cell capacitor for a memory cell. It should be understood that the figures presented in conjunction with this description are not meant to be illustrative of actual cross-sectional views of any particular portion of an actual semiconductor device, but are merely idealized representations which are employed to more clearly and fully depict a process of the invention than would otherwise be possible.

[0022] FIG. 1 illustrates a cross-sectional view of an in-process intermediate structure 100 in the production of a memory cell array (i.e., a DRAM). This intermediate structure 100 comprises a substrate 102, such as a lightly doped P-type crystal silicon substrate, which has been oxidized to form thick field oxide areas 104 and exposed to implantation processes to form drain regions 106 and source regions 108 of N+ doping. Transistor gate members 112 are formed on the surface of the substrate 102, including gate members 112 residing on a substrate active area 110 spanned between the drain regions 106 and the source regions 108 and gate members 112 residing on the thick field oxide areas 104. The transistor gate members 112 each comprise a lower buffer layer 114, preferably made of silicon dioxide, separating a gate conducting layer or wordline 116 of the transistor gate member 112 from the substrate 102. Transistor insulating spacer members 118, preferably made of silicon nitride, are formed on either side of each transistor gate member 112. A cap insulator 122, also preferably made of silicon nitride, is formed on the top of each transistor gate member 112. A first barrier layer 124 (preferably made of tetraethyl orthosilicate—TEOS or the like) is applied over the transistor gate members 112 and the substrate 102. A second barrier layer 126 (preferably made of borophosphosilicate glass—BPSG, phosphosilicate glass—PSG, borosilicate glass—BSG, or the like) is deposited over the first barrier layer 124. The second barrier layer 126 may be optionally planarized, if necessary, preferably using an abrasive process, such as chemical mechanical planarization (CMP).

[0023] It is, of course, understood that a single barrier layer could be employed. However, a typical barrier configuration is a layer of TEOS over the transistor gate members 112 and the substrate 102 followed by a BPSG layer over the TEOS layer. The TEOS layer is applied to prevent dopant migration. The BPSG layer contains boron and phosphorus which can migrate into the source and drain regions formed on the substrate during inherent device fabrication heating steps. This migration of boron and phosphorus can change the dopant concentrations in the source and drain regions which can adversely affect the transistor performance.

[0024] A first resist layer 128 is patterned, as shown in FIG. 2, and the second barrier layer 126 and the first barrier layer 124 are etched to expose the drain regions 106 in the substrate 102 forming vias 132, as shown in FIG. 3. Any remaining first resist layer 128 is then stripped, as shown in FIG. 4, and a layer of conductive polysilicon material 134 is applied over the structure to fill the vias 132, as shown in FIG. 5. The conductive polysilicon material 134 is etched such that it is recessed within the vias 132, as shown in FIG. 6. This may be achieved with CMP, wet etch, dry etch, or a combination thereof.

[0025] An HSG polysilicon layer is formed by applying a layer of amorphous silicon 138 over the layer of conductive polysilicon material 134 and over the exposed second barrier layer 126, as shown in FIG. 7. A polysilicon seed crystal layer is applied at a temperature of at least 500° C., preferably between about 550 and 600° C., and a pressure of between about 10⁻⁷and 10⁻²Torr. The polysilicon seed crystal layer is then annealed at a temperature of at least 500° C., preferably between about 550 and 700° C., and a pressure between about 10⁻⁷and 10⁻²Torr. The annealing causes the amorphous silicon to nucleate into a polysilicon material around the polysilicon seed crystal to form the HSG polysilicon layer 142, as shown in FIG. 8. An optional etch step may be performed at this point to further roughen the HSG polysilicon layer 142.

[0026] A double metal layer 144 is deposited over the HSG polysilicon layer 142, as shown in FIG. 9. As shown in FIG. 10 (inset 10 of FIG. 9), the double metal layer 144 comprises a barrier metal layer 146 deposited over the HSG polysilicon layer 142 and an electrode metal layer 148, preferably platinum or palladium, deposited over the barrier metal layer 146. The barrier metal layer 146 is preferably deposited to a depth of between 40 and 300 Å and is an oxidizable metal which is conductive after oxidation and provides a barrier to oxygen diffusion after oxidation, such as ruthenium (oxidizes to ruthenium dioxide (RuO₂)), iridium (oxidizes to iridium dioxide (IrO₂)), molybdenum (oxidizes to molybdenum dioxide (MoO₂)), rhodium (oxidizes to rhodium dioxide (RhO₂)), or platinum (oxidizes to platinum dioxide (PtO₂)). The barrier metal layer 146 may also be a material which is conductive after thermal degradation to provide a barrier to oxygen diffusion, such as tungsten nitride (WN_x(x=1 to 4)) which degrades to a tungsten barrier layer. The barrier metal layer 146 may be partially or completely converted to its oxide or degraded form either during or after deposition, or during a subsequent processing step.

[0027] Additionally, a platinum layer may be used as the barrier metal layer 146, so long as the platinum is oxidized into platinum dioxide prior to the subsequent deposition of an HDC layer.

[0028] The electrode metal layer 148, preferably platinum, rhodium, ruthenium, or palladium, is deposited over the barrier metal layer 146 to a depth of between about 40 and 300 Å. The electrode metal layer 148 is preferably deposited by chemical vapor deposition or metal-organic chemical vapor deposition, as known in the art. The electrode metal layer 148 may also be deposited using e-beam evaporation or DC sputter deposition in an argon atmosphere at a pressure of approximately 5 millitorr using a target of the selected electrode metal material with the temperature of the substrate 102 held at about 325° C. When platinum is used as the electrode metal layer 148, it is preferable to perform the deposition at a temperature of between about 300 and 600° C., as the micro-structure in thermal stress of the platinum layer is generally improved at such a temperature range.

[0029] The double metal layer 144 is etched or abraded such that the polysilicon material layer 134 within each via 132 is electrically isolated from one another, as shown in FIG. 11. The double metal layer 144 may be preferably etched by dry etch in a low-pressure, high-density plasma RIE reactor or may be abraded with a chemical mechanical planarization technique, as known in the art.

[0030] Generally, the oxidation rate of barrier metal layer 146 is generally much more rapid at the beginning of the HDC material deposition process than later. Thus, it is usually beneficial to perform partial oxidation in order to let the barrier metal layer 146 oxidize to less strenuous oxidizing conditions before HDC material deposition. For example, if the metal-organic chemical vapor deposition (MOCVD) of the HDC material occurs at about 650° C. in an oxygen-containing atmosphere at a pressure of about 1 torr for about 3 minutes, then the barrier metal layer 146 should be annealed at about 600° C. in an oxygen-containing atmosphere at a pressure of about 1 torr for about 20 minutes before HDC material deposition. The lower temperature generally has some advantage in that it slows down the oxidation rate of the barrier metal layer 146 and allows double metal layer 144 more time to “relax” than if the oxidation is performed at full deposition temperature. Another benefit of this oxidation anneal process is that the electrode metal layer 148 can rearrange to further round any corners after being etched or abraded, which helps to dampen or eliminate intense, structure damaging electric fields which can be generated at sharp edge surfaces of the electrode metal layer 148 during the operation of the capacitor.

[0031] An HDC material layer 152, preferably BST or ST, is deposited over the double metal layer 144 and exposed portions of the second barrier layer 126, preferably by a MOCVD technique, as shown in FIG. 12. As previously mentioned, the deposition of the HDC material layer 152 generally requires conditions highly conducive to oxidation; however, the electrode metal layer 148 will remain unoxidized and barrier metal layer 146 (see FIG. 10) will substantially inhibit oxygen from diffusing into underlying materials, such as the conductive polysilicon material 134.

[0032] If the HDC material layer 152 used is barium strontium titanate, the HDC material layer 152 will be of a thickness ranging from 200 to 350 angstroms. Preferably, the entire film stack of the barrier metal layer 146, the electrode metal layer 148, and the HDC material layer 152 will have a thickness not exceeding 1,000 angstroms. The thin layer of barrier metal layer 146 and the electrode metal layer 148 are designed to preserve the advantages of the rough texture of the HSG polysilicon layer 142 therebelow, as it is advantageous to keep the HDC material layer 152 as close to the rough texture of the HSG polysilicon layer 142 as possible.

[0033] The capacitors are completed by depositing an upper cell plate electrode 154, preferably platinum, over the HDC material layer 152, as shown in FIG. 13. After subsequent processing steps, the capacitor structures may be annealed to improve the capacitor properties. However, since the present invention is a HSG capacitor having the previously described roughened layer of polysilicon, the annealing should be limited so that the HSG roughened layer characteristic is not destroyed.

[0034] Having thus described in detail preferred embodiments of the present invention, it is to be understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description as many apparent variations thereof are possible without departing from the spirit or scope thereof.