Method for manufacturing dual voltage flash integrated circuit

[0002] The present invention relates generally to the manufacturing of dual voltage flash integrated circuits and more particularly to a method in which the mask steps may be reduced and conventional processing used.

[0003] Flash electrically-eraseable programmable and read-only memories (flash EEPROMs) are a class of non-volatile memory devices that are programmed by hot electron injection and erased by Fowler-Nordheim tunneling. Flash EEPROMs are read/programmed byte-by-byte or word-by-word, and are erased globally (full chip erase) or partially by a particular portion of the overall array (sector erase). These integrated circuits generally require dual voltages for operation and have peripheral semiconductor devices along with the flash memory cell which use these dual voltages.

[0004] Each memory cell is formed on a semiconductor substrate (i.e., a silicon die or chip) having a heavily doped drain region and a source region embedded in the semiconductor substrate. The source region further contains a lightly doped deeply diffused region and a more heavily doped shallow diffused region embedded in the substrate. A channel region separates the drain region and the source region. The memory cell further includes a multilayer structure, commonly referred to as a “stacked gate” structure by which the charge indicative of the state of the flash EEPROM is controlled.

[0005] In the past, in manufacturing a dual voltage flash EEPROM, after active and floating gate polysilicon areas are formed, alternating layers of oxide-nitride-oxide (ONO) dielectric material was thermally grown on the polysilicon and the silicon substrate. A photoresist mask (mask) was then introduced to selectively allow removal of the top oxide and nitride layers of the ONO, followed by an oxide stripping etch to remove the bottom oxide of the ONO at the peripheral region of the integrated circuit.

[0006] An oxide (for high voltage devices) was thermally grown (a gate oxidation I) after removal of the mask.

[0007] Subsequently, a number of masks had to be used for the low voltage (LV) well, field, channel, and voltage threshold (V_t) implant. A first is used for the LV N-well implant, a second for an LV P-field (Pfld) implant, a third mask for an LV thin gate (first voltage) P-channel V_timplant, a fourth mask for an LV thick-gate (second voltage) P-channel V_timplant, a fifth mask for an LV thin-gate (first voltage) N-channel V_timplant, and a sixth mask for an LV thick-gate (second voltage) N-channel V_timplant.

[0008] A further mask is then introduced for the LV thick gate oxidation creation, and oxide strip is implemented to remove the gate oxidation I at the LV region. A gate oxide then was thermally grown (a gate oxidation II) after removal of the mask. Finally, another mask was used for the LV thin gate oxide creation and a further oxide strip.

[0009] Finally, a further polysilicon is deposited and the remaining conventional steps of the manufacturing process for the flash EEPROM are performed.

[0010] The above steps are problematic because of the number of masks required and incompatability with individual processes used by different foundries. A solution which would allow for a simplified more universal process has long been sought, but has equally long eluded those skilled in the art.

[0011] The present invention provides A method is provided for manufacturing a multiple voltage flash memory integrated circuit structure on a semiconductor substrate having a plurality of shallow trench isolations and a floating gate structure. A first dielectric layer is formed and a portion removed to expose regions of the semiconductor substrate for first and second low voltage devices. A second dielectric layer is formed over the first dielectric layer and the semiconductor substrate and a portion removed to expose a region of the semiconductor substrate for the second low voltage device. A third dielectric layer is formed over the second dielectric layer to form: a floating gate including the first, second, and third dielectric layers; a first voltage device including the first, second, and third dielectric layers; a second voltage device including the second and third dielectric layers; and a third voltage device including the third dielectric layer. This method is simplified over the prior art and uses individual processes which are conventional and well-known to those skilled in the art.

[0012] The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.

[0013] FIGS. 1A through 1D shows various cross-sections of a wafer in an intermediate stage of manufacturing after deposition of alternating dielectric layers;

[0014] FIGS. 2A through 2D shows various cross-sections of the wafer after the deposition and processing of a photoresist layer and removal of a portion of the alternating dielectric materials;

[0015] FIGS. 3A through 3D shows various cross-sections of the wafer after deposition and processing of a photoresist layer and implantation;

[0016] FIGS. 4A through 4D shows various cross-sections of the wafer after deposition and processing of a photoresist layer and implantation;

[0017] FIGS. 5A through 5D shows various cross-sections of the wafer after deposition of a dielectric layer, deposition and processing of a photoresist layer, and implantation;

[0018] FIGS. 6A through 6D shows various cross-sections of the wafer after deposition and processing of a photoresist layer and implantation;

[0019] FIGS. 7A through 7D shows various cross-sections of the wafer after deposition and processing of a photoresist layer and implantation;

[0020] FIGS. 8A through 8D shows various cross-sections of the wafer after deposition and processing of a photoresist layer and implantation;

[0021] FIGS. 9A through 9D shows various cross-sections of the wafer after deposition and processing of a photoresist layer and removal of a dielectric layer;

[0022] FIGS. 10A through 10D shows various cross-sections of the wafer after deposition and processing of a photoresist layer and deposition of a dielectric layer;and

[0023] FIGS. 11A through 11D shows various cross-sections of the wafer after deposition of a semiconductor material.

[0024] Referring now to FIGS. 1A through 1D, therein are shown various cross-sections of a flash EEPROM integrated circuit at an intermediate stage of manufacture.

[0025] FIG. 1A shows a memory region, which upon completion of processing will contain a plurality of memory cells 11. The plurality of memory cells 11 will be formed on a semiconductor substrate 16, generally of silicon, into which shallow trench isolations 18, generally of an oxide, have been formed. The implantations for forming the channels, wells, and/or junctions of the plurality of memory cells 11 will have been completed. A gate dielectric layer, generally an oxide layer 20, has been formed over the semiconductor substrate 16 and the shallow trench isolations 18. The oxide layer 20 generally becomes a part of the oxide material of the shallow trench isolations 18. As shown, polysilicon has been deposited over the oxide layer 20 and patterned to form a plurality of polysilicon floating gates 22 and alternating layers of dielectric material, an ONO layer 24, have been deposited over the plurality of polysilicon floating gates 22 and the shallow trench isolations 18. The ONO layer 24 consists of alternating layers of oxide, nitride and oxide.

[0026] Referring now to FIG. 1B, therein is shown a portion of a peripheral region, which upon completion of processing will contain a plurality of high voltage devices 12. The implantations for forming the channels, wells, and/or junctions of the plurality of high voltage devices 12 will have been completed. In FIG. 1B and the remaining FIGs., those elements which are the same as in previous FIGS. are designated by the same numbers. Thus, FIG. 1B shows the shallow trench isolations 18 and the semiconductor substrate 16 covered by the ONO layer 24.

[0027] Referring now to FIG. 1C, therein is shown a peripheral region, which upon completion of processing will contain a plurality of first low voltage devices 13. At this stage of manufacture, the structure is the same as FIG. 1B.

[0028] Referring now to FIG. 1D, therein is shown a portion of the peripheral region, which upon completion of processing will contain a plurality of second low voltage devices 14. When completed, the plurality of second low voltage devices 14 will operate at a lower voltage than the plurality of first low voltage devices 13.

[0029] The structures of FIGS. 1A through 1D are formed by conventional processes well known to those skilled in the art.

[0030] Referring now to FIG. 2A, therein is shown the structure of FIG. 1A having a photoresist mask or an ONO mask 26 deposited over the ONO layer 24.

[0031] Referring now to FIG. 2B, therein is shown the structure of FIG. 1B after removal of the oxide and nitride layers from the ONO layer 24 to leave a bottom oxide layer 28 which is integral with the shallow trench isolations 18 and the semiconductor substrate 16.

[0032] Referring now to FIG. 2C, therein is shown the structure of FIG. 1C after the same removal process of FIG. 2B to show the bottom oxide layer 28 of the ONO layer 24 integral with the shallow trench isolations 18 and the semiconductor substrate 16.

[0033] Referring now to FIG. 2D, therein is shown the structure of FIG. 1D after the same removal process of FIG. 2B to show the bottom oxide layer 28 of the ONO layer 24 integral with the shallow trench isolations 18 and the semiconductor substrate 16.

[0034] Referring now to FIG. 3A, therein is shown the structure of FIG. 2A having the ONO mask 26 removed and an N-well mask 30 deposited over the ONO layer 24.

[0035] Referring now to FIG. 3B, therein is shown the structure of FIG. 2B having the N-well mask 30 deposited on the bottom oxide layer 28.

[0036] Referring now to FIG. 3C, therein is shown the structure of FIG. 2C having the N-well mask 30 deposited, patterned, and developed to form a mask opening. After an N-well implantation 32 through the bottom oxide layer 28 into the semiconductor substrate 16 an oxide etch has been performed to remove the bottom oxide layer 28 to expose the semiconductor substrate 16.

[0037] Referring now to FIG. 3D, therein is shown the structure of FIG. 2D having the N-well mask 30 deposited, patterned, and developed to form a mask opening. After the N-well implantation 32 through the bottom oxide layer 28 into the semiconductor substrate 16, an oxide etch has been performed to remove the bottom oxide layer 28 to expose the semiconductor substrate 16.

[0038] Referring now to FIG. 4A, therein is shown the structure of FIG. 3A having the N-well mask 30 removed and a P-well mask 34 deposited over the ONO layer 24.

[0039] Referring now to FIG. 4B, therein is shown the structure of FIG. 3B having the P-well mask 34 deposited on the bottom oxide layer 28.

[0040] Referring now to FIG. 4C, therein is shown the structure of FIG. 3C having the P-well mask 34 deposited, patterned, and developed to form a mask opening. After a P-well implantation 36 through the bottom oxide layer 28 into the semiconductor substrate 16, an oxide etch has been performed to remove the bottom oxide layer 28 to expose the semiconductor substrate 16.

[0041] Referring now to FIG. 4D, therein is shown the structure of FIG. 3D having the P-well mask 34 deposited, patterned, and developed to form a mask opening. After an N-well implantation 37 through the bottom oxide layer 28 into the semiconductor substrate 16, an oxide etch has been performed to remove the bottom oxide layer 28 to expose the semiconductor substrate 16.

[0042] As would be understood by those skilled in the art, both the first and second low voltage devices 13 and 14 will contain N-wells and P-wells so the above FIGS. 3C through 3D and FIGS. 4C through 4D show representations of implantations through openings in the respective masks 30 and 34 which actually expose dfferent portions of the semiconductor substrate 16 so only one type of well is implanted in each portion. Further, the N-wells and P-wells may be implanted in any order.

[0043] Referring now to FIG. 5A, therein is shown the structure of FIG. 4A having a first gate oxide layer 38 deposited over the ONO layer 24 and a first voltage P-channel V_tmask 40 deposited over the first gate oxide layer 38.

[0044] Referring now to FIG. 5B, therein is shown the structure of FIG. 4B having the first gate oxide layer 38 deposited over the bottom oxide layer 28 and the first voltage P-channel V_tmask 40 deposited over the first gate oxide layer 38. The first gate oxide layer 38 in the one mode is grown to a thickness of 80 Å.

[0045] Referring now to FIG. 5C, therein is shown the structure of FIG. 4C having the first voltage P-channel V_tmask 40 deposited, patterned, and developed to form a mask opening. A P-channel implantation 42 for the threshold voltage implantation is perfomed through the openings in the first voltage P-channel V_tmask 40 and through the first gate oxide layer 38 into the semiconductor substrate 16.

[0046] Referring now to FIG. 5D, therein is shown the structure of FIG. 4D having the first gate oxide layer 38 deposited over the bottom oxide layer 28 and the first voltage P-channel V_tmask 40 deposited over the first gate oxide layer 38.

[0047] Referring now to FIG. 6A, therein is shown the structure of FIG. 5A having first voltage N-channel V_tmask 44 deposited over the first gate oxide layer 38.

[0048] Referring now to FIG. 6B, therein is shown the structure of FIG. 5B having the first voltage N-channel V_tmask 44 deposited over the first gate oxide layer 38.

[0049] Referring now to FIG. 6C, therein is shown the structure of FIG. 5C having the first voltage N-channel V_tmask 44 deposited, patterned, and developed to form a mask opening. An N-channel V_timplantation 46 for the threshold voltage implantation is perfomed through the openings in the first voltage N-channel V_tmask 44 and through the first gate oxide layer 38 into the semiconductor substrate 16.

[0050] Referring now to FIG. 6D, therein is shown the structure of FIG. 5D having the first voltage N-channel V_tmask 44 deposited over the first gate oxide layer 38.

[0051] As would be understood by those skilled in the art, the plurality of first low voltage devices 13 will contain P-channels for the N-wells and and N-channels for the P-wells so the above FIGS. 5C through 5D and FIGS. 6C through 6D show representations of implantations through openings in the respective masks 40 and 44 which actually expose dfferent portions of the semiconductor substrate 16 so only one type of channel of the opposite conductivity is implanted in each portion of the plurality of first low voltage devices 13. Further, the N-channels and P-channels may be implanted in any order.

[0052] Referring now to FIG. 7A, therein is shown the structure of FIG. 6A having the first voltage N-channel V_tmask 44 removed and the first gate oxide layer 38 deposited over the ONO layer 24 and a second voltage P-channel V_tmask 48 deposited over the first gate oxide layer 38.

[0053] Referring now to FIG. 7B, therein is shown the structure of FIG. 6B having the first voltage N-channel V_tmask 44 removed and the first gate oxide layer 38 deposited over the bottom oxide layer 28 and the second voltage P-channel V_tmask 48 deposited over the first gate oxide layer 38.

[0054] Referring now to FIG. 7C, therein is shown the structure of FIG. 6C having the first voltage N-channel V_tmask 44 removed and the first gate oxide layer 38 and the second voltage P-channel V_tmask 48 deposited over the first gate oxide layer 38.

[0055] Referring now to FIG. 7D, therein is shown the structure of FIG. 6D having the first voltage N-channel V_tmask 44 removed and the second voltage P-channel V_tmask 48 deposited, patterned, and developed to form a mask opening. A P-channel implantation 50 for the threshold voltage implantation is perfomed through the openings in the second voltage P-channel V_tmask 48 and through the first gate oxide layer 38 into the semiconductor substrate 16.

[0056] Referring now to FIG. 8A, therein is shown the structure of FIG. 7A having the second voltage P-channel V_tmask 48 removed and a second voltage N-channel V_tmask 52 deposited over the first gate oxide layer 38.

[0057] Referring now to FIG. 8B, therein is shown the structure of FIG. 7B having the second voltage P-channel V_tmask 48 removed and the second voltage N-channel V_tmask 52 deposited over the first gate oxide layer 38.

[0058] Referring now to FIG. 8C, therein is shown the structure of FIG. 7C having the second voltage P-channel V_tmask 48 removed and the second voltage N-channel V_tmask 52 deposited over the first gate oxide layer 38.

[0059] Referring now to FIG. 8D, therein is shown the structure of FIG. 7D having the second voltage N-channel V_tmask 52 deposited, patterned, and developed to form a mask opening. An N-channel V_timplantation 54 for the threshold voltage implantation is perfomed through the openings in the second voltage N-channel V_tmask 52 and through the first gate oxide layer 38 into the semiconductor substrate 16. Then, an oxide etch is performed to remove the first gate oxide layer 38 to expose the semiconductor substrate 16.

[0060] As would be understood by those skilled in the art, the plurality of second low voltage devices 14 will contain P-channels for the N-wells and and N-channels for the P-wells so the above FIGS. 7C through 7D and FIGS. 8C through 8D show representations of implantations through openings in the respective masks 48 and 52 which actually expose dfferent portions of the semiconductor substrate 16 so only one type of channel of the opposite conductivity is implanted in each portion of the plurality of second low voltage devices 14. Further, the N-channels and P-channels may be implanted in any order.

[0061] Referring now to FIG. 9A, therein is shown the structure of FIG. 8A unchanged because the second voltage N-channel V_tmask 52 protects the structure from a removal operation which has been completed as explaimed below.

[0062] Referring now to FIG. 9B, therein is shown the structure of FIG. 8B unchanged because the second voltage N-channel V_tmask 52 protects the structure from a removal operation which has been completed as explaimed below.

[0063] Referring now to FIG. 9C, therein is shown the structure of FIG. 8C unchanged because the second voltage N-channel V_tmask 52 protects the structure from a removal operation which has been completed as explaimed below.

[0064] Referring now to FIG. 9D, therein is shown the structure of FIG. 8D having the first gate oxide layer 38 removed by a process, such as etching, to expose the semiconductor substrate 16 and the shallow trench isolations 18.

[0065] Referring now to FIG. 10A, therein is shown the structure of FIG. 9A after removal of the second voltage N-channel V_tmask 52, and a gate oxidation II, which thermally grows a second gate oxide layer 58 on the first gate oxide layer 38.

[0066] Referring now to FIG. 10B, therein is shown the structure of FIG. 9B after removal of the second voltage N-channel V_tmask 52 and the gate oxidation II which deposits the second gate oxide layer 58 as shown in FIG. 10A.

[0067] Referring now to FIG. 10C, therein is shown the structure of FIG. 9C after removal of the second voltage N-channel V_tmask 52 and the gate oxidation II which deposits the second gate oxide layer 58 as shown in FIG. 10A.

[0068] Referring now to FIG. 10D, therein is shown the structure of FIG. 9D after the gate oxidation II, which deposits the second gate oxide layer 58 on the shallow trench isolations 18 and the semiconductor substrate 16.

[0069] After removal of the second voltage N-channel V_tmask 52, a chemical (i.e. RCA-like cleaning solution) cleaning process of 100:1 hydrogen fluoride dip is implemented prior to thermally growing an oxide, a gate oxidation III.

[0070] Referring now to FIG. 11A, therein is shown the structure of FIG. 10A having a semiconductor layer such as a polysilicon layer 60 deposited over a gate oxide 61 which consists of the ONO layer 24, the first gate oxide layer 38, and the second gate oxide layer 58 to form the plurality of memory cells 11.

[0071] Referring now to FIG. 11B, therein is shown the structure of FIG. 10B having the polysilicon layer 60 deposited over a gate oxide 62 which consist of the bottom oxide layer 28 of the ONO layer 24, the first gate oxide layer 38, and the second gate oxide layer 58 to form the plurality of high voltage devices 12.

[0072] Referring now to FIG. 11C, therein is shown the structure of FIG. 10C having the polysilicon layer 60 deposited over a gate oxide 63 which consists of the first gate oxide layer 38 and the second gate oxide layer 58 to form the plurality of first low voltage devices 13.

[0073] Referring now to FIG. 11D, therein is shown the structure of FIG. 10D having the polysilicon layer 60 deposited over the second gate oxide layer 58 to form the plurality of second low voltage devices 14.

[0074] Thus, by reference to FIGS. 11A through 11D, it may be shown that semiconductor devices have been formed having a plurality of gate thicknesses due to the layered structures 58, 61, 62, 63 for different voltages. In particular, the plurality of high voltage devices 12 is for the highest voltage, the plurality of first low voltage devices 13 is next for the next highest voltage, and finally, the plurality of second low voltage devices 14 is appropriate for the lowest voltage.

[0075] In the present invention, the manufacturing method to produce the plurality of memory cells 11, the plurality of high voltage devices 12, the plurality of first low voltage devices 13, and the plurality of second low voltage devices 14 is performed as follows:

[0076] 1. The semiconductor substrate 16 is provided with the shallow trench isolations 18 formed and the implantations for the plurality of memory cells 11 and the plurality of high voltage devices 12 performed. The plurality of polysilicon floating gates 22 is also formed for the plurality of memory cells 11.

[0077] 2. The alternating dielectric layers of the ONO layer 24 are thermally grown on the plurality of polysilicon floating gates 22 and the shallow trench isolations 18 in a core memory region which includes the plurality of memory cells 11 of FIG. 1A and also on the semiconductor substrate 16 and the shallow trench isolations 18 of a peripheral region shown in FIGS. 1B through 1D. Alternality, the ONO layer can be formed by depositing nitride and oxide films using CVD methods.

[0078] 3. The ONO mask 26 is deposited over the ONO layer 24 and is patterned and developed to expose the peripheral region for removal of the top oxide and nitride layers of the ONO layer 24 to expose the bottom oxide layer 28 as shown in FIGS. 2B through 2D.

[0079] 3. The ONO mask 26 is removed.

[0080] 4. The N-well mask 30 is deposited over the ONO layer 24 and the bottom oxide layer 28 and is patterned and developed to expose the bottom oxide layer 28 over the semiconductor substrate 16 a first selected plurality of the first and second low voltage devices 13 and 14.

[0081] 5. The N-well implantation 32 is performed using the N-well mask 30 into the first selected plurality of the first and second low voltage devices 13 and 14.

[0082] 6. An oxide strip is performed to remove the bottom oxide layer 28 from the shallow trench isolations 18 and the semiconductor substrate 16 for the first selected plurality of the first and second low voltage devices 13 and 14 which have the N-wells implanted.

[0083] 7. The N-well mask 30 is removed.

[0084] 8. The P-well mask 34 is deposited over the ONO layer 24 and the bottom oxide layer 28 and is patterned and developed to expose the bottom oxide layer 28 over the semiconductor substrate 16 a second selected plurality of the first and second low voltage devices 13 and 14.

[0085] 9. The P-well implantation 36 is performed using the P-well mask 34 into a second selected plurality of the first and second low voltage devices 13 and 14.

[0086] 10. An oxide strip is performed to remove the bottom oxide layer 28 from the shallow trench isolations 18 and the semiconductor substrate 16 for the the second selected plurality of the first and second low voltage devices 13 and 14 which have the P-wells implanted.

[0087] 11. The steps 4 through 7 leave the structure as shown in FIGS. 3A through 3D and the steps 8 through 11 leave the structure as shown in FIGS. 4A through 4D.

[0088] 12. The P-well mask 34 is removed.

[0089] 13. The first gate oxide layer 38 is thermally grown over the ONO layer 24 of memory cell 11, the bottom oxide layer 28 of high voltage devices 12, and the semiconductor substrate 16 of low voltage devices 13, 14.

[0090] 14. The first low voltage P-channel V_tmask 40 is deposited over the first gate oxide layer 38 and is patterned and developed to expose the first gate oxide layer 38 over the N-wells for the plurality of first low voltage devices 13.

[0091] 15. The P-channel V_timplantation 42 is performed using the first voltage P-channel V_tmask 40 into the the N-wells for the plurality of first low voltage devices 13.

[0092] 16. The first low voltage P-channel V_tmask 40 is removed.

[0093] 17. The first low voltage N-channel V_tmask 44 is deposited over the first gate oxide layer 38 and is patterned and developed to expose the first gate oxide layer 38 over the P-wells for the plurality of first low voltage devices 13.

[0094] 18. The N-channel V_timplantation 46 is performed using the first low voltage N-channel V_tmask 44 into the P-wells for the plurality of first low voltage devices 13.

[0095] 19. The steps 12 through 15 leave the structure as shown in FIGS. 5A through 5D and the steps 16 through 18 leave the structure as shown in FIGS. 6A through 6D.

[0096] 20. The first voltage N-channel V_tmask 44 is removed.

[0097] 21. The second low voltage P-channel V_tmask 48 is deposited over the first gate oxide layer 38 and is patterned and developed to expose the first gate oxide layer 38 over the N-wells for the plurality of second low voltage devices 14.

[0098] 22. The P-channel V_timplantation 50 is performed using the second low voltage P-channel V_tmask 48 into the the N-wells for the plurality of second low voltage devices 14.

[0099] 23. An oxide strip is performed to remove the first gate oxide layer 38 from the shallow trench isolations 18 and the semiconductor substrate 16 over the N-wells for the plurality of second low voltage devices 14.

[0100] 24. The second low voltage P-channel V_tmask 48 is removed.

[0101] 25. The second low voltage N-channel V_tmask 52 is deposited over the first gate oxide layer 38 and is patterned and developed to expose the first gate oxide layer 38 over the P-wells for the plurality of second low voltage devices 14.

[0102] 26. The N-channel V_timplantation 54 is performed using the second low voltage P-channel V_tmask 48 into the P-wells for the plurality of second low voltage devices 14.

[0103] 27. An oxide strip is performed to remove the first gate oxide layer 38 from the shallow trench isolations 18 and the semiconductor substrate 16 over the P-wells for the plurality of second low voltage devices 14.

[0104] 28. The steps 20 through 22 leave the structure as shown in FIGS. 7A through 7D and the steps 24 through 26 leave the structure as shown in FIGS. 8A through 8D.

[0105] 29. The steps 23 and 27 leave the structure as shown in FIGS. 9A through 9D.

[0106] 30. An RCA clean with 30″ at 100:1 hydrogen fluoride is implemented to remove about 20 Å of oxide in one embodiment.

[0107] 31. The second gate oxide layer 58 is deposited over the ONO layer 24, the first gate oxide layer 38, and the semiconductor substrate 16 of the memory cell 11.

[0108] 32. The polysilicon layer 60 is deposited over the second gate oxide layer 58.

[0109] In one embodiment, the first gate oxide layer 38 is deposited to a thickness of 80 Å and is cleaned to a thickness of 65 Å while the second gate oxide layer 58 is deposited to a thickness of 30 Å. The polysilicon layer 60 is deposited to a thickness of around 2,000 Å.

[0110] While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations which fall within the spirit and scope of the included claims. All matters hither-to-fore set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.