US 6,389,581 B1Grant
Optimizing repeaters positioning along interconnects
Issue Date:2002-05-14
•2 Claims
•6 Drawing Sheets
Abstract
An aspect of interconnect design for optimizing delay characteristics of interconnects. The interconnect design for delay characteristics optimization is performed using a method for optimizing repeaters positioning along interconnects. The method includes inserting repeaters in positions along a first interconnect at predetermined intervals that are related to signals transition time. The method further includes inserting repeaters in positions along a second interconnect at the predetermined intervals, the second interconnect being a neighbor of the first interconnect. The positions of repeaters along the second interconnect are offset, by a predetermined length, relative to the positions of repeaters along the first interconnect so that the repeaters positions along the second interconnect are shifted relative to the repeaters positions along the first interconnect. In one embodiment, the predetermined length is half (0.5) of the predetermined interval such that repeaters are shifted by half, wherein the interconnect delay that corresponds to the offsetting by half of the predetermined interval minimizes the interconnect delay under worst case conditions. The repeaters are inserted to decrease interconnect delay and make the interconnect delay scale linearly with an interconnect length.
Metadata
Assignee
- Silicone Graphics Inc.
Inventors
- Sudhakar Muddu
- Egino Sarto
Application Information
Application Number:US 09/388,938
Filing Date:1999-09-02
Priority Date:1999-07-16
Art Unit:7
Classifications
IPC:
G06F 1750
Patent Drawings (6 sheets)
Description
CROSS-NOTING TO PROVISIONAL APPLICATION
[0002] A claim is hereby made for the benefit under 35 U.S.C 119(e) of a U.S. provisional application serial no. 60/144,386, filed on Jul. 16, 1999, which is incorporated herein by reference.
RELATED APPLIACTIONS
[0003] This application is related to and incorporates herein by reference the following co-pending applications: U.S. patent application Ser. No. 09/276,992 titled “Interconnects Capacitive Effects Estimation,” filed Mar. 26, 1999, U.S. patent application Ser. No. 09/301,836 titled “Noise Estimation For Coupled RC Interconnects in Deep Submicron Integrated Circuits,” filed Apr. 29, 1999 and U.S. patent application Ser. No. 09/387,934 titled “Determining a Worst Case Switching Factor For Integrated Circuit Design,” filed Sep. 1, 1999, all of which are assigned to the assignee of the present application.
FIELD OF THE INVENTION
[0004] This application relates to integrated circuit (IC) design and, specifically, to interconnects propagation delay analysis in high speed, high density IC design.
BACKGROUND OF THE INVENTION
[0005] Forming interconnections in integrated circuit (IC), semiconductor fabrication in includes metallization. The purpose of metallization in semiconductor fabrication is to interconnect the various components of the IC. Metallization involves the deposition of a layer of conductive material, generally referred to as a metal layer, over the surface of the silicon substrate and the etching of a pattern in the metal layer to form the interconnections of the desired circuit. In automated IC design, the metal layer pattern is created by routing that implements the specified circuit. A typical IC includes more than one metal layer (e.g., M1, M2, . . . , and M6), the metal layers being individually created and then connections being made between the metal layers as needed.
[0006] As semiconductor design and fabrication improves, semiconductor technology scales become smaller. Semiconductor technology roadmaps predict, for example, that the number of metal (wiring) layers may reach 10 layers even in the 130 nm process generation, and the maximum clock frequencies will reach the gigahertz range even in the 180 nm process generation. It is further predicted that the interval between process generations may be somewhat less than three years.
[0007] With current and predicted technology scaling, the design for performance, manufacturability and reliability in high density, high performance deep-submicron ICs is increasingly dependent on IC interconnections design. In order to achieve high speed operations, special attention is paid to the method of interconnecting components in the IC. For instance, routing tools are increasingly required to combine considerations of signal, power/ground and clock distribution.
[0008] Interconnections in the IC form signal paths. For high speed signals, an interconnect and its environment becomes a relatively complex circuit element along which the signals propagate with finite speed. The complex circuit element has resistive, capacitive and inductive attributes that contribute to signal propagation time delays. With such attributes, the interconnect, also known in the context of ICs as a wire, net or line, is an important IC performance limiting factor. With interconnect delays dominating overall IC signal path delays, care is taken as to the characteristics of interconnects, their routing and the performance limiting factors that are associated with the interconnects.
[0009] For instance, a reflection of signal energy which is returned along an interconnect to the signal origin point may cause ringing or a “bumpy” rising edge. To maintain the integrity of signals propagating through interconnects, the geometry (e.g., length) of interconnects is controlled relative to the rise time of signals. Additionally, interconnects configured as transmission lines are typically terminated with a resistance corresponding to the characteristic impedance of such interconnects. However, further improvement in the design of interconnects is needed in order to achieve high speed operations in high density sub-micron ICs. The present invention addresses this and related problems.
SUMMARY OF THE INVENTION
[0010] A preferred embodiment of the present invention provides an aspect of interconnect design for optimizing delay characteristics of interconnects. The preferred embodiment further provides a method for analyzing the delay characteristics of interconnects for verifying interconnect design results. Interconnect delay characteristics are improved by inserting repeaters at predetermined intervals along interconnects in a metal layer. The metal layer is any one of a plurality of metal layers in a semiconductor device that embodies an integrated circuit (IC). Typically, each interconnect in the metal layer has at least one neighboring interconnect. The position of repeaters along every other interconnect in the metal layer is shifted relative to the position of repeaters along their neighboring interconnect(s). To achieve improved interconnect delay characteristics, the positioning of repeaters along interconnects is optimized by adjusting the position shift based on factors such as repeaters physical characteristics and signal waveforms.
[0011] In accordance with the purpose of the invention, as embodied and broadly described herein, the invention relates to a method for optimizing repeaters positioning along interconnects. Specifically, the method includes inserting repeaters in positions along a first interconnect at predetermined intervals that are related to signal transition times. The method further includes inserting repeaters in positions along a second interconnect at the predetermined intervals, the second interconnect being a neighbor of the first interconnect. The positions along the second interconnect are offset, by a predetermined length, relative to the positions along the first interconnect so that the repeaters along the second interconnect are shifted relative to the repeaters along the first interconnect. The predetermined length is half (0.5) of the predetermined intervals such that repeaters are phase shifted by half, wherein the interconnect delay that corresponds to the offsetting by half of the predetermined interval minimizes the interconnect delay under worst case conditions. The repeaters are inserted to decrease interconnect delay and to make the interconnect delay scale linearly with an interconnect length.
[0012] In further accordance with the purpose of the invention, as embodied and broadly described herein, the invention relates to a second method of analyzing interconnects tuning. The method of analyzing interconnects tuning also includes providing a metal layer in a semiconductor device, wherein the metal layer is patterned to have a plurality of interconnects, and inserting repeaters at predetermined intervals along each of the plurality of interconnects, the predetermined intervals being related to signal transition times. This analyzing method further includes providing a signal having a waveform to each of the plurality of interconnects, wherein each of the signal waveforms of signals that are provided to every other interconnect of the plurality of interconnects are offset, by a predetermined phase, relative to signal waveforms that are provided to interconnects neighboring the every other interconnect. With this setup, the delay characteristics of each interconnect are analyzed for selected values of the predetermined phase. One of the selected values of the predetermined phase correlates to half (0.5) of the predetermined interval.
[0013] In further accordance with the purpose of the invention, as embodied and broadly described herein, the invention relates to a second method of analyzing interconnects tuning. The method of analyzing interconnects tuning also includes providing a metal layer in a semiconductor device, wherein the metal layer is patterned to have a plurality of interconnects, and inserting repeaters at predetermined intervals along each of the plurality of interconnects, the predetermined intervals being related to signals transition time. This analyzing method further includes providing a signal having a waveform to each of the plurality interconnects, wherein each of the signal waveforms of signals that are provided to every other interconnect of the plurality of interconnects are offset, by a predetermined phase, relative to signal waveforms that are provided to interconnects neighboring the every other interconnect. With this setup, the delay characteristics of each interconnect is analyzed for selected values of the predetermined phase. One of the selected values of the predetermined phase correlates to half (0.5) of the predetermined interval.
[0014] Advantages of the invention will be set forth, in part, in the description that follows and, in part, will be understood by those skilled in the art from the description herein. The advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims and equivalents.
[0015] part of this specification, illustrate several embodiments of the invention and, together with the description, serve to explain the principles of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
[0017] FIGS. 1aand 1billustrate insertion to interconnects of repeaters in intervals. In FIG. 1b, the repeaters in adjacent interconnects are offset.
[0018] FIG. 2 shows experimental propagation delay results for all combinations of rising (R) and falling (F) initial transition of signals and phase shifts of approximately (0,0) and (0.5,0.5) of repeater locations along aggressor interconnects relative to the phase 0 (no shift) of repeater locations along a victim interconnect.
[0019] FIGS. 3a-3dshow worst-case propagation delays (with respect to all eight possible combinations of rising and falling signals) for the victim interconnect, for each combination of phase shifts of repeater locations along the aggressor (left and right neighbor) interconnects.
[0020] FIGS. 4a-4dshow the same worst-case delay results for the victim interconnect, taken over all eight rise/fall combinations and all nine combinations of signal waveform offsets.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
[0021] The present invention provides an aspect of interconnect design for optimizing delay characteristics of interconnects. Specifically, to satisfy signal propagation delay and integrity constraints, repeaters are inserted in locations along interconnects. The relative positioning of the repeaters is optimized.
[0022] Reference will now by made in detail to a preferred embodiment of the invention, examples of which are illustrated in the accompanying drawings. Wherever convenient, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
[0023] When lateral coupling capacitances are large, worst-case “Miller coupling” begins to dominate noise and delay calculations. Miller coupling is a gain-related multiplication effect that causes the multiplication of effective coupling capacitances seen by interconnects. The Miller Coupling effect increases with the frequency and thus interconnect coupling becomes increasingly detrimental at higher frequencies. When a pair of neighboring interconnects L1 and L2 switch simultaneously in opposite directions, the driver gate of L1 sees the grounded interconnect capacitance plus twice the coupling capacitance of L1 to L2. If L2 is quiet when L1 switches, then the driver gate of L1 sees the grounded interconnect capacitance plus the coupling capacitance to L2. And if L2 switches simultaneously in the same direction, the driver gate of L1 sees only the grounded interconnect capacitance. (In leading-edge processes, each neighbor coupling is of the same (and possibly greater) magnitude as the area coupling to ground.) The “coupling factor” or “switching factor” is often given in the range of [0,2], and since most interconnects have two neighbors, the total coupling factor is in the range of [0,4]. (A detailed discussion about determining the switching factor under worst-case switching conditions at coupled interconnects is provided in the above-referenced co-pending application titled: “Determining A Switching Factor For Optimized Integrated Circuit Design.”)
Repeaters Position Offsetting Methodology for Global Buses
[0024] Global interconnect layers (e.g., metal layers M4-M6) support inter-component signal runs with a length on the order of 3000 um-15000 μm. Global interconnects are increasingly dominated by wide buses and are designed in light of worst-case Miller coupling. A long global bus is routed using repeater blocks, i.e., blocks of co-located repeaters (e.g., inverters) spaced in intervals, say, 4000 μm.
[0025] To reduce the worst-case Miller coupling, the repeaters in adjacent interconnects are offset, as shown in FIG. 1b. FIGS. 1aand 1billustrate insertion to interconnects of repeaters (shown as inverters) in predetermined intervals. In FIG. 1a, there are three interconnects 102, 104 and 106. Each of the interconnects is assumed to be coupled to the neighbor interconnect and is affected by switching conditions at the neighbor interconnect. Interconnect 104, in the middle, is affected by the interconnects 102 and 106 on either one of its sides. Accordingly, interconnect 104 is labeled “victim” and the interconnects 102 and 106 on either one of its sides are labeled “aggressors.” In FIG. 1a, the repeaters are placed along their respective interconnect without any offset between them. In other words, the repeaters along each of the aggressor interconnects 102 and 106 are placed at zero (0) phase difference relative to the respective repeaters along the victim interconnect 104.
[0026] Preferably, the repeaters are inverters or logic gates configured as inverters. A characteristic of CMOS (coupled metal oxide semiconductor) inverters is the ratio (K:1) of the positive (P) region width to negative (N) region width. For typical CMOS inverters, particularly where K=2, the preferred offset is equal to half (0.5) the interval between repeaters. In other words, a phase shift of 50% between respective repeaters along neighboring interconnects is preferred. For example, if repeaters are place along an interconnect at intervals of Lμm, the offset translates to ½L. The interval, L, e.g., 4000 μm, is determined based on relative transition start and end times of signals. With a relative offset between respective repeaters of 0.5 (half) distance, the signals in neighboring interconnects switch in the opposite direction only one half of the switching cycle.
[0027] In a configuration as shown in FIG. 1a, the worst-case switching condition (i.e., signals at aggressor interconnects switching simultaneously and in the opposite direction relative to signals at the victim interconnect) persists throughout the entire chain of repeaters. This is so because of the relative placement of the repeaters (with no offset) as described above. (A detailed description of the effects of worst-case switching conditions on coupled interconnects is provided in the above-referenced co-pending application titled: “Determining A Switching Factor For Optimized Integrated Circuit Design.”) Conversely, in a configuration as shown in FIG. 1b, where the phase shift of repeater locations is substantially half (translated to half of the predetermined interval), any worst-case simultaneous switching on aggressor and victim interconnects persists only for half of each switching period (distance) between consecutive repeaters. Furthermore, for the other half of the switching period (distance) the switching condition becomes best-case simultaneous switching.
[0028] To confirm the advantages of this approach, various phase shift (offset) configurations can be studied. In each case, signal propagation delay results at the aggressors and victim interconnects is then registered. The phase shifts range from 0.0 to 1.0 at 0.1 increments.
[0029] For each configuration in the study, the interconnects are modeled using metal layers M3 and M4 in a 0.25 μm CMOS process as representative technology. It is noted, however, that the principles presented herein are applicable to any metal layer (e.g., M1, M2, . . . M7). In each metal layer, there are three interconnects, a victim interconnect and on each side of the victim interconnect an aggressor interconnect. The interconnects have lengths of either 10,000 μm or 14,000 μm. Characteristic interconnect resistance in this technology is 50 Ωper 1000 μm. In layer M3, the capacitive coupling per 1000 μm from the victim interconnect to each of the aggressor interconnects is 60 μF, and to ground the capacitive coupling is 80 μF. In layer M4, the capacitive coupling per 1000 μm from the victim interconnect to each of the aggressor interconnects is 80 μF, and to ground the capacitive coupling is 160 μF.
[0030] As mentioned before, for analysis purposes the middle interconnect is considered the victim. The interval between repeaters is assumed to be 4000 μm. The repeaters along the victim (middle) interconnect are placed at zero (0.0) phase locations at intervals of 4000 μ, i.e., at positions 4000 μ, 8000 μ, etc., along the victim interconnect. For each of the above-mentioned configurations, the repeaters along the aggressor interconnects are placed at intervals (of 4000 μ) according to all the phase shift (offset) combinations 0.0, 0.1, 0.2, . . . , 0.9. That is, with a phase shift (offset) of 0.2, for example, the repeaters are placed along the aggressor interconnects at positions 4800 μ, 9600 μ, etc., and with a phase shift (offset) of 0.5, the repeaters are placed at positions 6000 μ, 1000 μ, etc. There are 100 different phase combinations.
[0031] For this study, the interconnects are stimulated by signals of a waveform with a rise-time and fall-time of 200 ps. The signal waveforms are periodic with the first transition either rising (R) or falling (F). There are eight combinations of directions for the first transitions, i.e., RRR, RRF, . . . , FFF. Additionally, the waveform cycles of the signals for each of the aggressor interconnects can be offset relative to the waveform cycle of the signal for the victim interconnect. If so, the signals are offset (delayed or accelerated), for example, by −100 ps, 0.0 ps or +100 ps. There are nine (9) combinations of these input signals offsets.
[0032] FIG. 2 shows, for an example of the above-described configurations, experimental propagation delay results for all combinations of rising (R) and falling (F) initial transition of the signals. The interconnects length in this example is 10,000 μ, and the metal layer is M3. FIG. 2 shows respective propagation delay results for phase shifts of approximately (0,0) and (0.5,0.5) of repeaters along aggressor interconnects relative to the phase 0 (no shift) of repeaters along the victim interconnect. The effect of Miller coupling is clearly shown in the results.
[0033] FIGS. 3a-3dshow the worst-case propagation delays (with respect to all eight possible combinations of rising and falling signals) for the victim, for each combination of phase shifts for the repeater locations along the aggressor (left and right neighbor) interconnects. Signal offsets are all 0, i.e., the waveforms cycle start at the same time. All four combinations of metal layer and line length are shown. In every case, the optimum phase shift combination is (0.5,0.5), while the phase shift combination of (0.0,0.0) is actually the least beneficial. The worstcase delay is reduced by anywhere from 25% to 30% when the repeaters are placed with the optimum 0.5 phase shift.
[0034] Finally, and in comparison to the delay results shown in FIGS. 3a-3d, FIGS. 4a-4dshow the same worst-case delay results for the victim interconnect, taken over all eight rise/fall combinations and all nine combinations of signal waveform offsets (rather than repeaters location offsets). Again, even when the signal stimulating the interconnects do not switch perfectly simultaneously, the best phase combination is (0.5,0.5) and the least beneficial phase combination is (0,0).
[0035] In summary, the foregoing repeaters offset technique, particularly, the use in accordance with the preferred embodiment of the invention of 0.5 phase shift as an offset, can reduce worst-case propagation delays along interconnects by more than 30% as compared with conventional techniques. Even though the discussion elaborated on the case of shifting the repeaters by an offset of 0.5 (i.e., placing the repeaters in the middle of the interval) other offsets could be used depending, for example, on repeaters technology (e.g., relative width of P and N regions), neighboring interconnects coupling capacitance and slew time values. In any case, the principle of offsetting repeaters along an interconnect relative to repeaters along a neighbor (adjacent, parallel or the like) interconnect applies to all interconnects throughout each metal layer. It means the interconnects with non-offset repeaters (i.e., victims) are interleaved among interconnects with offset repeaters (i.e., aggressors), where two interconnects of the same kind are typically not next to each other.
[0036] Other embodiments will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope of the invention being indicated by the following claims and equivalents.
Claims
Certificate of Correction present
The claims shown below may not include correction changes. Use the corrected PDF for authoritative text.
What is claimed is:
1. A method of analyzing delay characteristics of interconnects, comprising:
providing a metal layer in a semiconductor device, the metal layer being patterned to have a plurality of interconnects;
inserting repeaters at predetermined intervals along each of the plurality of interconnects, the predetermined intervals being related to signals transition time;
providing a signal having a waveform to each of the plurality of interconnects, the signal waveforms of signals that are provided to every other interconnect of the plurality of interconnects being offset, by. a predetermined phase, relative to signal waveforms that are provided to interconnects neighboring the every other interconnect; and
analyzing the delay characteristics of each interconnect for selected values of the predetermined phase.
2. The method of claim 1, wherein one of the selected values of the predetermined phase correlates to half (0.5) of the predetermined interval.
Patent Citations (11)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US5212107(A) | 1993-05-01 | Suzuki et al. | Examiner |
| US5285165(A) | 1994-02-01 | Renfors et al. | Applicant |
| US5519351(A) | 1996-05-01 | Matsumoto | Examiner |
| US5557779(A) | 1996-09-01 | Minami | Examiner |
| US5798935(A) | 1998-08-01 | Doreswamy et al. | Examiner |
| US5926397(A) | 1999-07-01 | Yamanouchi | Examiner |
| US5974245(A) | 1999-10-01 | Li et al. | Examiner |
| US6009248(A) | 1999-12-01 | Sato et al. | Examiner |
| US6117182(A) | 2000-09-01 | Alpert et al. | Examiner |
| US6198978(B1) | 2001-03-01 | Takahashi | Examiner |
| US6205570(B1) | 2001-03-01 | Yamashita | Examiner |
Non-Patent Literature (40)
- Chen et al. (“An algorithm for zero-skew clock tree routing with buffer insertion”, Proceedings of European Design and Test Conference, Mar. 11, 1996, pp. 230-236).Applicant
- Tellez et al. (“Minimal buffer insertion in clock trees with skew and slew rate constraint”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, No. 4, Apr. 1997, pp. 333-342).Applicant
- Adler et al. (“Repeater design to reduce delay and power in resistive interconnect”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 45, No. 5, May 1998, pp. 607-616),Applicant
- Chung et al. (“Optimal buffered clock tree synthesis”, Proceedings of the Seventh Annual International ASIC Conference and Exhibit, Sep. 19, 1994, pp. 130-133).Applicant
- Muddu et al. (“Repeater and interconnect strategies for high-performance physical designs”, Proceedings of XI Brazilian Sympsoium on Integrated Circuit Design, Sep. 30, 1998, pp. 226-231).Applicant
- Semiconductor Industry Association, National Technology Roadmap for Semiconductors, pages Table of Contents, pp. 1-3, 7-19, 23-113, 163-178, Appendix B1-C8, 1994.Applicant
- Personal communication, SIA NTRS 1997 Revision, Design and Test Technology Working Group (chairs: R. Howard, P. Verhofstadt), 1997 Table of Contents, pp. 1-3, 8, 10-17, 25-38, 94-109, Appendix B, C and D, 1997.Applicant
- C. J. Alpert and A. Devgan, “Wire Segmenting for Improved Buffer Insertion”, Proc. Design Automation Conf., pp. 558-593, Jun. 1997.Applicant
- D. P. LaPotin, U. Ghoshal, E. Chiprout, S. R. Nassif, “Physical Design Challenges For Performance”, International Symposium on Physical Design, pp. 225-226, Apr. 1997.Applicant
- L. Scheffer, “A Roadmap Of CAD Tool Changes For Sub-Micron Interconnect Problems”, International Symposium on Physical Design, pp. 104-109, Apr. 1997.Applicant
- R. F. Sechler, “Interconnect design with VLSI CMOS”, IBM Journal of Research and Development, pp. 23-31, Jan.-Mar. 1995.Applicant
- J. Cong, L. He, A.B. Kahng, D. Noice, N. Shirali and S. H.-C. Yen, Analysis And Justification Of A Simple, Practical 2 ½-D Capacitance Extraction Methodology, Proc. Design Automation Conference, pp. 627-632, Jun. 1997.Applicant
- L. Gwennap, “IC Vendors Prepare for 0.25-Micron Leap”, Microprocessor Report, pp. 11-15, Sep. 16, 1996.Applicant
- A. B. Kahng and S. Muddu, “Efficient Gate Delay Modeling For Large Interconnect Loads”, Proc. IEEE Multi-Chip Module Conference, 6 pages, Feb. 1996.Applicant
- S.Y. Oh, K.-J. Chang, N. Chang and K. Lee, “Interconnect Modeling And Design In High-Speed VLSI-ULSI Systems”, Proc. International Conference on Computer Design: VLSI in Computers and Processors, pp. 184-189, Oct. 1992.Applicant
- W.C. Elmore, “The Transient Response Of Damped Linear Networks with Particular Regard To Wideband Amplifiers,” Journal of Applied Physics, vol. 19, Jan.-Dec. 1948, pp. 55-63.Applicant
- A.B. Kahng and S. Muddu, “An Analytical Delay Model For RLC Interconnects,” IEEE 1996, pp. 237-240.Applicant
- A.B. Kahng, K. Masuko and S. Muddu, “Analytical Delay Models For VLSI Interconnects Under Ramp Input”, IEEE/ACM International Conference on CAD, Nov. 1996, 7 pages.Applicant
- A.B. Kahng and S. Muddu, “A Glossary On Analysis And Modeling Of VLSI Interconnections,”marked Confidential, including Contents, Feb. 1996, 3 pages.Applicant
- S.P McCormick, “Modeling and Simulation of VLSI Interconnections with Moments,” RLE Technical Report No. 543, PhD Thesis, MIT, May 1989.Applicant
- J.K. Ousterhout, “A Switch-Level Timing Verifier For Digital MOS VLSI,” IEEE Transactions on Computer-Aided Design, vol. CAD-4, No. 3, Jul. 1985, pp. 336-349.Applicant
- P.R. O'Brien and T.L. Savarino, “Modeling the Driving-Point Characteristic Of Resistive Interconnect For Accurate Delay Estimation,” Proc. IEEE, 1989, pp. 512-515.Applicant
- P.R. O'Brien and T.L. Savarino, “Efficient On-Chip Delay Estimation For Leaky Models Of Multiple-Source Nets,” Proc. IEEE 1990, Custom Integrated Circuits Conference, pp. 9.6.1-9.6.4.Applicant
- L.T. Pillage, “Asymptotic Waveform Evaluation For Timing Analysis,” IEEE Transactions on Computer-Aided Design, vol. 9, No. 4, Apr. 1990, pp. 352-366.Applicant
- J. Qian, S. Pullela and L. Pillage, “Modeling The Effective Capacitance For The RC Interconnect Of CMOS Gates,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, No. 12, Dec. 1994, pp. 1526-1535.Applicant
- J. Rubinstein, P. Penfield, Jr. And M.A. Horowitz, “Signal Delay In RC Tree Networks,” IEEE Transactions on Computer-Aided Design, vol. CAD-2, No. 3, Jul. 1983, pp. 202-211.Applicant
- C.L. Ratzlaff, S. Pullela and L. T. Pillage, “Modeling The RC-Interconnect Effects In A Hierarchical Timing Analyzer,” IEEE Custom Integrated Circuits Conference, May 1992, pp. 15.6.1-15.6.4.Applicant
- Synopsys, “Design Compiler Family Reference Manual,” Version 3.3a, Mar. 1995, pp. 8-1-8-5.Applicant
- H.B. Bakoflu, “Circuits, Interconnections, and Packaging for VLSI,” Addison-Wesley Publishing Company, 1990, pp. 202-207, 212-215, 282-285.Applicant
- A. Devgan, “Efficient Coupled Noise Estimation for On-Chip Interconnects,” IEEE International Conference on Computer-Aided Design, Nov. 1997, pp. 147-151.Applicant
- G.A. Katopis and H.H. Smith, “Coupled Noise Predictors for Lossy Interconnects,” IEEE Transactions on Components, Packaging, and Manufacturing Technology-Part B. vol. 17, No. 4, Nov. 1994, pp. 520-524.Applicant
- H. Kawaguchi and T. Sakurai, “Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines,” Proc. Asian and South Pacific Design Automation Conference, 1998, pp. 35-43.Applicant
- K. Rahmat, O.S. Nakagawa, S-Y. Oh and J. Moll, “A Scaling Scheme for Interconnect in Deep-Submicron Processes,” IEEE International Electronic Devices Meeting, 1995, pp. 10.2.1-10.2.4.Applicant
- K.L. Shepard, S.M. Carey, E.K. Cho, B.W. Curran, R.F. Hatch, D.E. Hoffman, S.A. McCabe, G.A. Northrop, R. Seigler, “Design Methodology for the S/390 Parallel Enterprise Server G4 Microprocessors,” IBM Journal of Research and Development, vol. 41, No. 4/5, Jul/Sep. 1997, pp. 515-547.Applicant
- A. Vittal and M. Marek-Sadowsak, “Crosstalk Reduction for VLSI,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, No. 3, Mar. 1997, pp. 290-298.Applicant
- G. Yee, R. Chandra, V. Ganesan and C. Sechen, “Wire Delay In the Presence of Crosstalk,” ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Dec. 97, pp. 170-175.Applicant
- K.L. Shepard and V. Narayanan, “Conquering Noise in Deep-Submicron Digital Ics,” IEEE Design & Test of Computers, Jan.-Mar. 1998, pp. 51-62.Applicant
- K. Rahmat, J. Neves and J.F. Lee, “Methods for calculating coupling noise in early design: a comparative analysis,” IEEE 1998, pp. 76-81.Applicant
- R. Macys and S. McCormick, “A New Algorithm for Computing the Effective Capacitance in Deep Sub-micron Circuits,” IEEE Custom Integrated Circuits Conference, 1998, pp. 313-316.Applicant
- T. Sakurai, “Closed-Form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSI's”, IEEE Transactions on Electron Devices, vol., 40, No. 1, pp. 118-124, Jan. 1993.Applicant