Phased array antenna data re-alignment

[0002] This invention relates to phased array antenna data processing and, in particular, to a method and apparatus for digital phased array antenna data alignment.

[0003] Phased array antenna systems generally employ fixed, planar arrays of individual, or subarrays of, transmit and receive elements. Phased array antennas receive signals at the individual elements and coherently reassemble the signals over the entire array by compensating for the relative phases and time delays between the elements. For transmission, the relative phase compensation is applied to the signals at each of the individual elements to electronically steer the beam.

[0004] In conventional phased array antennas, the phase shifts and time delays are applied in the analog domain. Typically, the received signals are combined across an array using analog microwave combining circuits and down-converted to an intermediate frequency using analog microwave mixer components. The intermediate frequency is further processed in the analog domain prior to digitization at a low baseband frequency. This analog processing approach is generally not applicable to large arrays, since wide-bandwidth signals do not retain phase coherency over large arrays. Wideband signal processing in large phased arrays requires programmable true-time-delay components to combine the wideband signals over the array. Programmable, analog, true time delays are generally large, complex and costly components.

[0005] To help solve this problem for wideband signals, digital processing of the antenna signals has been attempted. This process typically involves digitally processing the received signals at an intermediate frequency. This digital solution requires high precision, high speed, analog-to-digital converters with large power demands to digitize the intermediate frequency.

[0006] In accordance with the present invention, the disadvantages and problems associated with previous phased array antennas have been substantially reduced.

[0007] In particular, the present invention provides a method and apparatus for digital phased array antenna data processing. The digital phase array antenna comprises a plurality of antenna elements, each element operable to receive a signal. An analog-to-digital converter is coupled through RF amplification and matching circuitry to at least one of the antenna elements to convert the signal to a multi-bit digital signal. Also included is a data re-alignment circuit coupled to the analog-to-digital converter to correct the received data for angle of arrival.

[0008] In another embodiment, there is provided a method for time re-aligning data received at a digital phase array antenna. This method includes the step of receiving a radar signal at an antenna element. Next, the signal is converted to a multi-bit digital signal using an analog-to-digital converter. Finally, the alignment of the multi-bit signal is corrected by applying a master clock to the analog-to-digital converter and applying time delays in the digital domain.

[0009] For a more complete understanding of the present invention, and for further features and advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0010] FIG. 1 is a block diagram illustrating subarray partitioning of an antenna with incremental time delay;

[0011] FIGS. 2A, 2B, 2C, 2D and 2E illustrate an exemplary antenna array for use with the data realignment system in accordance with the present invention;

[0012] FIG. 3 illustrates a digital antenna data processing system with data realignment in accordance with the present invention;

[0013] FIG. 4 is a block diagram of an analog/digital data realignment system for zeroing out misalignment due to time steering; and

[0014] FIG. 5 is a block diagram of an analog/digital data realignment system utilizing coarse and fine adjustment data realignment.

[0015] Referring to FIG. 1, there is illustrated subarray partitioning with time delay to correct for misalignment to received signals. A similar arrangement is utilized in the transmit mode. Typically transmitted signals are received by means of a phased array antenna and are “steered” using analog phase shifters located within the Transmit/Receive modules mounted at the radiating face of the antenna array. Using a received signal as an example as illustrated in FIG. 1, inbound energy to the phased array is received at an off-bore site angle θ. Active or passive elements are spaced along the antenna array with a center-to-center spacing of “d” such that as the energy is received by each element, a phase shift as given by the expression: $\phi =\frac{-2\pi d}{\lambda }\sin \theta$

[0016] is required to align signals at each element for phase coherent processing.

[0017] For large antenna arrays, the bandwidth and the size of the array must be considered for phase coherent processing. The size of the array is related to the “fill-time”, that is, the reciprocal of bandwidth is fill-time.

[0018] The size “D” of the antenna array or subarray for phase coherent processing is determined by the following equation: $D\le \frac{c}{\beta \sin \theta }$

[0019] where:

[0020] c=speed of light,

[0021] β=the array or subarray bandwidth.

[0022] When the dimension “D” is below a given threshold for the bandwidth, then phase adjusting may be utilized as the sole means for steering and phase coherent antenna processing. When the dimension “D” exceeds the threshold, the array must be divided into subarrays that are space apart by distance “D” as illustrated in FIG. 1.

[0023] Connected to each of the subarrays of FIG. 1, following element signal formation, there is a time delay unit (TDU) for each subarray. These time delay units are identified as: Δτ₀, Δτ₁, and Δτ₂. The time delays are interconnected to the subarrays to compensate for the time delay difference between the subarrays as a receiving signal crosses the large area of the antenna array. The incremental time delay from one subarray to the next subarray is determined by the scan angle θ and the size of the subarray as given by the relationship: $\Delta \tau =\frac{D\sin \theta }{c}$

[0024] Referring to FIGS. 2A, 2B, 2C, 2D, and 2E, there is illustrated an exemplary antenna array 10 comprised of three panels 12. Each panel is divided into a number of long subarrays (LSA) 14. In this system, each panel has four long subarrays 14 and is composed of eight sub-panels 16. Therefore, for the antenna array 10 there are 96 sub-panels 16. On each sub-panel 16 there are 512 antenna elements 18 for receiving and transmitting a data signal. In the antenna array 10, there are 49,152 antenna elements 18.

[0025] Referring to FIG. 3, there is illustrated a digital antenna array configuration in accordance with the teachings of the present invention. The Digital antenna array 20 comprises sub-panels 16 coupled to analog-to-digital converters 24. In turn, the analog-to-digital converters 24 are coupled through a data re-alignment circuit 27 to a digital receiver 26, which is coupled to a digital beamformer 28.

[0026] Sub-panel 16, as described, has 512 elements 18, each element capable of receiving and sending data signals. FIG. 3 illustrates data signals 22 received at the elements 18 of sub-panel 16. In a typical phased array antenna, each element 18 of sub-panel 16 receives data signals 22.

[0027] As illustrated, the analog-to-digital converters 24 receive data signals 22 from antenna elements 18 and converts the received signals from an analog format to a digital format on line 25. In one embodiment, each analog-to-digital converter 24 receives and combines the signals from eight antenna elements 18 in sub-panel 16 as shown in FIG. 1. Other combinations, including providing an analog-to-digital converter for each element, is also possible.

[0028] In conventional phased array receiver systems, analog-to-digital conversion occurs after all the output RF signals of each element in the array are first additively combined and then converted to an intermediate frequency. Often the signal combining process is carried out in layers with a subset of elements combined at a subarray level and the separate subarray outputs combined into one or more final signals. The final signal is then conveyed to an analog-to-digital converter, to provide a sampled, digital representation of the overall received signal to digital processing circuitry.

[0029] Normally, in conventional phased array receiver systems, the element combining process causes the overall strength of the received RF signal power to increase roughly as the number of elements while the coverall RF noise power increases roughly as the square root of the number of elements. As a result, in conventional systems, the signal presented to the input of the analog-to-digital converter tends to be above the noise floor of the received radar signal. That is, the signal-to-noise ratio of the information at the input of the analog-to-digital converter tends to be much greater than unity. Generally, the effective signal-to-noise ratio of the analog-to-digital converter must be equal to or greater than the best case signal-to-noise ratio of the signal at its input. Also, the dynamic range of the analog-to-digital converter, the range of signals that the analog-to-digital converter can accommodate without saturation, must be equal to or greater than the dynamic range of the input signal. Therefore, in conventional systems a multi-bit analog-to-digital converter is used to avoid loss of information due to noise or saturation effects. In a typical conventional system a ten-bit analog-to-digital converter is necessary.

[0030] However, the signal-to-noise ratio of RF signals received by a single element or a small number of elements within a phased array receiver is generally less than unity. The total noise power due to external effects such as atmospheric noise, and internal noise due to temperature effects tend to be greater than the power of the desired radio frequency signal at each element. Since each analog-to-digital converter 24 receives signals directly from antenna elements 18 of the sub-panel 16, the received radar signals are generally below the noise floor. This allows for the use of an analog-to-digital converter with comparably fewer bits, less demanding signal-to-noise ratio, and dynamic range. In one embodiment of the present invention, a one-bit analog-to-digital converter, also known as a one-bit quantizer, is sufficient for use as analog-to-digital converter 24.

[0031] Analog-to-digital converter 24 outputs a binary value of “1” (positive one) if it receives a positive input voltage and outputs a value of “−1” (negative one) if it receives a negative voltage. The average value of the output of analog-to-digital converter 24 follows the average value of the input signal level. When the analog-to-digital converter 24 comprises a single-bit quantizer, it receives an analog signal of Gaussian distributed noise with the mean value of the noise biased by the actual radar signal.

[0032] According to the well known “Sampling Theorem,” to accurately reproduce the original signal from a sampled signal, the sampling must occur at what is known as the “Nyquist” rate. Usually, a low-pass filter is placed before the analog-to-digital converter to prevent signals with a frequency above the frequency from being sampled by the converter.

[0033] After converting the data signals 22 to digital signal format on line 25 by the analog-to-digital converter 24, the digital signal is applied to a data re-alignment circuit 27 that performs various signal processing re-alignment operations on the digital signal. These may include filtering, correcting for Doppler error, adjusting the bandwidth of the signal, extracting the relative phase of the signal output from each subpanel array and other operations.

[0034] After processing on the re-alignment circuit 27, the processed signal passes through a digital receiver 26 to a beamformer 28 which combines signals from multiple digital receivers 26 to achieve an aligned signal across array 10. After the signal from one array is recovered other arrays can be combined together and processed to increase signal-to-noise ratio or to perform other processing operations on the effective larger array.

[0035] Referring to FIG. 4, there is illustrated an implementation of the realignment circuit 27 connected to a series of subarrays 30-1 through 30-M, each of size “D” as illustrated in FIG. 1. Also as illustrated is FIG. 1, a wave front impinges on the elements of the subarray at an angle θ. The signals from each element of a subarray are combined and input to one of the analog-to-digital converters 24-0 through 24-M.

[0036] To provide data realignment in accordance with the present invention, a clock time delay unit 32-0 through 32-M is connected in each of the data paths. Each of the clock time delay units 32-0 through 32-M is connected to a master clock 34 and has an output connected to a respective one of the analog-to-digital converters 24-0 through 24-M. By connecting the clock time delay units in the data path, time misalignment is substantially “zeroed” out due to the time steering created by the master clock 34 connected to the analog-to-digital converters 24-0 through 24-M through respective clock time delay unit 32-0 through 32-M.

[0037] As illustrated in FIG. 4, the data time delay units 36-0 through 36-M, connected to an output of a respective analog-to-digital converter 24-0 through 24-M, functions as described with reference to the time delay units illustrated in FIG. 1. The outputs of the data time delay units 36-0 through 36-M are combined in a summing network 38 and transferred to the digital receiver 26.

[0038] Each of the clock time delay units 32-0 through 32-M introduces a time delay Δτ_clkbased on the position of the interconnected subarray thereby aligning signals of the subarrays to compensate for “fill-time” associated with wideband, large antenna arrays. Each of the data time delays units 36-0 through 36-M introduces a time delay Δτ_datto realign (re-synchronize) data to the master clock 34 prior to summation (combining) in the summing network 38. The relationship between the time delay Δτ_datand time delay Δτ_clkis given as follows: $\Delta {\tau }_{\mathrm{clk}}\left(n\right)=\frac{\mathrm{nD}\sin \theta }{c},\Delta {\tau }_{\mathrm{dat}}\left(n\right)=\frac{\left(M-n\right)D\sin \theta }{c}$

[0039] where, n=the position of the data time delay unit within the array, and M=the number of subarrays in the antenna to be aligned.

[0040] Referring to FIG. 5, there is shown an alternate embodiment of the realignment circuit 27 that includes a “coarse” adjustment and a “fine” adjustment. The subarrays 30-1 through 30-M are connected to a respective analog-to-digital converter 24-0 through 24-M with each of the converters connected to a clock time delay 32-0 through 32-M. Each of the clock time delay units receives an output clock from the master clock 34.

[0041] An output of each of the analog-to-digital converters 24-0 through 24-M is connected to a respective fine adjustment time delay unit 40-0 through 40-M for “fine” data realignment adjustment. Realignment of the data continues with the output of the fine adjustment time delay units 40-0 through 40-M connected respectively to a coarse adjustment shift register 42-0 through 42-M. Each of the shift registers 42-0 through 42-M is clocked by the output of the master clock 34. From the shift registers 42-0 through 42-M the realigned data is combined in a summing network 44.

[0042] Total delay of data signals for realignment in accordance with the network of FIG. 5 is given by the expression:

[0043] Δτ_DAT=Δτ_coarse+Δτ_fine

[0044] where, $\Delta {\tau }_{\mathrm{coarse}}=\mathrm{MODULO}\left(\frac{F_{\mathrm{data}}D\sin \theta }{c}\right)\times \frac{1}{F_{\mathrm{data}}}$ $\Delta {\tau }_{\mathrm{fine}}<\frac{1}{F_{\mathrm{data}}}$

[0045] F_data=the digital data rate within the shift registers 42-0 through 42-M.

[0046] Delay values of the fine and coarse adjustments are incremented in terms of the sample rate (1/F_s) as illustrated in FIG. 5 by utilization of programmable time delay shift registers in the data path. Each shift register is programmed to have enough depth to handle maximum delay for each subarray or groups of subarrays.

[0047] Although the invention has been described with reference to several embodiments thereof, many variations and modification will become apparent to those skilled in the art. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.