Method of etching silicon nitride by a mixture of CH2 F2, CH3F or CHF3 and an inert gas

[0002] 1. Field of the Invention

[0003] The present invention relates to a method of etching a silicon nitride layer and a method of manufacturing a semiconductor device including a step of patterning the silicon nitride layer.

[0004] 2. Description of the Prior Art

[0005] With the development of miniaturization of the semiconductor integrated circuit (LSI), a SAC (Self Alignment Contact) technique and a BLC (Border Less Contact) technique have been employed to arrange the wirings from an impurity diffusion layer to a field insulating film.

[0006] According to the SAC technique, in the event that wirings are connected to two MOS transistors which employ one impurity diffusion layer as a common constituent element and the wirings are to be connected to a common impurity diffusion layer between two gate electrodes, connecting positions of the wirings are regulated by an insulating layer formed on surfaces of two gate electrodes.

[0007] Like the above, with the use of the SAC technique, the wirings can be easily and firmly connected to the impurity diffusion layer between the gate electrodes which are narrowed together with the miniaturization.

[0008] According to the BLC technique, grooves are formed in a device isolation region of a semiconductor substrate, then silicon oxide is filled in the grooves, then an impurity diffusion layer is formed on a semiconductor substrate, then wirings are formed in a region spreading from the impurity diffusion layer to the device isolation region.

[0009] If such BLC technique is employed, an alignment margin in the contact area between the wiring and the impurity diffusion layer can be increased.

[0010] Next, examples of the semiconductor device employing the SAC technique and the BLC technique in the prior art will be explained hereunder.

[0011] SAC technique

[0012] As shown in FIG. 17A, a gate electrode 103 is formed on a silicon substrate 100 via a gate insulating layer 102 and then a cap layer 104 made of SiO₂is formed on the gate electrode 103. Side walls 105 made of SiO₂are formed on the side surfaces of the gate electrode 103. Impurity diffusion layers 101 on the silicon substrate 100 are formed by a first ion implantation with low concentration after the gate electrodes 103 have been formed and a second ion implantation with high concentration after the side walls 105 are formed to have an LDD (Lightly Doped Drain) structure.

[0013] In such condition, after a thin protection film 106 made of SiO₂is formed on an overall surface, a covering layer 107 made of Si₃N₄is formed and then an interlayer insulating layer 108 made of BPSG and an intermediate layer 109 made of SiO₂are formed on the covering layer 107.

[0014] Subsequently, in order to form contact holes in the interlayer insulating layer 108 and the intermediate layer 109, a photoresist 110 having windows 111 over gaps between the side walls 105 is formed.

[0015] In turn, as shown in FIG. 17B, contact holes 112 are formed by dry-etching the interlayer insulating layer 108 via the windows 111 of the photoresist 110 in the vertical direction. In this case, the covering layer 107 made of Si₃N₄having a small etching rate may be used as an etchant to etch the interlayer insulating layer 108 and the intermediate layer 109. Hence, the cap layer 104 and the side walls 105 still remain beneath the covering layer 107 because the covering layer 107 serves as an etching stopper.

[0016] Next, as shown in FIG. 17C, the covering layer 107 and the protection film 106 formed beneath the contact holes 112 are removed by etching. Thus, the impurity diffusion layers 101 are formed on the side surfaces of the side walls 105 are exposed. As the method of etching the covering layer 107 made of Si₃N₄, reactive ion etching using the fluorine gas can be employed. In addition, etching of the protection film 106 made of SiO₂is executed by use of dilution hydrogen fluoride.

[0017] After the photoresist 110 has been removed, wirings are formed on the interlayer insulating layer 108, though not particularly depicted, and then the wirings are connected to the impurity diffusion layers 101 via clearances between the contact holes 112 and clearances between the side walls 105.

[0018] BLC technique

[0019] First, steps of forming up to a structure shown in FIG. 18A will be explained.

[0020] A groove 112 is formed is formed in the device isolation region of the silicon substrate 121, and then a buried insulating film 123 made of silicon oxide is filled into the groove 122. As a method of filling the buried insulating film 123 into the groove 122, such a method can be employed, for example, that the buried insulating film 123 is formed by CVD (Chemical Vapor Deposition) in the groove 122 and on the silicon substrate 121 and then the buried insulating film 123 on a surface of the silicon substrate 121 is removed by polishing.

[0021] A gate insulating film 124, a gate electrode 125, and a gate covering insulating film 126 are then formed in an active region. Then, low-impurity concentration regions 127a, 127dare formed by ion-implanting the impurity into the silicon substrate 121 on both sides of the gate electrode 125 at a low dosage by use of the gate electrode 125 as a mask.

[0022] Then, an insulating film 128 made of silicon nitride and silicon nitride oxide is formed on the silicon substrate 121, the gate covering insulating film 126, and the low-impurity concentration regions 127a, 127d.

[0023] Thereafter, as shown in FIG. 18B, the insulating film 128 is etched in the substantially vertical direction by RIE (Reactive Ion Etching) such that the insulating film 128 remains on side surfaces of the gate electrode 125 and the gate covering insulating film 126. Such insulating films 128 remaining on the side surfaces of the gate electrode 125 are called side walls.

[0024] Then, as shown in FIG. 18C, using the side walls 128 and the gate covering insulating film 126 as a mask, impurity is ion-implanted at a high dosage into the active region which is not covered with the gate electrode 125 and the side walls 128. Therefore, high-impurity concentration regions 129a, 129dare formed in the active region.

[0025] The LDD structure impurity diffusion layers 129a, 129dcan be formed on both sides of the gate electrode 125 by the high-impurity concentration regions 129s, 129dand the low-impurity concentration regions 127a, 127d.

[0026] As shown in FIG. 18D, silicide layers 131s, 131dare formed on surfaces of the low-impurity concentration regions 127s, 127dby the salicide (self-align silicide) technique.

[0027] Thus, a MOS transistor can be formed in the active region.

[0028] After this, as shown in FIG. 18E, a silicon nitride film 132 is formed in the active region and the device isolation region, and then an interlayer insulating film 133 made of silicon oxide is formed on the silicon nitride film 132.

[0029] Then, a plurality of contact holes 134a, 134dare formed in the silicon nitride film 132 and the interlayer insulating film 133 by the photolithography technique. These contact holes 134s, 134dare formed on two silicide layers 131s, 131din the active region. In this case, if miniaturization of the semiconductor device is considered, a diameter of the contact holes 134s, 134dcannot be formed to have a wide margin in size rather than the high-impurity concentration regions 129s, 129dand as a result the contact holes 134s, 134dcan be formed to cross over the buried insulating film 123.

[0030] Then, the wirings (not shown) are provided to the LDD structure impurity diffusion layers 129s, 129dvia the contact holes 124s, 134d.

[0031] With the above, the common SAC technique and the common BCL technique have been described.

[0032] Meanwhile, for example, as set forth in Patent Application Publication (KOKAI) 6-12765, it has been deduced that an etching rate of Si₃N₄can be enhanced rather than that of Si if one of CH₂F₂and CH₃F is employed as an etching gas to etch a covering layer made of silicon nitride, and that the etching rate of Si₃N₄can be enhanced up to about ten times those of SiO₂and Si if the flow rate of the gas is changed and the pressure is set higher.

[0033] In general, if Si₃N₄is etched by use of a gas mixture which consists of a fluorine compound gas as a major gas such as CF₄, SF₆, or NF₃, oxygen, etc., following etching performance has been derived.

[0034] Si etching rate>Si₃N₄etching rate>SiO₂etching rate

[0035] In this case, a value α/β obtained by dividing the etching rate α of Si₃N₄by the etching rate β of SiO₂(referred to as an “etching selectivity of Si₃N₄to SiO₂” hereinafter) has been 2 to 3. Therefore, such gas mixture can be used for the SAC and the BLC, but such gas mixture enables only isotropic etching. Besides, damage of the silicon substrate is increased under such SiN_xetching condition.

[0036] According to the inventors' experiment using another etching gas which includes CF₄and CHF₃mainly, following etching performance has been derived.

[0037] SiO₂etching rate>Si₃N₄etching rate>Si etching rate

[0038] In this case, the etching selectivity of Si₃N₄to SiO₂has been in the range of 0.5 to 1 and such another etching gas enables anisotropic etching. Such another etching gas can be used for information of the contact hole and removal of the LOCOS nitride film.

[0039] Meanwhile, followings have arisen as problems in the SAC technique.

[0040] If the fluorine gas is used as the etching gas, the etching selectivity of Si₃N₄to SiO₂or Si has been enhanced, but such fluorine gas has enabled only isotropic etching. Hence, a patterning accuracy of the silicon nitride layer has been degraded.

[0041] For instance, as shown in FIG. 17A, if etching isotropy is enhanced on the etching step of the covering layer 107, the covering layer 107 is side-etched and further extended from the contact hole 112 laterally. As a result, recesses are formed between the cap layer 104 and the interlayer insulating layer 108 along the lateral direction. If such lateral recesses are considerably deep, i.e., an amount of the side etching becomes large, the covering layer 107 has been eliminated over the gate electrodes 103 so that the lateral holes are formed. Such lateral holes would cause short-circuit of two wirings passing through the neighboring contact holes 112.

[0042] On the contrary, it may be considered that an etching time can be shortened in order to prevent the side etching of the covering layer 107. However, in this case, because of insufficient etching, the covering layer 107 has remained on the side surfaces of the side walls 105. Thus, respective areas of the impurity diffusion layers 101 which are exposed on the side of the side walls 105 are made small. Under such condition, a contact resistance between the wiring passing through the contact hole 112 and the impurity diffusion layer 101 is likely to be increased.

[0043] In addition, in order to completely remove the covering layer 107 on the side surfaces of the side walls 105, it may also be considered that the etching selectivity of Si₃N₄to SiO₂can be made small to thus enhance anisotropy. In this case, there has been caused such a disadvantage that side surfaces of the SiO₂cap layer 104 covering the gate electrode 103 is etched and thus short-circuit between the wiring formed in the contact hole 112 and the gate electrode 103 would be caused.

[0044] Further, if overetching is carried out to remove completely the covering layer 107 between two gate electrodes 103, upper edges of the side walls 105 are also removed so that a part of the gate electrode 103 is exposed. As a result, the gate electrode 103 is short-circuited to a plug passing through the contact hole 112.

[0045] While, followings have arisen as problems in the BLC technique.

[0046] For example, if the etching selectivity of the silicon nitride to the silicon oxide cannot be enhanced when the silicon nitride film 132 is etched via the contact holes 134s, 134dformed in the interlayer insulating film 133, a surface of the buried insulating film 123 made of silicon oxide is etched to thus expose a part of the silicon substrate 121, as shown in FIG. 19. Therefore, since a metal plug formed in the contact holes 134s, 134dis also connected to the silicon substrate 121, the silicon substrate 121 and the metal plug are short-circuited so that a leakage current flows via such short-circuited portion.

[0047] The side wall 128 has been formed of silicon oxide in the above explanation. However, if the side wall 128 is formed of silicon nitride, the etching selectivity of the silicon nitride to the silicon substrate must be enhanced. More particularly, as shown on the left side in FIG. 20, the event that the low-impurity concentration regions 127s, 127dare etched upon vertical etching of the silicon nitride signifies that the low-impurity concentration regions 127s, 127dbeneath the silicide layer 134sare made shallower and therefore resistances of the low-impurity concentration regions 127s, 127dare increased. In addition, as shown on the right side in FIG. 20, if an etching depth on the surface of the silicon substrate 121 is increased upon etching of the silicon nitride constituting the side wall 128a, a depletion layer extended from the impurity diffusion layer 130dcannot be stabilized, but also the silicide layer 134sprotrudes from the low-impurity concentration regions 127s. As a result, a leakage current becomes easy to flow into the silicon substrate 121.

[0048] As described above, in the above prior art, there has been such a problem that the etching selectivity of the silicon nitride to the silicon oxide and the anisotropy have trade-off relations with each other.

[0049] It is an object of the present invention to provide a method of etching a silicon nitride layer which is capable of enhancing an etching selectivity of silicon nitride to silicon and silicon oxide and enhancing etching anisotropy of the silicon nitride, and a method of manufacturing a semiconductor device including such etching step.

[0050] The method of etching a silicon nitride layer comprising the steps of forming a silicon nitride layer on a silicon layer or a silicon oxide layer; loading the silicon layer or the silicon oxide layer and the silicon nitride layer in a dry etching atmosphere; and selectively etching the silicon nitride layer with respect to the silicon layer or the silicon oxide layer by flowing a fluorine compound gas consisting of any one of CH₂F₂, CH₃F, and CHF₃and an inert gas to the dry etching atmosphere.

[0051] According to the present invention, the silicon nitride layer is dry-etched by using the fluorine compound gas composed of any one of CH₂F₂, CH₃, and CHF₃and the inert gas such as Ar, He, etc. With the use of these gases, the etching rate of the silicon nitride layer can be enhanced ten times or more the etching rate of the silicon oxide layer or the silicon layer beneath the silicon nitride layer and in addition the anisotropic etching thereof can be achieved.

[0052] That is to say, the etching selectivity of the silicon nitride layer to the silicon oxide layer and the silicon layer can be enhanced and simultaneously side etching upon patterning of the silicon nitride layer can be suppressed.

[0053] Such etching performance can remarkably appear when the flow rate of the inert gas is set more than three times the flow rate of the fluorine compound gas, in a ratio between the fluorine compound gas introduced into the chamber and the inert gas.

[0054] Hence, in the step of forming the semiconductor device employing the SAC technique, because such etching process is employed, the silicon nitride layer can be excessively etched not to remain the silicon nitride on the side surfaces of the side walls of the gate electrodes. In addition, the silicon oxide layer covering the gate electrodes is never removed by etching. As a result, the contact region formed between two side walls can be prevented from being narrowed and also short-circuit between the gate electrodes and conductive layers in the contact holes can be prevented.

[0055] Also, in the step of forming the semiconductor device employing the BLC technique, if the etching method is applied under the above conditions, etching of the silicon oxide layer which is buried in the groove in the neighboring of the device forming region can be suppressed and the silicon substrate is difficult to be exposed from the side walls of the groove. Consequently, the electrodes formed to cross over the boarder between the groove and the silicon substrate can be avoided from being connected to the silicon substrate beneath the impurity diffusion layer.

[0056] Furthermore, the impurity diffusion layer becomes difficult to be etched by virtue of the RIE which is used to form the side wall made of silicon nitride or silicon nitride oxide on both sides of the gate electrode of the MOS transistor, so that the increase of the leakage current and the increase of electric resistance due to the thinned impurity diffusion layer can be avoided.

[0057] In order to carry out the patterning of the silicon nitride layer as an oxidation preventing mask upon selective oxidation of the silicon substrate, the etching selectivity of the silicon nitride layer to the silicon substrate or the silicon oxide layer formed thereunder can be improved even if the silicon nitride layer is etched under the above conditions. As a result, crystal defects in the silicon substrate due to the etching of the silicon nitride layer can be prevented and also contamination of the silicon oxide layer can be prevented.

[0058] Other and further objects and features of the present invention will become obvious in an understanding of the embodiments about to be described in connection with the accompanying drawings or will be indicated in the appended claims.

[0059] FIG. 1 is a schematic view showing a configuration of an example of an etching equipment used for etching of an insulating film in the present invention;

[0060] FIG. 2 is a graph showing an experimental result illustrative of etching conditions of the present invention, i.e., a relationship between an etching rate and an Ar flow rate for the silicon nitride layer and a silicon oxide layer if a CH₂F₂and an Ar gas is employed;

[0061] FIG. 3 is a graph showing an experimental result illustrative of etching conditions of the present invention, i.e., a relationship between an etching rate and an Ar flow rate for the silicon nitride layer and the silicon oxide layer under the condition that a flow rate of the CH₂F₂is reduced to half of the experiment shown in FIG. 2;

[0062] FIG. 4 is a graph showing an experimental result illustrative of etching conditions of the present invention, i.e., a relationship between an etching rate and an etching atmospheric pressure if the silicon nitride layer and the silicon oxide layer are separately etched;

[0063] FIG. 5 is a graph showing an experimental result illustrative of etching conditions of the present invention, i.e., a relationship between an etching rate and an etching atmospheric pressure if openings are formed in the silicon nitride layer and the silicon oxide layer;

[0064] FIG. 6 is a graph showing an experimental result illustrative of etching conditions of the present invention, i.e., a relationship between an etching rate and a magnitude of an RF power for the silicon nitride layer and the silicon oxide layer;

[0065] FIG. 7 is a graph showing an experimental result illustrative of etching conditions of the present invention, i.e., a relationship between an etching selectivity and a supplied power of an RF power supply in the silicon nitride layer and those in the silicon oxide layer;

[0066] FIGS. 8A and 8B are sectional views showing steps of forming contact holes in the experiment of the present invention respectively;

[0067] FIG. 9 is a graph showing an experimental result illustrative of etching conditions of the present invention, i.e., a relationship between a substrate heating temperature and an etching rate of the silicon nitride in a substrate central region and a substrate peripheral region formed by the etching of the silicon nitride layer;

[0068] FIG. 10 is a graph showing an experimental result illustrative of etching conditions of the present invention, i.e., a relationship between an etching rate of the silicon nitride layer and the substrate heating temperature in the substrate central region and the substrate peripheral region;

[0069] FIG. 11 is a graph showing an experimental result illustrative of etching conditions of the present invention, i.e., a relationship between an etching rate and a magnitude of an RF power for the silicon nitride layer and the silicon oxide layer if a distance between electrodes and a power supply frequency of a reactive ion etching equipment are set lower than those in the experiment shown in FIG. 6;

[0070] FIG. 12 is a graph showing an experimental result illustrative of etching conditions of the present invention, i.e., a relationship between an etching selectivity and a supplied power of an RF power supply in the silicon nitride layer and those in the silicon oxide layer if the distance between electrodes and the power supply frequency of the reactive ion etching equipment are set lower than those in the experiment shown in FIG. 7;

[0071] FIG. 13 is a graph showing a distribution of etching selectivity of the silicon nitride in compliance with difference in the supplied power from the RF power supply and the substrate heating temperature;

[0072] FIGS. 14A to 14C are sectional views showing steps of forming a selective oxidation film on a surface of a semiconductor substrate in the embodiment of the present invention respectively;

[0073] FIGS. 15A to 15K are sectional views showing steps of manufacturing a DRAM cell in the embodiment of the present invention;

[0074] FIGS. 16A to 16J are sectional views showing steps of manufacturing a semiconductor device with the use of BLC technique in the embodiment of the present invention;

[0075] FIGS. 17A to 17C are sectional views showing steps of forming contact holes in the silicon nitride film according to the SAC technique in the prior art;

[0076] FIGS. 18A to 18E are sectional views showing steps of forming contact holes in the silicon nitride film according to the BLC technique in the prior art;

[0077] FIG. 19 is a sectional view showing etching of an oxide film in a device isolation region when the contact holes are formed in the silicon nitride film according to the BLC technique in the prior art; and

[0078] FIG. 20 is a sectional view showing impurity diffusion layers which are thinned by the etching to form side walls in the prior art.

[0079] Embodiments of the present invention will be explained in detail with reference to the accompanying drawings hereinafter. It should be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings and the explanation of the same or similar parts or elements will be omitted or simplified.

[0080] FIG. 1 is a schematic view showing a configuration of a reactive ion etching (RIE) equipment used for etching a silicon nitride layer in the present invention.

[0081] An electrode 3 on which a wafer (substrate) W is loaded and a gas shower 4 which opposes to the electrode 3 at a distance L are arranged in a quartz chamber 2 of the RIE equipment 1. The gas shower 4 has a plurality of gas injecting holes 4aon the side opposing to the electrode 3. A gas pipe 4bis connected to a part of the gas shower 4. The gas shower 4 is made of conductive material such as aluminum, and can function as the other electrode (4).

[0082] A radio frequency power supply RF of a frequency f is connected to the electrode 3, while an earth wire is connected to the gas shower 4.

[0083] In FIG. 1, a reference 5 denotes an exhausting pipe; 6, a template; 7, a heating means; and 8, a temperature controlling means.

[0084] It has been found by the inventors of the present invention that, if an interior of the chamber 2 of the RIE equipment 1 is reduced in pressure, then a fluorine compound gas such as CH₂F₂, CH₃F, or CHF₃and an inert gas such as Ar, He, etc. are introduced into the chamber 2, and then a silicon nitride (Si₃N₄) film, a silicon oxide (SiO₂) film, and a silicon (Si) layer on the wafer W are etched with the use of products obtained by plasmanizing these gases, vertical anisotropic etching of Si₃N₄is made possible under the situation that the etching selectivity of Si₃N₄to SiO₂or Si is enhanced.

[0085] Therefore, results of etching of Si₃N₄, SiO₂, and Si by introducing CH₂F₂as the fluorine compound gas and the argon (Ar) gas as the inert gas into the chamber 2 will be explained hereunder. A six-inch silicon wafer has been used as the wafer W herein.

[0086] For examination of etching, experiments have been carried out by changing conditions of the distance L between the electrodes and the power supply frequency f of the RIE equipment. The case where the distance L between the electrodes and the power supply frequency f are selected as 70 mm and 13.56 MHZ respectively is set as the first equipment constituting condition, and the case where the distance L between the electrodes and the power supply frequency f are selected as 10 mm and 400 kHz respectively is set as the second equipment constituting condition.

[0087] FIG. 2 showing the results of a relationship between an etching rate and an Ar gas flow rate examined under the condition that CH₂F₂gas is supplied to the chamber 2 at a flow rate of 48 sccm. In this experiment, power of the power supply RF is 400 W, and a pressure in the chamber 2 is 100 mTorr. According to this experimental results, as the flow rate of Ar gas is increased, an etching rate of the Si₃N₄film has been enhanced, but an etching rate of the SiO₂film has been hardly changed.

[0088] Hence, in order to enhance the etching selectivity of the Si₃N₄film to the SiO₂film, it has been evident that it is effective that the argon gas must be introduced and its flow rate must be controlled.

[0089] FIG. 3 showing the results of a relationship between an etching rate and an Ar gas flow rate examined under the condition that a flow rate of the CH₂F₂is set to 24 sccm. In this experiment, power of the power supply RF is 400 W, and a pressure in the chamber 2 is 100 mTorr. According to characteristic curves of this experiment, it would be understood that the etching selectivity becomes large rather than the case shown in FIG. 2.

[0090] What is derived from the characteristic curves in FIGS. 2 and 3 is that the etching selectivity of the Si₃N₄film can be enhanced by increasing the flow rate of Ar gas rather than the flow rate of CH₂F₂gas. Particularly, as shown in FIG. 3, such tendency appears remarkably in the event that the flow rate of CH₂F₂gas is reduced. The etching selectivity exceeds 10 if the flow rate of Ar gas is set three times the flow rate of CH₂F₂gas whereas the etching selectivity becomes about 30 if the flow rate of Ar gas is set eight times the flow rate of CH₂F₂gas. The etching rate of the silicon is 3 nm/min, when the Art flow is set for 290 sccm.

[0091] When a relationship between an etching rate and a pressure in the chamber 2 has been examined, the results shown in FIG. 4 has been derived. It has been found that the etching selectivity of the Si₃N₄film can be further enhanced as the pressure is made higher until the pressure comes up to 150 mTorr, but the etching selectivity of the Si₃N₄film is reduced when the pressure exceeds 150 mTorr. As the reason for reduction in the etching selectivity of the Si₃N₄film, it may be considered that a film growth component on the surface of the wafer W is increased when the pressure becomes higher.

[0092] In the experiment shown in FIG. 4, the flow rate of CH₂F₂gas is set to 24 sccm, the flow rate of Ar gas is set to 290 sccm, and the power of the power supply RF is set to 400 W.

[0093] FIG. 4 shows experimental results when the SiO₂film, the Si film, and the Si₃N₄film are etched. Therefore, the results as shown in FIG. 5 can be derived when it has been examined how the etching selectivity of the Si₃N₄film to SiO₂or Si is changed in the contact hole. As shown in FIG. 7, the etching is carried out with respect to the Si₃N₄film, the SiO₂film, and the Si substrate which are located beneath the contact hole opened to have an aspect ratio of about 2.

[0094] According to FIG. 5, the etching rate of the Si₃N₄film beneath the contact hole is never decreased abruptly even when the etching atmospheric pressure is made higher than 200 mTorr. An etching amount in excess of 200 nm/min has been obtained at 450 mTorr. While the etching rate of the SiO₂film formed beneath the contact hole is also enhanced, but it can be reduced lower a the pressure becomes higher. The etching rate can be reduced to 20 nm/min at the pressure of more than 250 mTorr, which is less than {fraction (1/10)} the etching rate of the Si₃N₄film.

[0095] With the above explanation, it has been found that the etching selectivity of the Si₃N₄film to the SiO₂film can be controlled arbitrarily by changing the etching atmospheric pressure.

[0096] In addition, it has also been found that, when the Si₃N₄film is etched with the use of the CH₂F₂gas and the Ar gas, the etching selectivity of the Si₃N₄film to the SiO₂film or the Si layer can be enhanced and simultaneously the etching rate can be increased as the flow rate of the argon gas is increased.

[0097] In this case, even if the etching rate of the Si₃N₄film is increased, i.e., even if the etching selectivity of the Si₃N₄film to the SiO₂film is set to more than 10, the Si₃N₄film beneath the contact hole is seldom side-etched and therefore good patterns have been obtained.

[0098] Next, the results shown in FIG. 6 has been obtained when the magnitude of the power supply RF applied to the electrode 3 of the RIE equipment 1 is varied. Particularly, as the power is increased, the etching rate of the Si₃N₄film can be enhanced but the etching rate of the SiO₂film is hardly changed. Hence, it has become obvious that, as the power is increased, the etching selectivity of the Si₃N₄film to the SiO₂film can be enhanced. The etching selectivity corresponding to change in power has been obtained as shown in FIG. 7.

[0099] According to further experiment by the inventors of the present invention, it has been found that preferably the flow rate of the fluorine gas is set to 5 to 50 sccm, the flow rate of the inert gas is set three times or more that of the fluorine gas, the etching atmospheric pressure is set to 10 to 500 mTorr, and power applied to the silicon nitride layer is set to 1.1 to 5.5 W/cm².

[0100] Even if another fluorine gas and another inert gas are employed, the same results as the above-mentioned results can be obtained.

[0101] Next, when the distance L between the electrodes and the power supply frequency f are set to 10 mm and 400 kHz respectively, the etching rates and the etching selectivities have been examined. In this case, CH₂F₂and Ar as the gases used in etching are set to 36 sccm and 290 sccm respectively, the pressure in the etching atmosphere is set to 350 mTorr, and the supplied power of the radio frequency power supply is set to 500 W.

[0102] Then, as shown in FIGS. 8A and 8B, the silicon oxide film 16 and the silicon nitride film 17 are formed in order on the silicon substrate 11 and a resist 18 in which a window 18ais opened is formed thereon. In addition, etched states of the silicon nitride film 17 and the silicon oxide film 16 in the middle of forming the contact hole 19 by using the resist 18 as a mask have been examined.

[0103] FIG. 9 is an experimental result illustrative of a relationship between the wafer heating temperature and the etching rate of the silicon nitride. According to FIG. 9, the etching rate of the silicon nitride is slightly increased as the temperature is increased higher. Further, the result shown in FIG. 10 has been derived by examining the etching selectivity of the silicon nitride to the silicon oxide. The etching selectivity of the silicon nitride is enhanced higher in compliance with an increase in the temperature. However, if the temperature exceeds more than 95° C., etching of the silicon nitride does not proceed and in addition the etching rate becomes zero and it is impossible to measure the etching selectivity. Followings may be guessed as reasons why such results have been derived.

[0104] Points 1˜3 are possible reasons for the effect of temperature. The sputter ability of ion depends on the Ar flow, the power and the pressure in the atmosphere.

[0105] 1. The selectivity does not attain the sufficient value when the substrate temperature is set too low, with the effect at the bottom of contact hole 19 being:

[0106] the radical amount of high sticking probability <<the ion sputter etching amount

[0107] 2. The selectivity attains a sufficient value, when the substrate temperature is set higher than 1), with the effect at the bottom of contact hole 19 being:

[0108] the radical amount of high sticking probability ≧the ion sputter etching amount

[0109] 3. The Si₃N₄layer is difficult to etch when the substrate temperature is set too high, with the effect at the bottom of contact hole 19 being:

[0110] the radical amount of high sticking probability >>the ion sputter etching amount

[0111] The area on which the radicals stick depends on the temperature, and the sticking amount depends on the frequency of the radio frequency power supply. The high selective ion assist etching is done by adjusting the radical sticking probability and the ion sputter etching at the bottom of the contact hole to suppress the fluorine radical (F^*) production and to hasten the CF_x^*production.

[0112] During the experiments to obtain characteristic curves shown in FIGS. 9 and 10, the power of the radio frequency power supply applied between the electrodes 3, 4 of the RIE equipment 1 was kept constant at 500 W. Therefore, a relationship between the power and the etching selectivity will be explained respectively.

[0113] The result shown in FIG. 11 has been derived by examining how the etching rate of the silicon nitride film depends on the magnitude of the power.

[0114] Next, in order to examine change of the etching rate due to differences in the distance L between the electrodes and the power supply frequency f, the results shown in FIG. 11 and FIG. 6 are compared with each other. Further, in order to examine the etching selectivity due to differences in the distance L between the electrodes and the power supply frequency f, the results shown in FIG. 12 and FIG. 7 are compared with each other. According to such comparison, it has become evident that, if the distance L between the electrodes is smaller or the power supply frequency f is lower, the etching rate and the etching selectivity of the silicon nitride can be increased.

[0115] This is because ion in the plasma can be effectively catched by the silicon substrate side by making the distance L between the electrodes smaller or making the power supply frequency f lower, so that the higher etching rate of the silicon nitride can be obtained.

[0116] Other than the distance L between the electrodes and the power supply frequency f, the etching conditions to detect the characteristics shown in FIGS. 11 and 12 are set substantially identical entirely.

[0117] Next, in the SAC technique shown in FIGS. 16B and 16C to be described later, it has been checked by the experiment how the etching of shoulder portions of the side walls 29 made of the silicon oxide advances during formation of the contact holes by etching the silicon nitride film 32, according to differences in the substrate heating temperature and the power of the radio frequency power supply.

[0118] The etching selectivity near the shoulder of the side walls 29 has appeared as distribution shown in FIG. 13. It has been found that the etching selectivity can be enhanced as the substrate temperature becomes higher and the power of the radio frequency power supply is increased higher. The etching selectivity in the direction 45 degree from the surface can be selected in the range of 10 to 15 by selecting the substrate heating temperature and the power of the radio frequency power supply in such a manner. The etching rate of the silicon nitride film at that etching selectivity ranges from about 400 to 700 mm/min.

[0119] In order to enhance the etching selectivity of the silicon nitride film to the silicon oxide film, it is preferable to set the substrate heating temperature to 20 to 95° C. and to set the power of the radio frequency power supply to more than 350 W. The range of these conditions resides in the left side area rather than a dot-dash line in FIG. 13. The etching is difficult to advance in the right side area rather than the dot-dash line in FIG. 13. The reason for this may be guessed that the ions are hard to enter into the contact hole 36 narrowed by the side walls 29 because of high aspect radio of the contact hole 36.

[0120] Where the temperature labeled on the abscissas in FIGS. 9, 10, 13 correspond to the set temperature of the template 7 of the RIE equipment. The substrate temperature is affected by the plasma in the chamber 2 as a matter of fact. The temperatures put in parenthenes are values by actual measurement, as shown in FIGS. 9,10 and 13.

[0121] In turn, an example of the case where the above technique is applied to manufacture of a semiconductor device will be explained hereunder.

[0122] In this first example, there will be explained a step of forming a field oxide film on a silicon substrate by the selective oxidation method using the RIE equipment 1 shown in FIG. 1.

[0123] First, as shown in FIG. 14A, a thin SiO₂film 12 of 50 Å thickness is formed on a silicon substrate 11, and then an Si₃N₄film 13 is formed on the SiO₂film 12 by CVD. Then, a resist film 14 in which device isolation regions are opened is formed.

[0124] Next, as shown in FIG. 14B, the Si₃N₄film 13 in the range not covered with the resist film 14 is etched. As the etching conditions, according to the experimental results shown in FIG. 4, the pressure in the chamber 2 is set in the range of 50 to 150 mTorr and the etching selectivity is set to more than 10. In addition, the power supplied to the electrode 3 of the RIE equipment 1 is set to 400 W and the flow rate of the CH₂F₂gas is set less than ⅓, preferably ⅕ that of the Ar gas.

[0125] After this, as shown in FIG. 14C, field oxide films 15 made of SiO₂are formed by selectively etching surfaces of the silicon substrate 11 in the range not covered with the Si₃N₄film 13.

[0126] If the fluorine gas and the argon gas are employed to pattern the Si₃N₄film for use in selective oxidation as above, the SiO₂film 12 in the device isolation region has not been etched and has still remained though it is thin, so that the surface of the silicon substrate 11 has not been exposed. As a result, the surface of the silicon substrate 11 can be protected by the SiO₂film 12 and therefore contamination and generation of crystal defect upon etching can be prevented.

[0127] FIGS. 15A to 15K are sectional views showing steps of manufacturing a DRAM cell to which the above etching technique is applied.

[0128] First of all, steps of forming a configuration shown in FIG. 15A will be explained.

[0129] The field oxide film 22 is formed on the silicon substrate 21 by the selective oxidation method. The field oxide film 22 is formed to surround a device forming region A. Formation of this field oxide film 22 may be carried out according to common conditions, otherwise it may be carried out along the steps being explained in the first example. An about 60 Å thick gate insulating layer 23 made of SiO₂is formed in the device forming region A.

[0130] Then, a polysilicon layer 24, a silicide layer 25, and a first cap layer 26 made of SiO₂are formed in sequence on the overall silicon substrate 21 to have thicknesses of 500 Å, 700 Å, and 800 Å respectively. The silicide film 25 is made of tungsten silicide, titanium silicide, etc. and is formed by the salicide technique. The polysilicon layer 24, the silicide layer 25, and the first cap layer 26 are patterned like stripes, as shown in FIG. 15A, by photolitho-graphy using a resist mask (not shown). The polysilicon layer 24 and the silicide layer 25, all being formed like stripes, are used as a word line WL of the DRAM cell. An impurity is introduced into the polysilicon layer 24 upon film formation or after patterning.

[0131] These word lines WL are formed to pass through on the gate insulating layer 23 or the field oxide film 22. Portions of the word lines WL passing through on the gate insulating layer 23 may function as the gate electrode of the MOS transistor. The word line WL may be formed to pass through not only on the field oxide film 22 but also boarders between the field oxide film 22 and the device forming region A. In addition, a plurality of word lines WL are arranged at a distance in the device forming region A.

[0132] Next, an impurity of one conductivity type is introduced into a surface layer of the silicon substrate 21 using the word lines WL and the field oxide films 22 as a mask to thus form a shallow impurity diffusion layer 27 with low impurity concentration. The impurity has an opposite conductivity type to that being included in the silicon substrate 21.

[0133] Subsequently, as shown in FIG. 15B, a first insulating layer 28 made of SiO₂and used for formation of the side walls is formed as a whole to have a thickness of 1000 Å. Further, as shown in FIG. 15C, the first insulating layer 28 is remained as the side walls 29 on the side surfaces of the word lines WL by vertically etching the first insulating layer 28 in terms of the RIE.

[0134] After this, the impurity is introduced into both sides of the gate electrode WL in the device forming regions A while using the side walls 29, the first cap layer 26, etc. as a mask and then activated so as to form a deep impurity diffusion layer 30 of high impurity concentration. The source layer and the drain layer in the LDD structure of the MOS transistor are constructed by the deep impurity diffusion layer 30 and the above shallow impurity diffusion layer 27.

[0135] Next, as shown in FIG. 15D, a first protection film 31 made of SiO₂and covering the gate oxide film 23, the side walls 29, the first cap layers 26, and so on is formed by CVD to have a thickness of 200 Å. Then, a first covering layer 32 made of Si₃N₄, a first interlayer insulating layer 33 made of BPSG, and a first intermediate layer 34 made of SiO₂are grown in sequence on the first protection film 31 to have a thickness of 1000 Å, 2000 Å, and 200 Å respectively, and then a photoresist 35 is coated on the first intermediate layer 34. A film thickness of the first covering layer 32 is set to sufficiently bury the word lines WL.

[0136] Thereafter, windows 35aare formed by exposing and developing the photoresist 35. The windows 35ain the photoresist 35 are formed to be positioned over high concentration impurity diffusion layers 30 to which the capacitor is electrically connected, as described later.

[0137] Then, as shown in FIG. 15E, the first intermediate layer 34 and the first interlayer insulating layer 33 beneath the windows 35aare etched by RIE sequentially to form upper portions of storage contact holes 36.

[0138] Thereafter, as shown in FIG. 15F, the first covering layer 32 made of Si₃N₄and exposed at the bottom of the windows 35ais etched under the above conditions to form lower portions of the storage contact holes 36. In the etching conditions, as shown in FIG. 5, the pressure is set to more than 250 mTorr and the etching selectivity exceeds more than 10. The power supplied to the electrode 3 of the RIE equipment 1 is set to 400 W and, for example, the flow rate of the CH₂F₂gas is set to less than ⅕ of the flow rate of the Ar gas.

[0139] According to such conditions, since the etching rate of the first blanket layer 32 is high and anisotropic etching in the vertical direction can be achieved, the side etching hardly occurs in the first blanket layer 32 but the first protection film 32 still remains. Accordingly, since there is no possibility that the lateral recesses occur in the first covering film 32 on the first cap layers 26, the storage contact holes 36 are never connected. In addition, selectivity and anisotropy of the etching can be sufficiently assured, the first covering layer 32 on the side surfaces of the side walls 29 can be completely removed by excessively etching the first covering layer 32 and therefore the storage contact holes 36 can be prevented from being narrowed on the side surfaces of the side walls 39. In this case, the word lines WL are never exposed from the side walls 29 and the first cap layers 26.

[0140] In turn, under the condition shown in FIG. 16C, the first protection film 32 made of SiO₂and the gate insulating layer 23 are removed by the dilution hydrogen fluoride via the storage contact holes 36. Consequently, the high concentration impurity diffusion layers 30 can be exposed from the storage contact holes 36.

[0141] As shown in FIG. 15G, a polysilicon including impurity is then formed by CVD to be buried in the storage contact holes 36 after the photoresist 35 is removed, so that storage contact layers 37 made of polysilicon are formed. Since the polysilicon is also grown on the first intermediate layer 34, such polysilicon formed on areas other than the storage contact layers 37 is removed by etching.

[0142] After this, an underlying layer 38 of 200 Å thickness is formed on the first intermediate layer 34 and the storage contact layers 37. In addition, as shown in FIG. 15H, the underlying layer 38 is patterned using a resist mask 39 to form openings 40 over the high concentration impurity diffusion layers 30 to which bit lines described later are electrically connected.

[0143] Then, as shown in FIG. 15I, the first intermediate layer 34 and the interlayer insulating layer 33 positioned below the openings 40 are etched by RIE using the resist mask 39 to upper portions of bit line contact holes 41.

[0144] Then, the first covering layer 32, the first protection film 31, and the gate insulating layer 23 positioned below the openings 40 are etched by RIE to form lower portions of the bit line contact holes 41. The etching conditions are set to the same as in the case where the lower portions of the storage contact holes 36 are formed. As a consequence, such a condition can be achieved that side etching of the first covering layer 32 on the side surfaces of the bit line contact holes 41 scarcely occurs, and the first covering layer 32 do not remain on the side surfaces of the side walls 29, and also the word lines WL are not exposed from the side walls 29 and the first cap layers 26.

[0145] After this, as shown in FIG. 18A, bit lines BL are formed. Steps of forming the bit lines BL are given as follow.

[0146] A polysilicon layer 42, a silicide layer 43, and a second cap layer 44 are formed sequentially by CVD in the bit line contact holes 41 and on the underlying layer 38. These layers 42, 43, and 44 are formed under the same conditions as layer growth conditions used to form the word lines WL. In this case, since no first covering layer 32 remains on the side surfaces of the side walls 29 in the bit line contact holes 41 because of vertical anisotropic etching of the first covering layer 32, a contacting area between the polysilicon layer 42 and the high concentration impurity diffusion layer 30 can be assured as designed. Further, since the word lines WL are never exposed from the side walls 29 and the first cap layers 26, the polysilicon 42 constituting the bit line contact portion is in no way brought into contact with the word line WL.

[0147] The polysilicon layer 42, the silicide layer 43, and the second cap layer 44 are patterned to form the bit lines BL. A part of the bit line BL is connected to the high concentration impurity diffusion layer 30 via the bit line contact holes 41. Then, insulating side walls 45 are formed on the side surface of the bit line BL in the same manner as the side walls 29 on the side surfaces of the word lines WL are formed.

[0148] Then, as shown in FIG. 15K, a second protection film 46 made of SiO₂, a second covering layer 47 made of Si₃N₄, and a second interlayer insulating layer 48 made of BPSG are formed in sequence by CVD.

[0149] Next, the second protection film 46, the second covering layer 47, and the second interlayer insulating layer 48 are patterned to form capacitor forming openings 49 on the storage contact layer 37. Capacitors each being made up of storage electrode, a dielectric film, and an opposing electrode are formed in the capacitor forming openings 49 respectively.

[0150] As constituent material for the side walls 29, 45, Si₃N₄in place of SiO₂may be employed together with the above process. However, is such case, it is preferable that the gate insulating layer 26 therebetween should be formed of Si₃N₄. It has been confirmed according to the experiment that a low frequency below 13.56 MHZ may be similarly used as a frequency of the power supply applied to the substrate if RIE is used, but there can be brought about an effect of improving selective etching of the silicon nitride film at 400 kHz.

[0151] The RIE equipment has been employed in the above explanation, but the almost similar effect can be obtained by ECR plasma etching.

[0152] Moreover, as the gas to be added to the fluorine gas, other inert gas such as helium or other gas may be employed in addition to argon.

[0153] Etching of the silicon nitride film in LOCOS and SAL has been explained in the above example. In addition to this, the above etching process may be applied to the case where the side walls made of Si₃N₄are formed or the silicon nitride mask which is used to form recesses in the silicon substrate is formed.

[0154] Next, a step of selectively etching the silicon nitride in forming the contact holes by the BLC technique will be explained.

[0155] First, steps of forming up to a structure shown in FIG. 16A will be explained.

[0156] A groove 52 is formed in the device isolation region of the silicon substrate 51, and then a buried insulating film 53 made of silicon oxide is filled into the groove 52. As a method of filling the buried insulating film 53 into the groove 52, such a method can be employed, for example, that the buried insulating film 53 is formed by CVD in the groove 52 and on the silicon substrate 51 and then the buried insulating film 53 on a surface of the silicon substrate 51 is removed by polishing.

[0157] A gate insulating film 54, a gate electrode 55, and a gate covering insulating film 56 are then formed in an active region. Then, low-impurity concentration regions 57s,57dare formed by ion-implanting the impurity into the silicon substrate 51 on both sides of the gate electrode 55 at a low dosage by use of the gate electrode 55 as a mask. The impurity is phosphorous (P), for example, and has an opposite conductivity to the impurity included in the silicon substrate 51.

[0158] Then, an insulating film 58 made of silicon nitride or silicon nitride oxide is formed on the silicon substrate 51, the gate covering insulating film 56, and the low-impurity concentration regions 57s,57dto have a thickness of 50 nm.

[0159] Thereafter, the silicon substrate 51 is loaded in the chamber 2 of the RIE equipment 1 shown in FIG. 1. Then, as shown in FIG. 16B, the insulating film 58 is etched in the substantially vertical direction by RIE such that the insulating film 58 remains on side surfaces of the gate electrode 55 and the gate covering insulating film 56. Such insulating film 128 remaining on the side surfaces of the gate electrodes 125 are used as the side walls.

[0160] During reactive ion etching, as mentioned above, the fluorine compound gas consisting of any one of CH₂F₂, CH₃F, and CHF₃and the inert gas such as Ar, He, etc. are introduced into the chamber 2. The flow rate of the fluorine compound gas is set to 5 to 50 sccm, and the flow rate of the inert gas is set more than three times the flow rate of the fluorine compound gas. The pressure in the chamber 2 is set to 10 to 500 mTorr, the substrate heating temperature is set in the range of 20 to 95° C., and the supply power of the radio frequency power supply RF is set in the range of 350 to 700 W.

[0161] Under these conditions, the etching selectivity of the silicon nitride to the silicon oxide can be enhanced. Therefore, since the buried insulating film 53 made of silicon oxide is difficult to be etched in the etching step to form the side wall 58s,the silicon substrate 51 is hard to exposed from the side surfaces of the groove 52. In addition, since the surface of the silicon substrate 51 is difficult to be etched, the low-impurity concentration regions 57s,57dcan be suppressed from being thinned.

[0162] Then, as shown in FIG. 16C, using the side walls 58 and the gate covering insulating film 56 as a mask, impurity such as arsenic (As) is ion-implanted at a high dosage into the active region which is not covered with the gate electrode 55 and the side walls 58. Therefore, high-impurity concentration regions 59s,59dare formed in the active region.

[0163] The LDD structure impurity diffusion layers 60s,60dcan be formed on both sides of the gate electrode 55 by the high-impurity concentration regions 59s,59dand the low-impurity concentration regions 57s,57d.

[0164] Then, as shown in FIG. 16D, a metal film 61 made of cobalt (Co) is formed by sputtering to cover the side wall 58sand the silicon substrate 51.

[0165] Then, by heating the metal film 61 and the low-impurity concentration regions 57s,57dat a temperature of 550° C., silicon and metal as constituent material can be alloyed. As a result, the silicide layers 62s,62dare formed on surfaces of the low-impurity concentration regions 57s,57dby the salicide technique. Then, as shown in FIG. 16E, the metal film 61 which does not react yet and remains on the silicon substrate 51 is removed.

[0166] After this, as shown in FIG. 16F, the silicon nitride film 63 is formed in the active region and the device isolation region, and then an interlayer insulating film 64 such as PSG, BSG, or SiO₂including the silicon oxide is formed on the silicon nitride film 63. Then, the interlayer insulating film 64 is planarized by chemical-mechanical polishing, then a photoresist 65 is coated on the interlayer insulating film 64, and then windows 65aare formed over the high-impurity concentration regions 59s,59din the photoresist 65 by selectivity exposing and developing the photoresist 65.

[0167] Then, the silicon substrate 51 is loaded in the chamber 2 of the RIE equipment 1 shown in FIG. 1. Then, as shown in FIG. 16G, the interlayer insulating film 64 is etched using the photoresist 65 as a mask. Then, as shown in FIG. 16H, contact holes 66 are formed by etching the silicon nitride film 63.

[0168] The etching of the interlayer insulating film 64 can be etched by the gas including C₄F₈, CO, Ar, for example. According to such etching gas, the etching selectivity of the interlayer insulating film 64 to the silicon nitride film 63 can be made high so that the silicon nitride film 63 can remain.

[0169] As described above, during the etching of the silicon nitride film 63, the fluorine compound gas consisting of any one of CH₂F₂, CH₃F, and CHF₃and the inert gas such as Ar, He, etc. are introduced into the chamber 2. The flow rate of the fluorine compound gas is set to 5 to 50 sccm, and the flow rate of the inert gas is set more than three times the flow rate of the fluorine compound gas. The pressure in the chamber 2 is set to 10 to 500 mTorr, the substrate heating temperature is set in the range of 20 to 95° C., and the supply power of the radio frequency power supply RF is set in the range of 350 to 700 W.

[0170] Under these conditions, the etching rate of the silicon nitride film 63 can be enhanced and also etching of the silicon oxide film 53 and the silicon substrate 51 can be suppressed. As a consequence, the silicon substrate 51 can be prevented from being exposed from the groove 52.

[0171] Thereafter, as shown in FIG. 16I, the photoresist 65 is removed by the solvent, then as shown in FIG. 16J, conductive films 67s,67dare filled in the contact hole 66, and then wirings 68s,68dare formed on the interlayer insulating film 64. In this case, the wirings 68s,68dare electrically connected to the LDD structure impurity diffusion layers 60s,60d.The conductive films 67s,67din the contact hole 66 are not connected substantially to the silicon substrate 51 beneath the impurity diffusion layers 60s,60d,but connected only to the silicide layers 62s,62d.As a result, leakage current flowing from the wirings 68s,68dto the silicon substrate 51 can be suppressed.

[0172] According to the present invention described above, since the silicon nitride layer is dry-etched while using the fluorine gas composed of any one of CH₂F₂, CH₃, and CHF₃and the inert gas, the etching rate of the silicon nitride layer can be enhanced 10 times or more the etching rate of the silicon oxide layer or the silicon layer beneath the silicon nitride layer and in addition the anisotropic etching thereof can be achieved.

[0173] Accordingly, because such etching process is employed in the SAC step for the semiconductor device, the silicon nitride layer can be excessively etched not to remain the silicon nitride on the side surfaces of the side walls of the gate electrodes and furthermore the silicon oxide layer covering the gate electrodes is never removed by etching. As a result, the contact region formed between two side walls can be prevented from being narrowed and also short-circuit between the gate electrodes and conductive layers in the contact holes can be prevented.

[0174] Various advantages not referred to herein will occur to one skilled in the art in employing of the invention in practice. Many variations of such embodiments exist and such variations are intended to be within the scope of the present invention and the appended claims.