Method of forming plugs and local interconnect for embedded memory/system-on-chip (SOC) applications

[0002] This invention is directed to a method for fabricating chips having embedded memory and other components, such as logic circuits. More particularly, this invention is directed to a simple method for providing plugs and local interconnects in chips having embedded DRAM.

[0003] Combining both embedded DRAM memory and other components, such as high speed logic circuits, onto a single chip is often useful. For example, U.S. Pat. No. 5,883,814 discloses advantages to such a system-on-chip (SOC) including faster speed and overcoming bandwidth and capacitance problems associated with off-chip connections between arrays of memory and logic.

[0004] Systems-on-chip include memory-in-logic, where memory circuits are embedded in primarily logic blocks and logic-in-memory which are predominantly memory blocks with some logic circuitry. Increasingly important applications for systems-on-chip include high-performance, low-power multi-media apparatus.

[0005] In systems comprising both memory and logic, both the memory and logic are preferably made with as many common processing steps as possible. However, many process steps that are conveniently used for logic and SRAM applications, such as metal local interconnects, are not practical for embedded memory applications, specifically DRAM, because of the leakage/refresh requirements for the DRAM process.

[0006] A hallmark of this invention is a process for fabricating low resistance local interconnects and polysilicon plugs for a combined embedded memory/logic array.

[0007] The applicants have found via this invention that the formation of low resistance interconnects and plugs with metal silicide interconnects can be used in the same chip with DRAM arrays.

[0008] One embodiment of the invention is a method of fabricating silicided plugs, the method comprising the steps of: (i) providing a silicon substrate having at least one N-type doped region and at least one P-type doped region, wherein the N-type doped region and P-type doped region are arranged to form at least one diffused source/drain junction or are separated by isolation wherein the silicon substrate is overlaid with an insulative layer; (ii) opening a first hole in the insulative layer to expose the diffused source/drain junction (if present) and at least part of the N-type doped region or P-type doped region; (iii) forming a layer of a first highly doped polysilicon having the same doping as the region exposed in step (ii) within the first hole to form a first plug, such that the layer of first highly doped polysilicon is at least as high as the insulative layer; (iv) opening a second hole in the insulative layer adjacent to the first plug to expose at least part of the doped region having a different type doping than the first highly doped polysilicon; (v) forming a layer of a second highly doped polysilicon, having the same type doping as the region exposed by the second hole, within the second hole to form a second plug abutting the first plug, such that the layer of second highly doped polysilicon is at least as high as the insulative layer; and, (vi) forming a metal silicide layer on top of both the first plug and the second plug electrically connecting the first and second plugs (local interconnect).

[0009] Another preferred embodiment of the invention is a method of fabricating a system-on-chip, the method comprising the steps of: (i) providing a semiconductor device comprising a silicon substrate, the silicon substrate having arrayed thereon at least one first component comprising a DRAM wordline and at least one second component selected from the group consisting of a device comprising a logic gate, an SRAM or a combination thereof, wherein the silicon substrate, the first component and the second component are overlaid with a layer of an insulative material, wherein a first silicon plug, in electrical contact with the first component and second component, extends through the layer of insulative material to the silicon substrate of like doping and a second silicon plug, in electrical contact with the second component, extends through the layer of protective material to the silicon substrate of like doping; and (ii) forming a metal silicide layer on the first plug and the second plug creating a local interconnect in the second component.

[0010] Another preferred embodiment of the invention is a method of fabricating a system-on-chip, the method comprising the steps of: (i) providing a semiconductor device comprising a silicon substrate, the silicon substrate having arrayed thereon at least one first component comprising a DRAM wordline and at least one second component selected from the group consisting of a device comprising a logic gate, an SRAM or a combination thereof, wherein the silicon substrate, the first component and the second component are overlaid with a layer of a insulative material, wherein a first silicon plug, in electrical contact with the first component and second component, extends through the layer of insulative material to the silicon substrate of like doping and a second silicon plug, in electrical contact with the second component, extends through the layer of insulative material to the silicon substrate of like doping; (ii) depositing a second insulative layer on top of the first insulative material, the first plug and the second plug; (iii) opening a hole in the second insulative layer to expose a local interconnect pattern for the second component; and (iv) depositing a layer of refractory metal (and associated thin barrier/adhesive layers of Titanium (Ti)/Titanium nitride (TiN)) in the hole to form a local interconnect.

[0011] Still another preferred embodiment of the invention is a method of fabricating a system-on-chip, the method comprising the steps of: (i) providing a semiconductor device comprising a silicon substrate, the silicon substrate having arrayed thereon at least one first component comprising a DRAM wordline and at least one second component selected from the group consisting of a device comprising a logic gate, an SRAM or a combination thereof, wherein the silicon substrate, the first component and the second component are overlaid with a layer of a insulative material, wherein a first silicon plug, in electrical contact with the first component and second component, extends through the layer of protective material to the silicon substrate of like doping and a second silicon plug, in electrical contact with the second component, extends through the layer of insulative material to the silicon substrate of like doping; (ii) depositing a second insulative layer on top of the layer of first insulator material, the first plug and the second plug; (iii) opening a first hole in the second insulator layer to expose a local interconnect pattern for the second component; (iv) opening a second hole in the second insulator layer to expose the top of the first plug; and (v) depositing a layer of refractory metal (and associated thin barrier/adhesive layers of Ti/TiN) in the first hole to form a first local interconnect and in the second hole to form a bottom electrode.

[0012] Another embodiment of the invention is a system-on-chip comprising: (i) a silicon substrate, the silicon substrate having arrayed thereon at least one first component comprising a DRAM wordline and at least one second component selected from the group consisting of a device comprising a logic gate, an SRAM or a combination thereof; (ii) a layer of a insulative material overlaying the silicon substrate, the first component and the second component, wherein a first silicon plug, in electrical contact with the first and second component, extends through the layer of protective material to the silicon substrate of like doping and a second silicon plug, in electrical contact with the second component and abutting first plug, extends through the layer of insulative material to the silicon substrate of like doping; and (iii) a local interconnect comprising a salicide layer located over, and in electrical contact with, the first silicon plug and the second silicon plug.

[0013] Preferred embodiments of the invention are described below with reference to the following accompanying drawings, which are for illustrative purposes only. Throughout the following views, reference numerals will be used in the drawings, and the same reference numerals will be used throughout the several views and in the description to indicate same or like parts.

[0014] FIG. 1 is a cross-sectional view of a wafer suitable for undergoing the process of the invention.

[0015] FIG. 2 shows a cross-sectional view of a wafer having a diffused N-P junction undergoing the process of an embodiment of the invention.

[0016] FIG. 3 shows the wafer of FIG. 2 at a processing step subsequent to that shown in FIG. 2.

[0017] FIG. 4 shows the wafer of FIG. 2 at a processing step subsequent to that shown in FIG. 3.

[0018] FIG. 5 shows the wafer of FIG. 2 at a processing step subsequent to that shown in FIG. 4.

[0019] FIG. 6 shows the wafer of FIG. 2 at a processing step subsequent to that shown in FIG. 5.

[0020] FIG. 7 shows the wafer of FIG. 2 at a processing step subsequent to that shown in FIG. 6.

[0021] FIG. 8 shows the wafer of FIG. 2 at a processing step subsequent to that shown in FIG. 7.

[0022] FIG. 9 shows the wafer of FIG. 2 at a processing step subsequent to that shown in FIG. 8.

[0023] FIG. 10 shows the wafer of FIG. 2 at a processing step subsequent to that shown in FIG. 9.

[0024] FIG. 11 shows the wafer of FIG. 1 undergoing another embodiment of the invention at a processing step subsequent to that shown in FIG. 1.

[0025] FIG. 12 shows the wafer of FIG. 1 at a processing step subsequent to that shown in FIG. 11.

[0026] FIG. 13 shows the wafer of FIG. 1 at a processing step subsequent to that shown in FIG. 12.

[0027] FIG. 14 shows the wafer of FIG. 1 at a processing step subsequent to that shown in FIG. 13.

[0028] FIG. 15 shows the wafer of FIG. 1 with a possible mim/mis capacitor for reference only.

[0029] FIG. 16 shows a cross-sectional view of a wafer having isolated N-type and P-type regions undergoing a process of the invention.

[0030] In the following detailed description, references made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.

[0031] The terms “wafer” or “substrate” used in the following description include any semiconductor-based structure having a silicon surface. Wafer and substrate are to be understood as including silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when references made to a wafer or substrate in the following description, previous process steps may have been used to form regions or junctions in the base semiconductor structure or foundation.

[0032] The process of the invention to form plugs and local interconnects starts subsequent to the formation of a semiconductor device having an embedded DRAM array along with other components, such as logic or SRAM arrays and appropriate polysilicon contact plugs. An example of such a semiconductor device 70, which for illustration comprises a DRAM array 71 and a DRAM periphery/logic/SRAM array/SRAM periphery 72, is shown in FIG. 1. The device 70 comprises a silicon substrate 10 having isolation areas 11 which are typically shallow trench isolation (STI) oxides. A number of transistors 12a-bare arrayed on substrate 10. Transistors 12aare part of a DRAM array 71. Transistors 12bare part of a DRAM periphery/logic/SRAM array/SRAM periphery 72. Transistors 12a-bconsist of a number of layers. In an exemplary transistor 12a-b(FIG. 1), layer 13 is a gate oxide comprising silicon dioxide. Layer 14 is a single or dual-doped polysilicon which, for transistors 12a,comprises a wordline. Layer 15 is a tungsten/tungsten nitride (or tungsten silicide) layer. Layer 16 is a silicon nitride cap. Layer 17 is a silicon nitride spacer. The substrate 10 and transistors 12a-bare all overlaid with a insulative layer 18 which has been formed over the device by conventional chemical vapor deposition (CVD) or other suitable means. Typically, insulative layer 18 is borophosphosilicate (BPSG), phosphosilicate glass (PSG), or silicon dioxide, preferably BPSG. Plugs 19, 20, 21, 22 comprise heavily doped polysilicon and provide electrical pathways to the transistors 12a-band silicon substrate 10. The conductive plugs 19, 20, 21, 22 are composed of different conductivity type materials.

[0033] Semiconductor device 70 may be fabricated by known means such as described in copending U.S. patent application Ser. No. 09/268,737 which is incorporated herein by reference. Briefly, U.S. patent application Ser. No. 09/268,737 provides a method for making a semiconductor device with conductive plugs 19, 20, 21, 22 of different conductivity types in contact with the active areas of a semiconductor substrate 10 and the active layers of devices such as transistors 12a-b,as depicted in FIG. 1 (device 70). Although not shown, the insulative layer 18 (e.g., BPSG) of the semiconductor device 70 is selectively etched to a semiconductor region of one conductivity type and to the protective layers nitride in our example of an active device (such as transistors 12a-b) to provide openings that are subsequently filled with conductive material of a first type (such as N-type doped polysilicon) to form conductive plugs, e.g., 19, 22. Next, the insulative layer is again selectively etched down to a semiconductor region of an opposite conductivity type and to the protective layers nitride in our example of an active device (such as transistors 12a-b) to provide openings that are subsequently filled with conductive material of a type different than that of the first conductive material (such as P-type doped polysilicon) to form conductive plugs, e.g., 21. The conductive materials are then removed from the surface of the insulative layer 18, for example by CMP processing. The resulting structure is device 70.

[0034] FIGS. 2-10 and 16 shows one embodiment of the current invention. Referring to FIG. 2, substrate 100 has a region of diffused N-type conductivity 101 and a region of diffused P-type conductivity 102. Regions 101 and 102 may overlap to form a diffused junction 103 (as shown in FIG. 2), or may be separated by shallow trench isolation 99 (STI) (as shown in FIG. 16). Substrate 100 is overlaid with an insulative layer 104 which has been formed over the substrate 100 by CVD or other suitable means. Typically, insulative layer 104 is BPSG, PSG, or silicon oxide, preferably BPSG. Preferably, the substrate 100 forms part of a semiconductor device comprising both logic and memory. An example of such a device is semiconductor device 70, as shown in FIG. 1.

[0035] The process of the invention begins by applying a photoresist masking layer 105 having a first opening 107 to define an area to be etched, as shown in FIG. 2. A portion of the insulative layer 104 is etched to form a first plug opening 109 to expose at least portions of the N-type conductivity region 101, and the diffused junction 103 (or STI 99), as shown in FIG. 3. A directional etching process, such as RIE, can be used to etch the insulative layer 104 to form the first plug opening 109. After the etch, the photoresist layer 105 is removed as shown in FIG. 3.

[0036] A highly doped N-type conductivity polysilicon is deposited over the surface of the insulative layer 104 and into the opening 109 to form layer 111, as shown in FIG. 4. After the highly doped N-type conductivity polysilicon is deposited, a conventional CMP/Etch-back process is used to remove the polysilicon layer 111 overlying the insulative layer 104, to form plug 113, as shown in FIG. 5.

[0037] FIG. 6 depicts the next step, in which a second photoresist masking layer 115 having opening 117 is applied to define an area to be etched. A directional etching process, such as RIE, that is selective to silicon, can be used to etch the insulative layer (e.g. BPSG) 104 and, optionally, plug 113 to form the plug opening 119 and expose at least a portion of the P-type conductivity region 102, as shown in FIG. 7. After the etch, the photoresist layer 115 is removed as shown in FIG. 7.

[0038] Next, a layer 121 of a heavily doped P-type polysilicon is blanket deposited over the exposed surfaces and into the opening 119 as shown in FIG. 8. Next, a conventional CMP/Etch-back process is used to remove the polysilicon layer overlying the insulative layer 104 and the plug 113, to form plug 123, as shown in FIG. 9.

[0039] FIG. 10 shows the next step of the inventive process wherein a salicide layer 125 is formed over the exposed surfaces of conductive plugs 113 and 123. The salicide layer 125 forms a local interconnect that allows the use of only one contact (not shown) to either side of the dual-conductivity plugs 113, 123 for a connection. The salicide layer 125 may be formed by any convenient process, for example, Ti or Co is blanket deposited by conventional PVD (sputtering) over the exposed surfaces. A, low temperature thermal anneal in N₂(˜650° C. for Ti and ˜400-500° C. for Co) is next used to react the Ti or Co metal component and the Si exposed at the surface of the substrate 100 to form a metastable C49 phase of TiSi₂. The blanket deposition is then etched to selectively using H₂O:H₂O₂:NH₄OH remove only the TiN, leaving behind the C49 TiSi₂. An optional second thermal step is carried out to convert the C49-phase TiSi₂to the more stable, lower resistivity C54-phase TiSi₂. The thermal steps are carried out by RTP in an N₂atmosphere.

[0040] Another embodiment of the method of the invention to form a local interconnect begins subsequent to the formation of a semiconductor device 70 such as shown in FIG. 1. As shown in FIG. 11, a second insulative layer 25, typically silicon oxide, is deposited over the exposed surface of the first insulative layer 18 and over the exposed surfaces of the polysilicon plugs 19, 20, 21, 22. Any practical means for depositing the second insulative layer may be used. Example processes include CVD, ozone/tetraethylorthosilicate (TEOS), and plasma enhanced chemical vapor deposition (PECVD) deposition methods, which are well known to one skilled in the art.

[0041] Next, photolithographic techniques using a photoresist mask are used to define the interconnect line to be etched into the second insulative layer 25. As shown in FIG. 12, layer 25 is patterned and etched to form openings 51, 52 to the plugs 20, 21, 22 of DRAM periphery/logic/SRAM array/SRAM periphery 72. Optionally, layer 25 is also patterned and etched to form opening 50 to expose the N-plug for the DRAM array 71. The photoresist is then removed by conventional cleaning methods.

[0042] Next, a blanket layer 30 of tungsten, or another refractory metal, is deposited on the exposed surfaces of the device 70 sufficient to fill openings 50, 51, 52, as shown in FIG. 13. Any practical method for depositing tungsten can be used. Typically, tungsten and associated thin Ti/TiN layers is deposited by low pressure chemical vapor deposition (LPCVD) in a cold-wall, low pressure system. The tungsten can be deposited from tungsten hexafluoride or tungsten hexachloride, preferably tungsten hexafluoride. The CVD of tungsten is well known in the art and is described in more detail in Silicon Processing,pg. 207-213. The tungsten deposition is preceded by depositing a titanium layer followed by annealing by RTP in nitrogen ambient atmosphere. The optional titanium layer aids in decreasing the sheet resistance of the local interconnect and the reacted TiN serves as an adhesion/barrier layer.

[0043] Next after deposition of the tungsten layer 30, a conventional chemical mechanical polishing (CMP) or etch back (Plasma Dry Etch) is used to remove the tungsten (and titanium nitride) layer overlying the second insulative layer 25. This results in tungsten interconnects 53, 54, and 55 within layer 25, as shown in FIG. 14.

[0044] When DRAM plug 19 is unmasked to the foregoing tungsten deposition process resulting in the formation of tungsten plug 53 (FIG. 14), the tungsten plug 53 can serve as the bottom capacitor electrode for metal-insulator-metal/metal-insulator-semiconductor (MIM/MIS) or simply as a bit line contact for a standard cell capacitor as well as MIM/MIS.

[0045] In one embodiment of a MIM/MIS capacitor, shown in FIG. 15, an insulating layer 60 is deposited, for example by CVD, over tungsten plug 53. The insulating layer 60 may be silicon oxide or silicon nitride. Next, a conducting layer 61 is deposited over insulating layer 60 to form a MIM/MIS capacitor. The conducting layer 61 may comprise a refractory metal, such as tungsten, aluminum, or a doped polysilicon. Any suitable means, such as CVD or any other means may be used to deposit the conducting layer 61. The insulator 60 and conducting layer 61 can be etched by photolithography to form the structure shown in FIG. 15.

[0046] In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.