Static and monolithic current limiter and circuit-breaker component

[0002] This application is a continuation of application Ser. No. 08/769,684, filed Dec. 18, 1996, entitled STATIC AND MONOLITHIC CURRENT LIMITER AND CIRCUIT-BREAKER COMPONENT, and now issued as U.S. Pat. No. 5,903,028.

[0003] 1. Field of the Invention

[0004] The present invention relates to the field of semiconductor components and more specifically to medium or high power components.

[0005] 2. Discussion of the Related Art

[0006] In this field, components are known which are to be connected in series with a load and have the function of limiting the current in this load to a predetermined maximum value. For this purpose, a depletion MOS transistor with its gate connected to its source is for example used.

[0007] Components acting as circuit-breakers are also known.

[0008] An object of the present invention is to provide a new type of static and monolithic component which acts as both a current limiter and a circuit-breaker. Such a component lets a current with a limited value run through it as long as the voltage across it does not exceed a selected trigger threshold, then interrupts the current running through it when the voltage across it exceeds this threshold.

[0009] Another object of the present invention is to implement such a component which is self-restarting, that is, which functions as a current limiter again as soon as the voltage across it falls bellow a selected restarting threshold.

[0010] To achieve these objects, the present invention provides a static and monolithic current limiter and circuit-breaker component including, between two terminals, a one-way conduction current limiter and a sensor of the voltage between the two terminals. The component further includes inhibition means for inhibiting the conduction of the current limiter when the voltage sensed exceeds a selected threshold.

[0011] According to an embodiment of the present invention, the voltage sensor is a voltage divider.

[0012] According to an embodiment of the present invention, the voltage divider includes two N-channel MOS depletion transistors connected in series between the terminals.

[0013] According to an embodiment of the present invention, the inhibition means is a static switch in series with the current limiter.

[0014] According to an embodiment of the present invention, the current limiter is a vertical-type N-channel MOS depletion transistor.

[0015] According to an embodiment of the present invention, the current limiter is a vertical IGBT-type depletion transistor.

[0016] According to an embodiment of the present invention, the current limiter is a bipolar NPN transistor having its collector connected to its base via an N-channel MOS depletion transistor.

[0017] According to an embodiment of the present invention, the current limiter includes a vertical thyristor, a lateral floating-substrate P-channel MOS depletion transistor having its drain connected to the cathode of the vertical thyristor, and an N-channel MOS depletion transistor being placed between the cathode and the anode gate of the thyristor.

[0018] According to an embodiment of the present invention, the divider includes a first vertical N-channel MOS depletion transistor and a second lateral N-channel MOS depletion transistor.

[0019] These objects, features and advantages, as well as others, of the present invention will be discussed in detail in the following description of specific embodiments, taken in conjunction with the following drawings, but not limited by them.

[0020] FIG. 1 shows the current/voltage characteristic of a device according to the present invention;

[0021] FIG. 2A is a block diagram illustrating the main components of a device according to a first embodiment of the invention;

[0022] FIG. 2B is a block diagram illustrating the main components of a device according to a second embodiment of the invention.

[0023] FIGS. 3A and 3B respectively are a symbolic representation and a schematic cross sectional view of a suitable current limiter according to the present invention;

[0024] FIGS. 4A and 4B respectively are a symbolic representation and a schematic cross-sectional view of another suitable current limiter according to the present invention;

[0025] FIGS. 5A and 5B respectively are a symbolic representation and a schematic cross-sectional view of another suitable current limiter according to the present invention;

[0026] FIGS. 6A and 6B respectively are a symbolic representation and a schematic cross-sectional view of another suitable current limiter according to the present invention;

[0027] FIG. 7A is a symbolic representation of a suitable voltage divider according to the present invention, and FIGS. 7B and 7C are schematic cross-sectional views of suitable structures for the voltage divider of FIG. 7A;

[0028] FIG. 8A is a schematic cross-sectional view of a limiter-circuit-breaker according to the second embodiment of the present invention, and FIGS. 8B and 8C are equivalent symbolic representations of the limiter-circuit-breaker of FIG. 8A; and

[0029] FIG. 9A is a schematic cross-sectional view of a limiter-circuit-breaker according to the first embodiment of the present invention and FIG. 9B is an equivalent symbolic representation circuit diagram of the limiter-circuit-breaker of FIG. 9A.

[0030] Generally, as is conventional, the cross-sectional views of semiconductor components in the drawings are not drawn to scale, neither within a given figure, nor from one figure to another. Those skilled in the art will refer to their general knowledge to determine the thicknesses and the doping levels of the various layers. The surfaces occupied by the various layers or the number of cells constituting a primary component will, as is known, be selected according to the technology used and the power dissipation imperatives.

[0031] The present invention aims at implementing a static and monolithic component having the current/voltage characteristic illustrated in FIG. 1.

[0032] As long as the voltage is lower than a threshold voltage VT, the current flowing through the component is limited to a substantially constant value Ion. As soon as the voltage across the components exceeds value VT, the current falls to a value Ioff which is low with respect to Ion, wherefrom there results a substantial interruption of the current in the circuit including the component.

[0033] FIG. 2A shows in the form of a block diagram the overall structure of a component according to a first embodiment of the present invention. This component connects between terminals A and K, the terminal A or anode terminal being positive with respect to the terminal K or cathode terminal. The component includes, between these terminals, a current limiter 1 and a voltage detector 2. The voltage detector (or sensor) is, for example, a voltage divider which supplies a terminal C with a control voltage VC as the voltage between terminals A and K reaches threshold value VT. Voltage VC controls current limiter 1 to inhibit its operation, that is, to block it.

[0034] In a second embodiment of the present invention illustrated in FIG. 2B, the voltage detector causes the opening of a switch 3, in series with limiter 1, as the voltage between terminals A and K reaches value VT.

[0035] FIGS. 3 to 6 show various possible embodiments of a current limiter that are suitable for the present invention. Each embodiment may be integrated as one block with the other elements of the component according to the invention. Notably, this limiter is of a vertical type and includes a first electrode on a first main surface of the component and a second electrode on a second main surface of the component.

[0036] The current limiter of FIG. 3A is an N-channel MOS depletion transistor (NMOS_D) having its gate connected to its source.

[0037] FIG. 3B shows a simplified schematic cross-sectional view of an example of an embodiment of such a component.

[0038] This component is formed into an N-type silicon layer 11 with a low doping level including on its rear surface side a highly-doped N-type layer 12 enabling the making of an ohmic contact with an anode metallization M1 covering the rear surface. Transistor NMOS_Dis implemented in a vertical form to enable significant power dissipation. It includes one or more cells, each of which is formed in a lightly-doped P-type well 14 having, for example, an hexagonal or square shape in plane view. On the upper surface side of well 14 is formed an N⁺-type region 15 with substantially the shape of ring. The upper part of well 14 between the outer circumference of ring 15 and the outer circumference of well 14 is occupied by a lightly-doped N-type region 16 coated by a gate insulator 17. The central portion of well 14 generally corresponds to a more highly-doped P-type region 18. The upper surface of the component is coated with a cathode metallization M2.

[0039] Thus, as is known, the rear surface of the component corresponds to the drain of the MOS transistor, region 15 corresponds to its source, overdoped portion 18 corresponds to the contact of the substrate of the MOS transistor and region 16 corresponds to the channel region. Metallization M2 forms a gate contact above gate insulation region 17, a source contact above region 15 and a substract contact above region 18. A component having a function corresponding to the diagram of FIG. 3A is thus obtained.

[0040] This component is known in the art and is likely to have various alternative embodiments well known by those skilled in the art.

[0041] FIG. 4B shows an alternative embodiment of the component of FIG. 3B wherein the semiconductor highly-doped N-type rear surface layer 12 is replaced by a highly-doped P-type layer 19. A so-called depletion isolated-gate bipolar transistor (IGBT_D) is thus obtained, its equivalent diagram being illustrated in FIG. 4A. This component is equivalent to a PNP transistor, with its transmitter corresponding to layer 19, its base corresponding to lightly-doped region 11, and its collector corresponding to P regions 14, 18. A vertical N-channel MOS depletion transistor, identical to that of FIG. 3B, is connected through its source terminal to terminal K and through its drain terminal to the base of transistor PNP and thus ensures, by maintaining a constant base-collector current, the flowing of a constant current between the collector and transmitter of the PNP transistor.

[0042] In the diagram of FIG. 5A, a component is provided as a current limiter, which includes between terminals A and K a component BIP_Dincluding, between terminals A and K, an NPN-type bipolar transistor having its collector connected to terminal A and its transmitter to terminal K. The base of this NPN transistor is connected to its collector via a transistor NMOS_Dsuch as previously described. The maintaining of a constant collector-base current in this NPN transistor under the effect of transistor NMOS_Densures the maintaining of a constant current between the collector and transmitter. It should be noted that the provision of such a component constitutes an aspect of the present invention.

[0043] An example of implementation of the component of FIG. 5A is illustrated in the schematic cross-sectional view of FIG. 5B. The same parts as in FIG. 3B are found in this component, referred to by the same reference numerals, to constitute a vertical N-channel MOS depletion transistor notably including the regions and layers referred to by reference numerals 11-12 and 14-18. Again, the rear surface is coated with a uniform anode metallization M1. A specific character of the structure of FIG. 5B is that the central portion, internal to N⁺-type region 15, is occupied by a strongly-doped N-type region 21. This region 21 is formed into a portion with a low level of doping of well 14 and is coated with a metallization M3 connected to cathode K. A metallization M4 forms the gate, source and well contact metallization of transistor NMOS_D. This metallization M4, by its contact with well region 18, forms the base connection of the NPN transistor. This NPN transistor has region 21 as a transmitter, region 18 as a base and regions 11, 12 as a collector.

[0044] This implementation is likely to have various variants which will be apparent to those skilled in the art. Notably, the doping of P region 18 should be optimized to optimize the gain of the NPN transistor. In an alternative embodiment, the base well of the NPN transistor may be separated from the well of transistor NMOS_D. Then, these wells will be connected by a metallization. Such an embodiment will be described hereafter in relation with FIG. 9A, and has the advantage of enabling to optimize the doping levels of the wells according to the characteristics of the NPN transistor and of transistor NMOS_Dwhich are searched.

[0045] FIG. 6A shows the diagram of a structure TH_Dwherein the current limiter component is a P-channel MOS depletion floating-substrate transistor PMOS_DF. Transistor PMOS_DFis implemented in the form of a lateral MOS transistor. Thus, to ensure that the main electrodes of the current limiter are mounted on the opposite main surfaces of the component, this transistor PMOS_DFis connected in series with a thyristor TH. The turning-on of thyristor TH is ensured by the series-connection of its cathode and of an anode-gate region via an N-channel MOS depletion transistor NMOS_D.

[0046] FIG. 6B shows an example of an embodiment of the circuit of FIG. 6A. In the right portion of FIG. 6B, semiconductor regions similar to those described in the preceding drawings can be found. It should be noted that the rear surface semiconductor layer is a P⁺-type layer 19, as in the case of FIG. 4B. Thus, layers and regions 15, 14, 11 and 19 altogether form a thyristor TH. N⁺-region 15 forms, with channel region 16 and lightly-doped region 11, an NMOS depletion transistor. Metallization M4 corresponds to a gate-source connection of transistor NMOS_D, and to the cathode of thyristor TH. Metallization M4 extends over the more highly-doped P-type region 18. This structure includes, contiguous to region 18, a p-region 27 and a p region 28. p- region 31 is topped by a gate insulation region 29. A metallization M5 is in contact with region 28 and extends over gate insulation region 29. Thus, regions 18, 27 and 28 form a MOS depletion transistor, the substrate of which corresponds to N region 11. This substrate, which is not connected to the transistor source, is floating. A P-channel MOS depletion floating-substrate transistor PMOS_DFhas thus been obtained. Source-gate metallization MS is connected to terminal K. The drain metallization is formed by metallization M4. The structure of FIG. 6B thus corresponds to the structure of FIG. 6A, terminal K being formed on the upper surface and terminal A on the lower surface. Thus, the function of thyristor TH is to transfer to the rear surface the drain metallization of transistor PMOS_DF, and the function of transistor NMOS_Dis to turn on this thyristor.

[0047] FIG. 7A shows an example of a voltage sensor which can be used in a component according to an embodiment of the present invention. This voltage sensor is formed by a voltage divider including two N-channel MOS depletion transistors connected in series and operating as resistors, that is, prior to arriving in their current limiting operation region. Each of these MOS transistors has its gate connected to its source. Terminal A is connected to the drain of a first transistor NMOS_D1 and terminal K to the source-gate of the second transistor NMOS_D2. Besides, a zener diode Z has been shown on the equivalent diagram, with its anode connected to terminal K and its cathode connected to the connecting point C of the two transistors.

[0048] FIG. 7B shows a first embodiment of the circuit of FIG. 7A.

[0049] The transistor NMOS_D1 shown in the left portion of the drawing is a vertical N-channel MOS depletion transistor having substantially the same structure as that shown in FIG. 3B. Reference numerals 114-118 have been used to refer to regions corresponding to those referred to by reference numerals 14-18 in FIG. 3B. It should be noted that, on the rear surface side of the component, an N⁺ layer 12 or a P⁺ layer 19 can be provided which will not substantially alter the operation of transistor NMOS_D1 since, if this rear surface layer is a P⁺-type layer 19, the P⁺N junction between layers 19 and 11 is forward biased, this rear surface being meant to be connected to an anode terminal A which is the most positive of the voltages applied to the component.

[0050] Transistor NMOS_D2 is formed in an extension 30 of the lightly-doped P-type well 114 or in a distinct P-type well in the form of a conventional lateral MOS transistor including an N⁺-type drain region 31 and an N⁺-type source region 32 separated by a preformed lightly-doped N-type channel region 33. The channel region is topped by a gate insulating layer 34.

[0051] Zener diode Z is formed in an extension 40 of well 114 or in a distinct well and includes, in the upper surface of this well, an N⁺-type region 41.

[0052] A metallization M6 corresponds to the source and to the gate of transistor NMOS_D2 and is connected to the cathode terminal K. A metallization M7-1 corresponds to the gate, to the source and to the well contact of transistor NMOS_D1 as well as to the drain of transistor NMOS_D2 and is connected to terminal C. A metallization M7-2 in contact with the cathode region 41 of zener diode Z is also connected to terminal C. It should be noted that the anode of zener diode Z, corresponding to well 40, is connected to terminal K via an extension of metallization MG on well 40.

[0053] FIG. 7C shows a variant of FIG. 7B wherein wells 30, 40 have been separated from well 114, 118. Accordingly, metallization M7-1 joins the drain region 31 of transistor NMOS_D2 by passing over an insulating region 44.

[0054] In FIG. 7C, the insulating regions formed in the upper portion of the component have been shown, other than the gate insulating regions, as thicker as these gate insulating regions. This will correspond to practical implementations and has not been previously shown, for clarity. It should also be noted that, according to the manufacturing process used, more than two distinct insulating layers may be found at the upper surface of the component, some of these layers corresponding to what is generally called “thick oxide” in the context of MOS transistor manufacturing.

[0055] Also, in FIG. 7C, P-type wells 46 and 48 have been shown at the structure limits. These wells may be specifically provided to hold high voltage in the structure or may include other parts of a more complex component.

[0056] FIG. 8A is a schematic cross-sectional view of a limiter circuit-breaker component according to the second embodiment of the present invention. According to whether the rear surface layer of the component is of N⁺ or P⁺ type, the component corresponds to the equivalent diagram of FIG. 8B or of FIG. 8C.

[0057] The diagrams of FIGS. 8B and 8C correspond to implementations of the general diagram of the present invention previously described in relation with FIG. 2B. Limiter 1 is implemented in the form of an N-channel MOS depletion transistor NMOS_Dwith its gate and source interconnected in the case of FIG. 81 and in the form of a depletion IGBT transistor in the case of FIG. 8C. Voltage sensor 2 is implemented in the form of a divider including two N-channel MOS depletion transistors NMOS_D1 and NMOS_D2. Switch 3 is implemented in the form of a P-channel MOS depletion floating-substrate transistor PMOS_DF. A gate protection zener diode Z for transistor PMOS_DFis shown in FIGS. 8B and 8C. Further, in FIG. 8C, a diode D can be found. It is not a component required for the operation of the circuit but a component inherent to its implementation which corresponds to the junction between a P⁺-type rear surface region 19 and N-type substrate 11. Clearly, this diode D does not disturb the operation since it is forward biased. It is all the less disturbing as there normally flows a very low current through the branch including divider 2. Its forward voltage drop will only have to be taken into account for determining the triggering threshold of switch 3.

[0058] Thus, FIG. 8A reproduces in its left portion the parts shown in FIG. 7B. Transistors NMOS_D1 and NMOS_D2 and diode Z are notably to be found therein. In the right portion of the drawing, the structure of FIG. 3B or that of FIG. 4B is to be found, according to whether the lower layer is of N⁺ or P⁺ type. These components, previously described, will not be described again. They are referred to by the same reference numerals in FIG. 8A as in the preceding drawings.

[0059] Switch 3 is implemented in the form of a lateral P-channel MOS depletion floating-substrate transistor PMOS_DFincluding a highly-doped P-type drain region 51, a lightly-doped P-type preformed channel region 52 and a highly-doped P-type source region 53 which, in this embodiment, is common with region 18 of transistor NMOS_D.

[0060] On the portion corresponding to the voltage divider, the same metallizations M7-1, M6 and M7-2 as those described in relation with FIG. 7B are to be found.

[0061] In the right portion of FIG. 8A, a metallization M8 forms one piece with the drain region 51 of transistor PMOS_DF. Metallization M8 is also connected to cathode terminal K. A gate metallization M7-3 of transistor PMOS_Dis also connected to terminal C. A metallization M9 covers the P⁺ drain region of transistor PMOS_Dand the well region of transistor NMOS_D53/18 as well as the source region of transistor NMOS_Dand the gate insulation region of transistor NMOS_D.

[0062] The operating mode of this component clearly results from the diagrams of FIGS. 8B and 8C. As long as the voltage on the midpoint C of voltage divider 2 is lower than the threshold voltage of transistor PMOS_DF, this transistor conducts and transistor NMOS_Dor the depletion IGBT limits the current to a value Ion which depends on their characteristics. As soon as the voltage on midpoint C exceeds the above-mentioned threshold voltage, transistor PMOS_DFstops conducting and there only remains between terminals A and K a very low leakage current Ioff which corresponds to the current in divider 2.

[0063] FIGS. 9A and 9B illustrate a schematic cross-sectional view and an equivalent diagram of a semiconductor component according to the first embodiment of the present invention. This embodiment uses a limiter of the type illustrated in FIGS. 5A and 5B. The general arrangement resembles that represented in the form of blocks in FIG. 2A. Limiter 1, including an NPN transistor and a transistor NMOS_D, is connected between terminals A and K. The base terminal of the bipolar transistor is connected to the cathode terminal via an N-channel MOS enhancement transistor NMOS_Ehaving its gate connected to the output terminal C of divider bridge 2.

[0064] These various components are structurally shown in FIG. 9A. The left portion of FIG. 9A which corresponds to divider bridge 2 is identical to the left portion of FIG. 8A and includes transistors NMOS_D1 and NMOS_D2 as well as zener diode Z. As for the right portion of the drawing, a variant has been introduced with respect to the representation of FIG. 5B, that is, transistors NPN and NMOS_Dare implemented in distinct wells. The NPN transistor appears in the center portion of the drawing. Its base well is referred to by reference numeral 61. Transistor NMOS_Dappears in the right portion of the drawing. Between the NPN transistor and transistor NMOS_D, an example of an implementation of enhancement transistor NMOS_Ehas been shown, which is implemented in the form of a conventional lateral MOS transistor which includes, in a well 62, a drain region 63, a source region 64, and a channel region 65 topped by a gate insulating region 66.

[0065] The metallizations on the voltage divider region are identical to those of FIG. 8A and are referred to by the same reference numerals M6, M7-1, M7-2. As in FIG. 5B, the transmitter 21 of the NPN transistor is coated with a metallization M3 connected to terminal K. The base 61 of the NPN transistor forms one piece with a metallization M4-1 connected to a metallization M4-2 corresponding to the well/source/gate connection of transistor NMOS_D. The drain 63, the gate insulator 66 and the source 64 of transistor NMOS_Erespectively support metallizations M10, M11 and M12. Metallization M10 is connected to metallizations M4-1/M4-2; metallization M11 is connected to metallizations M7-1/M7-2; metallization M12 is connected to terminal K.

[0066] The operation of this component is the following. As soon as the voltage on terminal C is lower than the threshold voltage of transistor NMOS_E, this transistor is blocked and the NPN transistor ensures, by means of the connection between its base and its collector by transistor NMOS_D, the flowing of a constant limited current Ion between terminals A and K. As soon as the voltage on terminal C exceeds the threshold voltage of transistor NMOS_E, this transistor starts to conduct and short-circuits the base-transmitter junction of the NPN transistor, which blocks this latter transistor. Then, there only flows a current Ioff between terminals A and K, this current Ioff mostly corresponding to the current through divider bridge 2.

[0067] As an example only and without limiting the present invention, possible numeric values applicable to the structure schematically shown in FIG. 8A will be indicated hereafter.

[0068] This structure can be formed from an N-type silicon wafer in a plane <100> having a sheet resistance of 30 ohm.cm.

[0069] If the superficial concentration of a region is called Cs, and the junction depth is called xj, the following parameters can be chosen for the various regions.

[0070] The gate widths can be of around 50 nm. The horizontal dimensions of the wells are those currently chosen in the field of power MOS transistors, that is, from approximately 25 to 50 μm.

[0071] With such parameters, devices bearing voltages from 600 to 1500 V are obtained, the current Ion of which is from 1 to 5 A and the current Ioff of which is from 1 to 10 mA.

[0072] Of course, as has already been indicated in this description, each of the parts described as examples is likely to have various variants and can be formed by one or more cells. The present invention is likely to have several variants and modifications, which will occur to those skilled in the art. The latter will essentially have to monolithically assemble the following parts.

[0073] The current must be able to dissipate a significant amount of power. It will preferably be a current limiter, the main current-conducting component of which is a component implemented in a vertical form. The four embodiments of current limiters previously described are only examples. Those skilled in the art can provide other current limiters performing the same function or variants of the current limiters described. For example, the bipolar transistors can be turned into Darlington circuits, and associations of MOS transistors can also be provided.

[0074] Only one voltage sensor of the MOS depletion transistor divider type has been described herein. Those skilled in the art will know how to chose the dimensions and on-state resistances of the transistors so that voltage VC reaches a selected value when voltage VAK reaches a predetermined value. Other dividers, of resistive type or with transistors, may be used. Further, other types of voltage sensors can be provided, to issue an indication which regularly increases until a predetermined value is reached, or to issue an output which varies binarily when a certain threshold is reached. Such a circuit can for instance be formed by a comparator receiving the output of a voltage divider of the type described.

[0075] The switch may be integrated or not to the current limiter. The function of the switch is to bear the voltage in the non-conducting state.

[0076] Other current limiter, voltage sensor and switch associations can be provided, so long as they are compatible and can form a monolithic component.

[0077] Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The invention is limited only as defined in the following claims and the equivalents thereto.