CDMA receiver and method of operation

[0002] The following commonly-owned applications are being filed concurrently and are incorporated herein by reference in its entirety for all purposes:

[0003] U.S. patent application Ser. No. 09/113,603, filed Jul. 10, 1998, entitled “AN IMPROVED CDMA TRANSCEIVER AND FREQUENCY PLAN,” now U.S. Pat. No. 6,028,850.

[0004] U.S. Provisional Pat. App. No. 60/092,374, Jul. 10, 1998, entitled “A VARIABLE CLOCK RATE CORRELATION CIRCUIT FOR A CDMA RECEIVER AND METHOD OF OPERATION.”

[0005] This invention relates to receivers, and in one embodiment, to a dual mode CDMA/AMPS wireless receiver capable of accurately processing CDMA signals in the presence of AMPS interferers.

[0006] In the field of telecommunications, Direct Sequence (DS) Code Division Multiple Access (CDMA) transmission is a popular form of communication because a large number of users may communicate over the same frequency band without interference. In DS-CDMA systems, data is transmitted to an intended recipient by initially generating an address corresponding to the data which is to be transmitted. The address is then combined with a unique pseudo-random bit sequence (PN sequence) to form a combined waveform. The pseudo random sequence causes the combined waveform to appear highly uncorrelated, i.e., unpredictable. The combined waveform is then modulated onto a particular carrier frequency, ranging from 1931.25 MHz-1988.75 MHz in the PCS-band systems or in the frequency range of 869.04 MHz-893.97 MHz in the cellular-band systems. Although many users have access to the signals within a particular frequency band (typically 1.23 MHz wide), none can decipher the combined waveform since it appears to be random. Only the intended recipient is able to decode the combined waveform since his receiver alone produces the same PN sequence used to encode the data within the transmitter.

[0007] The transmitted data typically consists of two orthogonally-phased data streams (I and Q data) which are interleaved onto a single data stream prior to transmission. The orthogonal orientation between the I and Q data allows the compilation and transmission of the two data streams without interference between them. The modulated data stream is subsequently transmitted as “chips” to the receiver. The receiver removes the modulation and separates the original I and Q data from the single data stream.

[0008] FIG. 1 illustrates a typical receiver for the reception of the orthogonal DS-CDMA signals. The CDMA receiver 100 includes an RF amplifier 110, a downconverter 120, an automatic gain control amplifier (AGC) 130, a baseband conversion circuit 140, baseband analog filters 152 and 154, and I and Q channel analog to digital converters (ADCs) 162 and 164. Analog circuitry is shown in white, and digital circuitry is shown in gray.

[0009] During reception, A CDMA signal 102 is received by an electromagnetic collecting apparatus such as an antenna (not shown) and supplied to the CDMA receiver 100. The RF amplifier 110, typically a low noise amplifier (LNA), is used to increase the amplitude of the CDMA signal 102. A downconverter 120 is used to convert the input signal 105 to an IF signal 125 of lower frequency which the subsequent circuitry can process. The downconverter may consist of a single or multiple downconversion stages to frequency translate the RF signal to its final IF frequency.

[0010] The IF signal 125 is supplied to the AGC circuit 130 which provides variable signal gain to account for the varying distances over which the received signal may propagate. The AGC circuit 130 can be controlled via a gain control signal 132 to provide attenuation or gain in varying degrees, producing an AGC output signal 134. The AGC circuit 130 typically provides a sufficient amount of gain or attenuation so that the amplitude level of the I and Q signals supplied to the analog to digital converters (ADCs) 162 and 164 is within an optimum input power range.

[0011] A baseband conversion circuit 140, typically an analog quadrature downconverter circuit, is used to extract the I and Q data from the AGC output signal 134, producing I and Q channel baseband signals 142 and 144. This process typically involves frequency translating the AGC output signal 134 to lower frequency I and Q baseband signals 142 and 144 as well.

[0012] The I and Q channel analog filters 152 and 154 are used to filter out any out-of-band signals prior to the ADCs 162 and 164. Additional filtering 127 may be required within the receiver 100 to achieve the necessary out-of-band rejection.

[0013] The I and Q analog filters 152 and 154 are also designed to have precise group delay response. Prior to transmission, the phase of the CDMA signal is pre-distorted for optimum signal transmission. In order for the I and Q data to be properly reconstructed at the receiver output, the phase response over the communication channel (i.e., between the transmitter input and the receiver output) should be near linear. Thus, the analog filters 152 and 154 must be designed to provide a specific phase response which, when combined with the filters used within the CDMA transmitter (not shown) is a particular value.

[0014] Additionally, the I and Q channel analog filters 152 and 154 must be closely matched to provide substantially identical amplitude and phase responses. The close amplitude and phase matching ensures that the I and Q channel data are equally affected by the filtering stage. The analog filters 152 and 154 are typically realized in switched capacitor form and may be fabricated in IC form or from discrete components.

[0015] I and Q channel ADCs 162 and 164 receive the filtered I and Q baseband signals, converting the signals to I and Q channel data 172 and 174, respectively. Two DC offset voltages 175aand 175bare supplied to the ADCs 172 and 174 to correct for the DC voltage level superimposed on the filtered baseband signals 142 and 144 as a side-effect of the downconversion and analog to digital (A-D) conversion process. The I and Q channel data 172 and 174 is then fed into I and Q channel correlators (not shown) to determine the degree of correlation with the receiver's address code.

[0016] One disadvantage of the conventional CDMA receiver is its inability to reject correlated interfering signals. One such type of signal is generated from the Advanced Mobile Telephone System (AMPS), also commonly used in cellular telephony today. The AMPS system is an analog Frequency Division Multiple Access (FDMA) system in which data is communicated using frequency modulation (FM). Each user is allocated a particular carrier bandwidth, typically 30 KHz, which carries that user's transmissions. The AMPS signals are narrow band (30 KHz) compared to the CDMA signals (1.23 MHz) and are highly correlated.

[0017] Unfortunately, the AMPS system transmits its FM signals within the CDMA receiver band, 869.04 MHz-893.97 MHz. When the AMPS and CDMA signals 102 and 104 are both received by a non-linear device, such as the RF amplifier 105 within the CDMA receiver, a two-tone third order intermodulation product or “AMPS interferer” can be produced at the amplifier's output which is within the CDMA receivers band. Once within the CDMA receiver's band, the AMPS interferer can propagate as a false CDMA signal, causing erroneous data output and signal distortion. The inability of the conventional CDMA receiver to operate in environments where AMPS or other highly correlated signals propagate severely limits the use and operability of the conventional CDMA receiver.

[0018] Another disadvantage of the conventional CDMA receiver is the high cost and marginal performance associated with the I and Q channel analog filters 152 and 154. The I and Q channel analog filters 152 and 154 are needed to provide rejection of the out-of-band signals and add phase correction to the incoming signal. Additionally, the I and Q channel analog filters 152 and 154 must be closely matched to each other. If fabricated from discrete components, each of the analog filters 152 and 154 would require an extensive amount of time and labor to tune and test, and represents a significant cost factor of the CDMA receiver.

[0019] Alternatively, the analog filters 152 and 154 may be fabricated in integrated circuit (IC) form using Bipolar-CMOS (Bi-CMOS) technology. Bi-CMOS IC processing allows for the fabrication of analog and digital circuitry on the same IC die. Using this IC process, the analog filters can be fabricated in IC form without tuning. However, the Bi-CMOS technology is more expensive to implement and suffers from lower yields compared to the more mature digital CMOS or analog Bipolar IC processing technologies.

[0020] A further disadvantage of the conventional CDMA receiver architecture is the implementation of separate I and Q channel ADCs 152 and 154. The I and Q channel ADCs 152 and 154 can have slightly different amplitude and/or phase response characteristics. Implementing separate ADCs increases the likelihood that the I and Q channel data 172 and 174 will exhibit some amplitude and/or phase imbalance.

[0021] Still a further disadvantage of the conventional CDMA receiver is the need for DC offset voltage sources 175aand 175bto correct for the DC voltage superimposed onto the IF and baseband signals occurring as a side effect of the downconversion and the A-D conversion process. If left uncorrected, the added DC voltage will result in erroneous data I and Q channel data values and a degraded receiver bit error rate (BER).

[0022] What is needed is a new CDMA receiver architecture which remedies the aforementioned shortcomings of the conventional CDMA receiver. Specifically, a new CDMA receiver is needed which can discriminate and remove AMPS interfering signals and other correlated signals from the received signals. Also needed is a CDMA receiver architecture which employs low cost, highly manufacturable filters for providing the required out-of-band signal rejection and phase response. Further needed is a CDMA receiver architecture which consists of a single ADC for converting the IF signal to a digital data stream. Use of a single ADC will reduce the likelihood of introducing amplitude and/or phase imbalance between the I and Q channel data. Lastly, a new CDMA receiver architecture is needed which does not require the use of a DC offset source to correct for an superimposed DC voltage.

[0023] The present invention provides for a new CDMA receiver which uses digital noise cancellation circuitry to remove the AMPS interferer or any other highly correlated signal from the receiver during CDMA reception. The new CDMA receiver also employs less expensive, more manufacturable digital IC filters to provide the needed adjacent channel rejection and phase response necessary for proper I and Q data reconstruction. In addition, the new CDMA receiver uses a single ADC to convert the IF signal to a digital data stream containing orthogonally-phase I and Q data. Further, the new CDMA receiver employs IF sampling in the baseband conversion process to remove any superimposed DC voltage from the baseband data.

[0024] In one embodiment the CDMA receiver includes a RF amplifier, a downconverter, an analog to digital converter (ADC), a baseband conversion circuit, an I channel digital filter, a Q channel digital filter, an I channel digital noise cancellation circuit, and a Q channel digital noise cancellation circuit. The RF amplifier receives and amplifies and the downconverter downconverts the CDMA signal to an IF signal having an AMPS interfering component. The ADC receives and converts the CDMA+AMPS interfering signal to digital data. The baseband conversion circuit use an IF sampling technique to remove any superimposed DC voltage from the digital data by alternatively negating output data words and subsequently adding data word pairs together, thereby removing any commonly occurring magnitude. The AMPS interfering component is reduced by the noise cancellation circuitry which detects and removes highly correlated signals, such as the AMPS signal.

[0025] A further understanding of the nature and advantage of the invention herein may be realized by reference to the remaining portions of the specification and attached drawings.

[0026] FIG. 1 illustrates the block diagram of a conventional CDMA receiver known in the art.

[0027] FIG. 2 illustrates the block diagram of a new CDMA receiver architecture in accordance with the present invention.

[0028] FIG. 3 illustrates an exemplary embodiment of the gain control circuit in accordance with the present invention.

[0029] FIG. 4 illustrates an exemplary embodiment of the baseband circuit in accordance with the present invention.

[0030] FIG. 5 illustrates an exemplary embodiment of the noise cancellation circuit in accordance with the present invention.

[0031] FIG. 6 illustrates an exemplary embodiment of the rake receiver in accordance with the present invention.

[0032] FIG. 2 illustrates one embodiment of the CDMA receiver in accordance with the present invention. The new CDMA receiver 200 includes a RF amplifier 210, a downconverter 220, an AGC circuit 230, an ADC 240, a gain control circuit 250, a digital baseband conversion circuit 260, I and Q channel digital filters 262 and 264, I and Q channel digital noise cancellation circuits 272 and 274, and a rake receiver 280.

[0033] In operation, the receiver 200 receives a CDMA signal 202 and an AMPS signal 204. The RF amplifier 210 receives and amplifies the received AMPS and CDMA signals 202 and 204. In its preferred embodiment, the RF amplifier 210 is a FET-based LNA designed to operate either in the PCS-band (1931.25 MHz-1988.75 MHz) or the cell-band (869.04 MHz-893.9 MHz), as described in the co-pending patent application Ser. No. 09/113,603, “AN IMPROVED CDMA TRANSCEIVER AND FREQUENCY PLAN, now U.S. Pat. No. 6,028,850” herein incorporated by reference.

[0034] Because of the inherent non-linearity of the RF amplifier 210, the RF amplifier generates an in-band AMPS interferer in addition to the amplified CDMA signal at the RF amplifier output 215 (CDMA+AMPS interferer). The RF amplifier 210 is chosen to have a high degree of linearity so as to minimize the amplitude of the generated AMPS interferer.

[0035] The CDMA+AMPS interferer signal 215 is supplied to a downconverter 220. In response, the downconverter 220 produces an IF signal 225 which retains a portion of the AMPS interferer. In its preferred embodiment, the downconverter 220 is a two-stage super-heterodyne downconverter, as described in the aforementioned co-pending patent application Ser. No. 09/113,603, now U.S. Pat. No. 6,028,850, “AN IMPROVED CDMA TRANSCEIVER AND FREQUENCY PLAN.”

[0036] An AGC circuit 230 receives the IF signal 225 containing both the CDMA and AMPS interferer components, and provides a signal gain to produce an AGC output signal 235. In the preferred embodiment, the gain of the AGC circuit 230 ranges from −45 db to +45 dB. The gain is controlled by a control signal 259 received from a gain control circuit 250, further described below.

[0037] The AGC output signal 235 is supplied to a single ADC 240. The ADC 240 converts the AGC output signal 235 to digital data, which in the preferred embodiment is a stream of 10-bit data words, each data word having a value ranging from +511 or −512. In the preferred embodiment, the ADC 240 outputs an even number of 10-bit data words every correlation period.

[0038] The ADC 240 is designed to have an input amplitude range which will result in an unclipped data word, i.e., the produced data word does not exceed beyond the range of +511 or −512 in magnitude. The input amplitude calculation takes into account the most statistically probable amplitude of the AMPS interferer signal. In the preferred embodiment, the ADC 240 is designed with an input amplitude range which will produce unclipped data 99.7% of the time (called “3σ” statistics). Accordingly, the gain of the AGC amplifier 230 is controlled so that the total signal amplitude (CDMA+AMPS interferer) supplied to the ADC 240 is within this desired “3σ” amplitude range.

[0039] To control the amount of gain and signal amplitude output from the AGC circuit 230, the ADC 240 communicates the input level it senses to a gain control circuit 250. In response, the gain control circuit 250 generates a gain control signal 259 which it sends to the AGC circuit 230 to alter its gain up or down.

[0040] FIG. 3 illustrates one embodiment of the gain control circuit 250. The gain control circuit 250 includes a signal delay 251, absolute value operators 252aand 252b, an adder 253, a clip threshold generator 254, a comparator 255, a clip counter 256, a pulse density modulator 257, and a loop filter 258.

[0041] During operation, a 10-bit data word 241 is generated at the output of the ADC 240 and supplied to two branches of the gain control circuit 250. A first absolute value operator 252adetermines the magnitude of the current data word. A second absolute value operator 252bmeasures the magnitude of a previous data word using a signal delay 251. A magnitude which is too large indicates the ADC circuit 240 is close to clipping and the input signal strength is too high. A magnitude which is too small indicates that the signal-to-quantization noise ratio is low and that more input signal strength is needed. The magnitudes of the current and previous data words are averaged by means of an adder 253 and supplied to the non-inverting terminal of the comparator 255.

[0042] A clip threshold value 254 is supplied to the inverting terminal of the comparator 255. The clip threshold value 254 is set to the magnitude above which a predefined number of data words will exceed during a predefined interval. In the preferred embodiment, the clip threshold value 254 corresponds to a data word magnitude (approximately 509) which will result in 30-50 clipped signals over a 10,000 word period. Thus, the gain control circuit 250 will attempt to stabilize the gain of the AGC circuit 230 so that the ADC circuit 240 will clip 30-50 data words out of 10,000 data words. In the exemplary embodiment of FIG. 3, the clip threshold value 254 is approximately twice the value of each 10-bit data word since two 10-bit data words are added and used in the comparison.

[0043] When the magnitude of the added data words exceeds the magnitude of the clip threshold value 254, the comparator 255 increments a clip counter 256. After a predetermined period, the clip counter 256 supplies its accumulated count to a pulse density modulator 257. In response, the pulse density modulator 257 generates a number of pulses within a predefined pulse period, the number of pulses corresponding to the number of counts received from the clip counter 256. If the number of clip counts is small, only a few pulses are generated, and the resulting pulse density is low. If the number of clips is large, a large number of pulses are generated and the resulting pulse density is high.

[0044] The pulse density is supplied to a lowpass filter (LPF) 259. The LPF 258 operates as a simple DAC to produce a average value DC voltage. The averaged value DC voltage functions as the gain control signal 259 and is supplied to the AGC circuit 230. The voltage is used to control the AGC circuit to increase or decrease the signal gain and accordingly the output signal strength of the AGC signal 235.

[0045] Other gain control circuits are possible. For instance in an alternative embodiment, the gain control circuit 250 may sample the AGC signal 235 prior to its injection into the ADC. The gain control circuitry 251-259 described above may be realized in analog or digital-based circuitry and fabricated in either IC or discrete form. In the preferred embodiment, the signal delay 251, the absolute value operators 252aand 252b, the adder 253, the clip threshold source 254, the comparator 255, the clip counter 256, and the pulse density modulator 257 are IC CMOS digital circuits and the loop filter 258 is an external RC low pass filter.

[0046] The ADC output 242 is supplied to the baseband conversion circuit 260 which, in response, produces I and Q channel data 260iand 260q.The baseband circuit 260 together with the rake receiver 280 removes any DC voltage which may have been added to signal during the downconversion and A-D conversion operations.

[0047] FIG. 4 illustrates one embodiment of the baseband conversion circuit 260 as a quadrature downconverter (QDC) circuit. The QDC 260 operates as a digital downconverter to convert the ADC data 242 to I and Q channel baseband data 260iand 260q.Additionally, the QDC 260 performs a first IF sampling operation to remove the superimposed DC voltage level from the ADC data 242 by alternatively negating the I and Q channel data words. The rake receiver 280 performs a second operation on the alternatively negated data words to remove the DC voltage from the magnitude of the data words, as will be described below.

[0048] In operation, the QDC 260 spectrally shifts the ADC output 242 by exactly negative one-fourth of a provided sampling frequency, dividing the ADC output 242 into in-phase (I channel) and quadrature phase (Q channel) data 260iand 260q. In the preferred embodiment, the QDC 260 consists of a signal delay 261, negation circuits 262 and 263, and I and Q channel multiplexers 264 and 265. It is further preferred that a sampling source 266 operates at 8 times the ADC data rate (1.2288 MHz) or 9.8304 MHz. A one-half frequency divider 267 is used to convert the 9.8304 MHz sampling signal to 4 times the ADC data rate or 4.9152 MHz.

[0049] The QDC 260 receives the ADC output 242 and produces I channel data 260idescribed by eq (1):

[0050] Idata=[ADC output]* cos (¼*2Π*fs*t_w+θ) and Qchannel data 260qdescribed by eq (2):  (1)

[0051] Qdata=[ADC output]* −sin (¼*2Πfs*t_w+θ)  (2):

[0052] Where

[0053] fs=sampling frequency

[0054] t_w=word period

[0055] θ=word phase

[0056] One possible realization of the I channel cos multiplier is the sequence: 1, 0, −1, 0, . . . The Q channel −sin multiplier similarly produces the sequence 0, −1, 0, 1, . . . Thus, the QDC 260 operates to multiply the ADC output data 242 by zeros and ±1 for successive data words. By way of an example, if a, b, c, d are successive data words output from the ADC 242 during one sample period, the I channel output data 260ibecomes: a, 0, −c, 0. The Q channel output data 260qbecomes: 0, −b, 0, d. Further, since the ADC 240 is sampled at greater than twice the Nyquist rate needed for recovering all of the information, half of the output data (the zero value data) may be decimated without loss of information. The I channel data 260ibecomes: a, −c, and the Q channel data 260qbecomes: −b, d. Collectively, all of the information is retained (a, b, c, and d), but the data words in each I and Q channels are alternately negated. The alternating signs of the I and Q channel data words are used by the rake receiver 280 to remove any DC voltage level which may persist in the magnitude of the data words, as will be described below.

[0057] The I and Q channel data words 260iand 260qare subsequently supplied to I and Q channel digital filters 262 and 264, respectively. The digital filters 262 and 264 are designed to remove adjacently occurring out-of-band interference from the data words and are preferably fabricated using CMOS IC processing. CMOS IC processing allows for a more reliable, less expensive fabrication process compared to the analog baseband filters 152 and 154 of the conventional CDMA receiver. Additionally, each filter's rejection and phase response may be tightly controlled using IC design techniques as conventionally known. The filters 262 and 264 are preferably 6th order digital elliptic low pass filters exhibiting 60 dB of rejection at 933 KHz.

[0058] The filtered I and Q channel data words 260iand 260qare supplied to I and Q channel noise cancellation circuits 272 and 274, respectively. The noise cancellation circuits 272 and 274 are used to remove the AMPS interferer from the I and Q data words 260iand 260qprior to signal processing. Each of the noise cancellation circuits 262 and 264 operate to remove highly correlated signal components from the data words. The CDMA data component is pseudo-random and uncorrelated, and as such is not attenuated by the noise cancellation circuits. In contrast, the AMPS interferer data component is highly correlated in nature. The noise cancellation circuits identifies and removes the highly correlated AMPS interferer component, leaving only the CDMA component of the output data word.

[0059] FIG. 5 illustrates one embodiment of the I and Q channel noise cancellation circuits 272 and 274. Each noise cancellation circuit includes a decimate-by-4 circuit 272a,a linear adaptive predictor 272b,adders 272cand 272f,a weight update circuit 272d,an interpolate-by-4 circuit 272e,and a delay circuit 272g.

[0060] In operation, the I and Q channel data words 260iand 260qhaving the AMPS interferer and CDMA components is received along the I and Q channel paths as shown in FIG. 2. A decimate-by-4 circuit 272aeliminates 3 of the 4 data words every period, outputting one data word per period. The reduction in the number of data words results in the CDMA component appearing unpredictable. However, one data word per period for the AMPS interferer does not render it unpredictable. In the preferred embodiment where the I and Q channel data words 260iand 260qare supplied from the baseband conversion circuit 250 at a rate of 4.9152 MHz, the decimate-by-4 circuit 272areduces the effective sampling rate by a factor of 4 to 1.2288 MHz. This effective sampling rate is still quite large compared to the AMPS data rate (30 KHz), resulting in the AMPS interferer component being sampled over 40 times during one sampling period. Because the AMPS interferer component is highly oversampled, its signal behavior can be accurately predicted.

[0061] The decimated CDMA+AMPS data word is fed into the linear adaptive predictor 272b.The CDMA component is insufficiently sampled to allow prediction, thus the predictor 272bdoes not operate upon it. The AMPS interferer is highly predictable and the predictor 272boperates upon the AMPS component, predicting the next occurring AMPS component. The predicted AMPS component is negated and supplied to an adder 272c,subtracting it from the next occurring decimated AMPS+CDMA word. The difference is fed to a weight update circuit 272d.Assuming the CDMA component is not predictable, the difference generated by the adder 272cwill be due solely to the error of the predictor 272bin predicting the AMPS component. The weight update circuit 272dreads the difference between the predicted AMPS component and actual AMPS component and tunes the predictor 272bto minimize the error between the two during the next sample period. The predictor 272bis thus constantly updated with the most recent comparison to accurately predict the next occurring word sample.

[0062] The predicted AMPS component is also routed to the interpolate-by-4 circuit 272e.The interpolate-by-4 circuit 272elinearly interpolates the AMPS component to a reconstructed version of the AMPS interferer component having the original 4 samples per period. The linearly interpolated original length AMPS interferer is negated and added to a delayed version of the AMPS+CDMA word using an adder 272f,resulting the difference between the two words. A signal delay 272gis used to delay the AMPS+CDMA word L sample periods which allows the predictor 272bto accurately predict and construct the AMPS interferer component. The adder 272foutputs only the CDMA component of the CDMA+AMPS word to the receiver output. The process is repeated every 10-bit word in succession until the entire word stream has been processed. This processing is performed in parallel on the I and Q channels, producing AMPS-attenuated I and Q channel data words 270iand 270q.

[0063] The AMPS-reduced I and Q data 270iand 270qis supplied to the rake receiver 280. As explained above, the rake receiver 280 operates with the QDC 240 to remove any DC voltage level which may persist in the magnitude of the data words. FIG. 6 illustrates one embodiment of the rake receiver 280 which includes I and Q channel PN code generators 282iand 282q,correlators 284iand 284q,accumulators 286iand 286q,and registers 288iand 288q.

[0064] In operation, the I and Q channel correlators 284iand 284qreceive the I and Q channel data 270iand 270qand I and Q channel PN codes from the PN code generators 282iand 282q.Typically, the PN code generators 282iand 282qgenerate random sequences of 1 and 0 which have a high degree of correlation with I and Q channel data 270iand 270qintended for the receiver. The present invention uses PN codes consisting of sequences of 1 and −1 to determine correlation with the incoming I and Q channel data having positive and negative values.

[0065] The resulting I and Q channel correlations are supplied to accumulators 286iand 286q.There, the I and Q correlated values are compared with a predefined threshold value. When the I and Q channel correlations are greater than the threshold value indicating a high degree of correlation, a match is indicated and the I and Q channel data is stored in registers 288iand 288qfor further processing. If the I and Q channel correlations are less than the threshold value, a low correlation is indicated. In this case, the I and Q channel data is discarded and the next sequence of data words is processed during the next sampling period to determine if a high correlation exists.

[0066] The magnitude and sign of the I and Q channel data words 270iand 270qallow the extraction of a constant DC offset encoded within the data words. As explained above, the AMPS interferer component is effectively reduced or eliminated at this point in the processing, leaving only the superimposed DC voltage as the remaining error. The correlators 284iand 284qprocess an even number of data words during one sample period. As shown above, the QDC 260 produces data words, one-half of which are negative, and the other half being positive. If the I and Q channel data words 270iand 270qare highly correlated with the local I and Q channel PN codes 282iand 282q, the accumulators 286iand 286qwill retain the negative and positive data words. Since an equal number of data words are assigned positive and negative values of equal magnitude (±1), adding the data words removes any commonly occurring offset therebetween. In this manner, any DC offset signal is removed from each of the I and Q channel data 270iand 270qduring the accumulation period. The rake receiver 280 outputs the corrected data 280iand 280qfor further signal processing as required.

[0067] The above described CDMA receiver may be used as a dedicated CDMA receiver, for instance, in PCS-band systems where AMPS signals appear only as interference, or as a dual mode CDMA/AMPS receiver in which the receiver is capable of processing both AMPS and CDMA signals in addition to removing the AMPS interferer when receiving CDMA data. In the later case, the CDMA receiver will include correlation circuitry (not shown) coupled to the output of the digital filters 262 and 264 which controllably bypasses the noise cancellation circuitry 272 and 274 when AMPS signal processing is desired. The correlation circuitry may include, for instance, a carrier lock loop and/or a delay lock loop, the preferred embodiments of which are described in the co-pending provisional application No. 60/092,374 “A VARIABLE CLOCK RATE CORRELATION CIRCUIT FOR A CDMA RECEIVER AND METHOD OF OPERATION,” herein incorporated by reference. Of course, those skilled in the art will appreciate that other AMPS receiver circuitry may be coupled at various locations to the CDMA receiver shown in FIG. 2 to detect and process AMPS signals.

[0068] While the above is a complete description of the preferred embodiments of the invention, various alternatives modifications and equivalence may be used. It should be evident that the present invention is equally applicable by making appropriate modifications to the embodiments described above. Therefore, the above description should not be taken as limiting the scope of the invention which is defined by the metes and bounds of the appended claims.