Converter including a fly-back circuit

[0002] This invention relates to a converter including a fly-back circuit.

[0003] The converter according to the invention is preferably used as a part of a switching power supply in entertainment electronics devices.

[0004] U.S. Pat. No. 4,683,529 describes a switching power supply including a fly-back circuit and a control circuit for power factor correction. The switching power supply converts a line voltage into a regulated DC output voltage and is adapted for operation with different line voltages and line voltage frequencies which vary internationally. The control circuit controls the switching transistor of the fly-back circuit by means of a pulse width modulated control signal having a suitable frequency, so that the fly-back circuit operates on the borderline between continuous and discontinuous operation to minimize the switching losses. Furthermore, the switching power supply provides a high power factor under various mains and load conditions.

[0005] It is an object of the invention to provide a converter including a fly-back circuit (i.e. high frequency boost converter) arranged so that an optimum adaptation to the internationally different line voltages is achieved.

[0006] This object is achieved in that with a converter input voltage that lies in a first voltage range a first fly-back switching frequency range is provided and in that with a converter input voltage lying in a second voltage range a second fly-back switching frequency range is provided, the first voltage range having lower voltage values than the second voltage range and the first fly-back switching frequency range having higher frequency values than the second fly-back switching frequency range.

[0007] In this way the internationally different EMI requirements (Electro Magnetic Interference) in Europe and the USA for entertainment electronics devices are satisfied by a respectively adapted selection of the fly-back switching frequency ranges. This arrangement leads to switching power supplies that have small dimensions and little weight.

[0008] The inventive idea is more particularly realized in that the converter operates discontinuously in the second voltage range and in that approximately the same top limit for the current is provided by the fly-back inductance both during operation in the first voltage range and during operation in the second voltage range. More particularly, the converter operates in the boundary region between continuous and discontinuous operation in the first voltage range and under full load, whereas the converter operates discontinuously in the first voltage range and under partial load, and the converter operates discontinuously in the second voltage range both under fall load and under partial load.

[0009] In another embodiment of the converter according to the invention a first capacitor supplies the supply voltage of an integrated switching circuit which is used for supplying the control signal for the fly-back switching element and the first capacitor is coupled to a node between the fly-back inductance, fly-back switching element and fly-back diode via a second capacitor and a further diode via which the first capacitor is charged in the manner of a charge pump. This measure guarantees the voltage supply of the integrated circuit via simple circuit modifications.

[0010] In another circuit variant a circuit block is connected to the node between the fly-back inductance, the fly-back switching element and the fly-back diode and produces a signal for the recognition of the zero state of the current through the fly-back diode and/or the state of the minimum voltage on the switch. The signal thus supplied can be used for determining the optimum instant for turning on the fly-back switching element, so that the switching losses are minimized.

[0011] The transition from the first to the second operating mode (i.e. first voltage range to second voltage range) is preferably effected continuously.

[0012] Examples of embodiment of the invention will be further described hereinafter with reference to the drawings in which:

[0013] FIG. 1 shows a converter according to the invention,

[0014] FIG. 2 shows a control unit for the converter according to the invention,

[0015] FIGS. 3 to 5 show time diagrams of a current flowing through the fly-back coils of the converter and a voltage V_T, and

[0016] FIG. 6 shows a diagram which shows the connection between the minimum turn-off time and the converter input voltage.

[0017] In the (AC/DC) converter 1 shown in FIG. 1, a line voltage U_netis converted into an output voltage U_out, which is used for supplying power to a load 2. The line voltage U_netis first applied to a circuit block 3 operative as an input stage, which includes filter circuits 3aand 3b, a rectifier arrangement 3cand a voltage limiting circuit 3d. On the output of the input stage 3arectified voltage U_in, which in good approximation can be described as a sequence of positive sine half-waves, is produced while the converter 1 is in operation. The voltage U_inis supplied to a fly-back circuit 5 which normally comprises an inductance L, a switch/switching element S (arranged here as a MOSFET transistor) and a diode D. The current flowing through the inductance L is referenced I_L. The control input of the switch S, i.e. the gate electrode of the MOSFET transistor used as a switch, is connected to a respective output referenced Gate of a control unit 6. The operation of the control unit 6 will be discussed in more detail hereinafter with reference to FIG. 2.

[0018] In parallel with the output of the fly-back circuit 5 is connected a capacitor C_outfone terminal of which is coupled to a terminal of the output capacitor C_outvia a resistor R_inrush. The resistor R_inrushis used for limiting the current derived by the converter from the mains supplying the voltage U_net. This is accompanied by fewer losses than with customary current limitation by means of an NTC resistor connected on the input side of the converter 1. The other two terminals of the capacitors C_outfand C_outare both connected to zero potential (ground potential). At the capacitor C_outfthe output voltage U_outis tapped. The capacitor C_outis used for reducing the ripple of the DC output voltage U_outand for deriving the high-frequency portions of the output current of the up-converter and thus for further reducing the losses in the resistor R_inrush.

[0019] A voltage V(t) applied between the voltage limiter 3dand the filter circuit 3b(which applied voltage V(t) filtered by the filter circuit 3bprovides the voltage U_in) is applied to a respective input of the control unit 6. For the case where the filter circuit 3bis lacking, which circuit is not absolutely necessary within the framework of the invention, the voltage U_inwould be applied to the input V(t) of the control unit 6. The voltage V(t) is further applied to a series combination comprising a resistor R_senseand a capacitor C_sense, which is used for generating a voltage V_rmsfrom the voltage V(t). This voltage corresponds to the mean value of the rectified line voltage and furthermore represents a good approximation of a parameter for the effective value of the input voltage. The voltage value V_rmscorresponding to this effective value is tapped from the capacitor C_senseand applied to the input referenced V_rmsof the control unit 6.

[0020] A resistor R_shuntis used for measuring the current flowing through the switch S. A voltage having a voltage drop at this resistor R_shuntis applied to an input CS of the control unit 6 as a measuring quantity that corresponds to the current flowing through the switch S.

[0021] An input ZV/ZCS of the control unit 6 is used for receiving a signal by the aid of which a ZVS mode (Zero Voltage Switching, turning the switch S on with zero voltage or at least the smallest possible voltage) or ZCS mode (Zero Current Switching, turning the switch S on with a zero current in the diode D) is reached. The terminal ZV/ZCS is connected both to the terminal of the capacitor C_dv/dtlying across from the node between the inductance and the diode D, and from the cathode of the diode D_cp1, the anode of the diode D_cp1being connected to the node between the switch S and the resistor R_shunt, which node is connected to the terminal CS.

[0022] The cathode of the diode D_cp1is further connected to the anode of a diode D_cp2whose cathode is connected to the cathode of a zener diode D_z, whose anode again is connected to zero potential. In parallel with the zener diode D_zis further connected a capacitor C_buf. The voltage V_supplyis used as the supply voltage for the control unit 6 and is applied to an accordingly referenced input of the control unit 6.

[0023] Two terminals FB and COMP of the control unit 6 are coupled to a circuit block 7 (see FIG. 1) which evaluates the output voltage U_out. This circuit block contains two resistors R₁and R₂arranged as a voltage divider, on which the output voltage U_outis present. The node between the resistors R₁and R₂is connected via the resistor R₃to the terminal FB (FeedBack input) of the control unit 6. The terminal FB is further coupled to the terminal COMP via a parallel circuit comprising three branches, one of the parallel branches including a capacitor C₁, another branch including a resistor R₄and the third branch including a series combination of a resistor R₅and a capacitor C₂. Furthermore, two diodes not further referenced which have a forward direction in the direction of the terminal COMP are connected in parallel with the capacitor C₂. The circuit block 7 determines the control behavior of the control unit 6. More particularly, the components combined by the circuit block 7 are dimensioned so that the control unit 6 shows the behavior of a PI controller with limited DC voltage gain.

[0024] FIG. 2 shows the structure of the control unit 6 by which circuit portions combined in a block 9 are realized by means of a commercially available controller IC (UCC3807). A flipflop 10 delivers a control signal applied to a terminal referenced Gate and to the control input of the switch S. The flipflop 10 is triggered by a further flipflop 11. The RESET input of the flipflop 10 is connected to the output of a comparator 12 whose one input (+) is connected to a terminal CS and whose other input (−) is connected to the output of an error amplifier 13 and the terminal COMP. A voltage superimposed by a reference voltage Vref and present on a terminal FB is applied to the input of the amplifier 13. As soon as the voltage value present on the terminal CS, which value—as stated above—is equivalent to the current flowing through the switch S, exceeds the voltage value present on the terminal COMP or on the output of the amplifier 13 respectively, the flipflop 10 is reset and a respective turn-off signal is applied to the switch S via the terminal Gate.

[0025] On the inputs of the flipflop 11 are present the output signals of two comparators 14 and 15 i.e. on the reset input the output signal of the comparator 14, on the set input the output signal of the comparator 15. The positive input of the comparator 14 is connected to the negative input of the comparator 15. The two other comparator inputs are coupled to a series combination of three resistors R₆, R₇and R₈which combination is connected on one side via a terminal of the resistor R₈to ground potential and on the other side via a terminal of the resistor R₆to a terminal of a resistor R_supf, whose other terminal is connected to the supply voltage terminal V_supplyof the control unit 6. The node between R₆and R_supfis referenced A. A zener diode D_ziconnects the node A to ground potential. Between the two resistors R₆and R₈lies the resistor R₇. The node between the resistors R₆and R₇is connected to the negative input of the comparator 14. The node between the resistors R₇and R₈is connected to the positive input of the comparator 15.

[0026] The terminal ZV/ZCS is coupled via a resistor R_restartto ground potential. Furthermore, between the terminal ZV/ZCS and the node A lies the series arrangement of a resistor R_clipand a diode D_clipwhose cathode is connected to the node A. The anode of the diode D_clipis connected to the anode of a diode D_ZVCCS, whose cathode is connected to a terminal of a resistor R_ZVS1. Between the cathodes of the diodes D_clipand D_ZVZCSis arranged a capacitor C_ZVS. Furthermore, between the other terminal of the resistor R_ZVS1and ground potential there is a resistor R_ZVS2.

[0027] The node between the two resistors R_ZVS1and R_ZVS2is connected, on the one hand, to the negative input of the comparator 15 and, on the other hand, to the emitter of an npn bipolar transistor T_ZVZCS. A collector of the transistor T_ZVZCSis connected to the potential of the node A. The base of this transistor (node B) is connected to a terminal of a capacitor C_Twhose other terminal is connected to ground potential. Between a node C and the node B lies in forward direction from node C to node B a diode D_bypand in parallel with this diode D_bypa resistor R_toffmax. Furthermore, the node C is connected to a resistor R_toffmim, whose other terminal is connected to the collector of a pnp bipolar transistor T_trip. The emitter of the transistor T_tripis connected to the node B.

[0028] The base of the transistor T_tripis connected to the anode of the diode D₁. The cathode of the diode D₁is connected to a terminal of a resistor R_tonmax, whose other terminal is connected to the terminal V_rms. Between the cathode of the diode D₁and the node C lies a resistor R_tip. Between the node C and the terminal V(t) lies a resistor R_tonmin. The terminal V(t) is further connected to one terminal of a resistor R_boot, whose other terminal is connected, on the one hand, to the cathode of a diode D₂and, on the other, to one terminal of a capacitor C_buf1. The other terminal of the capacitor C_buf1is connected to ground potential. The anode of the diode D₂is connected to the node C.

[0029] By means of the control unit 6 the time durations t_onmaxand t_offmin(see FIGS. 3 to 6 ) are automatically set to suitable values. The values are determined by a suitable selection of the capacitor C_T, the resistor R_tonmax, the resistor R_tomin, the resistor R_toffmaxand the resistor R_toffmin. By means of the transistor T_ZVZCSthe capacitor C_Tis decoupled from the circuit portions D_ZVCS, R_ZVS1and R_ZVS2which effect the ZVS and ZCS behavior.

[0030] In the turned-on state of the switch S, the flipflop 10 applies to the terminal Gate a control signal which has a high signal level for turning the switch S on. The flipflop 10 is then accordingly triggered by the flipflop 11. At the beginning of such a phase the voltage on capacitor C_Tis about one third of the supply voltage V_supplyplus the forward voltage V_Fwhich drops at the base-emitter path of the transistor T_ZVZCS. At the terminal Gate there is a turn-on signal until the voltage on the capacitor C_Texceeds the upper trigger level i.e. the threshold having magnitude ⅔V_supply+V_F. The turn-on signal is switched off when the current in the resistor R_shuntand thus the voltage on the terminal CS of the control unit 6 exceeds a value that is determined by the voltage on the terminal COMP of the control unit. The rise of the voltage on the capacitor C_Tis then determined by the magnitude of the voltages V_rmsand V(t). The time constant belonging to this charging process is determined by R_tonmax, R_tripand R_tonmin. During the charging of the capacitor C_T, the resistors R_toffminand R_toffmaxare shunted by the diode D_bypand accordingly have no influence on this charging process. Furthermore, during the charging of C_T, the diode D_byphas the object to prevent the transistor T_tipexperiencing a positive collector-emitter voltage and prevent the node C being set to the supply voltage via the anti-latch-up diode D₂. In this case the time interval t_onmax(compare the explanations of FIGS. 3 to 5 ) would no longer be a function of the voltages V_rmsand V(t). The terminal between t_onmax, V(t) and V_rmsmay roughly be approximated by the formula $t_{\mathrm{onmax}}\cong \frac{k_1}{k_{2}V\left(t\right)+V_{\mathrm{rms}}}$

[0031] with k₁and k₂as constants. The time interval t_onmaxcalculated from a respective start of a switching cycle (at which the switch S is turned on) is the maximum time during which the switch S can be turned on. The switch S is turned off already when the current flowing through the switch S exceeds a certain limit value i.e. when the voltage decreasing on resistor R_shuntand present on the input CS of the control unit 6 becomes greater than the voltage present on the input COMP of the control unit 6. In this manner, the transmitted power of the converter is regulated. The fact that the time period t_onmaxdepends both on the time-independent magnitude V_rmsand on the time-dependent magnitude V(t) according to the above-defined function, limits, on the one hand, the smallest possible switching frequency of the switch S and, on the other hand, causes a more trapezoidal pattern of the current I_netto occur, which leads to a smaller part of low-frequency harmonics present in the current drawn from the converter.

[0032] After the said upper trigger level has been exceeded, the capacitor C_Tis discharged via the resistors R_toffminand R_toffmaxand a switch of the control unit 6 which is not further referenced. During the discharge operation, the voltage on capacitor C_Tdrops from ⅔V_DD+V_Fto ⅓V_DD+V_F. As long as the voltage on capacitor C_Tlies more than 233 V_Fabove the value on the anode of D₁(trip level), the transistor T_tripis conductive, so that the parallel circuit of the resistors R_toffminand R_toffmaxis active with respect to the discharging of C_T. If the converter works in the mains voltage range of 220 V, the voltage on the anode of D₁during the discharging of C_Tlies above ⅔V_supply+2×V_F. This is understood to mean that the transistor T_tripis never turned on and the discharge time of C_Tis only determined by R_toffmax.

[0033] With mains input voltages in the range of 110 V, the voltage on the anode lies below ⅓V_supply+2×V_F. In this case T_tripis turned on during the whole discharging phase which takes place between ⅓V_supply+V_Fand ⅔V_supply+V_F.

[0034] The maximum possible switching frequency with which the switch S is operated depends, on the one hand, on the time period t_onmaxand, on the other hand, on the time period t_offmin. The former time period depends on the time-dependent voltage V(t) and thus the instantaneous value of the converter input voltage U_net. t_offminis not time-dependent and depends only on the voltage V_rmsand thus on the voltage amplitude or effective value respectively, of the input voltage U_net(but not on its instantaneous value). Accordingly, the range in which the switching frequency of the switch S lies while a predefined converter input voltage is U_net, only depends on V_rms. FIG. 6 shows the connection between U_netand t_offminand clarifies that t_offminin a first range of rather small converter input voltages U_netwith voltage amplitudes around 110 Volts (in the present example having an upper range limit of 130 volts) is set to a small value of t_offmin(here 0.6 μs), so that the converter operates in a first switching frequency range with accordingly high frequencies. On the other hand, t_offminin a second range of rather large converter input voltages U_nethaving voltage amplitudes around 230 Volts (in the present example having a lower range limit of 200 volts) is set to a large value of t_offmin(here 6.5 μs), so that the converter operates in a second switching frequency range with low switching frequencies.

[0035] The minimum switching frequency is reached with V(t)=0 and thus with a maximum value of t_onmax, which is proportional to 1/V_rms. The maximum switching frequency appears with the maximum value of V(t) and thus a minimum value of t_onmax. Therefore, with the converter according to the invention, the switching frequency range (i.e. upper and lower switching frequency limit) is shifted to lower frequencies when the value of V_rmsrises and to higher frequencies when the value of V_rmsdrops. With the converter according to the invention it is possible to automatically adapt the switching frequency range, so that different EMI conditions, such as, more particularly used in entertainment electronics devices in Europe and the USA are satisfied. For example, the converter according to the invention can be dimensioned so that with a line voltage in the region of 230 volts, which is customary in Europe, it is set to switching frequencies below 140 kHz (in accordance with the EMI regulations there) and with a line voltage in the area of 110 volts, which is customary in the USA, it is set to high switching frequencies in the area of 300 kHz (in the USA such high switching frequencies are permitted on the basis of different EMI regulations). The converter structure according to the invention then leads to smaller converter losses. The converter efficiency is increased over a wide input or line voltage range and the converter can be realized with a smaller weight and smaller shape.

[0036] ZS, ZVS, valley switching and power supply of the control unit 6:

[0037] To guarantee operation of the converter 1 with a highest possible degree of efficiency, the switch S is not to be turned on until the current flowing through the diode D has dropped to zero. Different from the customary realization of such a ZCS operation, and optionally also of a ZVS operation, i.e. different from changing over the switch S in the case of a switching voltage of (substantially) zero volts, a charge pump is used in the present converter, which pump is simultaneously used for supplying power to the controller ICs used for the control unit 6 (see below) and providing the gate charge of the switching transistor S.

[0038] After the switching transistor S has been turned off, the voltage V_Ton its drain terminal rises sharply. The load current of the switching transistor S shifts to the capacitor C_dv/dt. The current flowing through the capacitor C_dv/dtflows through the diode D_cp2to the capacitor C_buf—in accordance with the function of a charge pump. An overcharging of the capacitor C_bufis avoided by the zener diode D_z. The voltage of the capacitor C_bufis used as a supply voltage V_supplyfor the control unit 6. Normally, the voltage on the capacitor C_bufis never considerably smaller than the usual supply voltage of the control unit 6. The voltage on node D thus has about the value of the supply voltage exclusive of the voltage drop on the diode D_cp1.

[0039] By means of a filter arranged inside the control unit 6, which filter comprises the resistor R_supfand the capacitor C_buf1, the voltage V_supplyis additionally filtered.

[0040] If the voltage on the capacitor C_dv/dthas reached the level of the output voltage, the diode D becomes conductive. At that moment the current shifts from the diode D_cp2, C_bufor D_zrespectively, to the diode D. The voltage on node D now slowly drops with the comparatively long time constant which is determined by capacitor C_dv/dtand the resistor R_restartof the control unit 6 (FIG. 2). When the converter operates in a normal way, this does not have any effect on the manner of functioning. The current in the coil L now drops linearly because the output voltage of the converter, when operated according to its use, is always larger than the instantaneous value of the input voltage.

[0041] The diode D blocks when the current flowing through it has become zero. At that moment an oscillating process begins in the oscillation circuit comprising L and C_dv/dt. The capacitor C_dv/dtthen again discharges. The discharge current flows via R_{shunt, Dcp1}, C_dv/dtand L. The voltage on node D is then the negative forward voltage of the diode D_cp2exclusive of the voltage drop on resistor R_shunt.

[0042] The voltage on the connection from the capacitor C_dv/dtto the diode D and the coil L then oscillates around the value of the input voltage. More particularly, when the input voltage is smaller than half the output voltage, the voltage on the capacitor C_dv/dtoscillates to zero. The oscillation process is continued until the switch S is turned on again. The processes in the charge pump then again correspond to the processes when the switching transistor S is turned off.

[0043] In the present circuit there is a substantially square-shaped voltage on node D, whose value is in essence equal to the supply voltage plus a forward voltage of the diode applied to the control unit 6 when the voltage on the switching transistor S rises or the diode D is conductive, and which is, in essence, equal to a negative forward voltage of the diode when the voltage on the switching transistor S drops or is zero.

[0044] This square-wave voltage is applied via the resistor R_clipto the cathodes of the two diodes D_clipand D_ZVZCS, which leads to the fact that the terminal on the R_ZVS1side of the capacitor C_ZVSis charged to the value V_supplywhen the voltage on node D has the upper value.

[0045] The voltage divider comprising the resistors R_ZBS1and R_ZVS2and the transistor T_ZVSnow provide a maximum function for half the value of the voltage on C_ZVSand for the voltage on the capacitor C_T, so that the controller IC cannot start a new switching cycle and turn on the switch S again until the two voltages have dropped below the value ⅓V_supply.

[0046] The value of C_ZVStogether with the values for R_ZVS1and R_ZVS2is selected so that after the change of the voltage on node D from the upper to the lower value, still half the period duration elapses that appears from a respective oscillation or resonant frequency coming from the resonant circuit elements L and C_dv/dt. At this instant the voltage V_Thas either the value zero (for the case where U_in<U_out/T), or drops to a minimum value.

[0047] The resistor R_restartnow prevents that in the event of high input voltages i.e. when the current in L takes a very long time to drop, that turning the switch S on again is delayed so much that there are switching frequencies in the audible range. Furthermore, this prevents that even if the detection of the turning-on again failed, the converter will stop its operation and not start again. Consequently, the time constant which is determined by C_dv/dtand R_restartis selected such that a minimum switching frequency of 20 kHz is not fallen short of.

[0048] When the converter 1 is being started, the capacitors C_buf1and C_bufare charged via the resistor R_boot. The converter is started when the minimum 12 volts start voltage of the control ICs 9 is reached. Then the resistors R_tonmaxand R_tonminsupport the starting process. Since these measures act in combination, the start time of 13 to 15 ms is achieved. Subsequently, the control IC 9 passes through a further soft starting phase which takes another 4 ms.

[0049] Furthermore, the converter having the described structure has rendered an additional power reserve available for mains or converter input voltages respectively that lie below the specified operating range. If the control unit 6 is in the state in which there is a turn-off control signal on the terminal Gate, because the turn-on condition (current in the diode D is zero, voltage on the capacitor C_dv/dtis zero or minimal) has not yet been satisfied, but the voltage on the capacitor C_Thas already dropped to ⅓V_supply+V_F, the capacitor C_Tis discharged further until the ZVS switching circuit again generates a turn-on signal on the terminal Gate. This occurs when the converter works with maximum power and a very small input voltage. This provides that the voltage on the capacitor C_Tis smaller than ⅓V_supply+V_Fat the start of the next cycle. Accordingly, the time interval t_onmaxfor the next cycle is longer than in normal operation. This leads to a momentary frequency drop and allows to briefly build up higher currents in the coil L than the dimensioning of the time-defining elements would actually allow. In this manner, a substantial increase of the maximum turn-on period t_onmaxmay be achieved (about 20 to 30% in the present converter circuit), which leads to the said additional power reserve for small line voltages U_net.

[0050] FIG. 3 shows the basic time diagrams of the current I_Land the switching voltage V_Tthat can be tapped from the node between the switch S, the inductance L and the diode D for the case of full load (maximum converter output power) and of a small input voltage in a first input voltage range (for example in the range around U_net=110 volts) are represented. At the instant to the switch S is turned on i.e. put in the conductive state. Until instant t₁the current I_Lthen linearly rises with the increase dI_L/dt=U_in/L up to the value I_I,max, while the instant t₁represents the instant at which the switch S is turned off. In the time space between t₀and t₁the voltage V_Tsubstantially keeps the zero value.

[0051] At the instant t₁the switch S is turned off. This leads to a steep rise of the voltage V_Thaving the slope I_L(t=t₁)/C_dv/dt, the upper limit of the slope being determined by the element properties of the switch S and the upper limit for the generation of electromagnetic disturbances. The value U_inis then exceeded by the voltage V_T. The current I_Ldriven along by the energy stored in the inductance L is diverted into the capacitor C_dv/dtafter the instant t₁.

[0052] At the instant t₂the voltage on the capacitor C_dv/dthas risen so far as to make the diode D conductive. This leads to a linear drop of the current I_Luntil instant t₃at which the diode D again adopts the blocking state. Between the instants t₂and t₃the switching voltage V_Tis constant and is equal to the voltage on capacitor C_outf.

[0053] At the instant t₃an oscillation of the voltage V_Tsets in around the drawn-in instantaneous value of the voltage U_in; the resonant circuit elements determining this oscillation are the inductance L and the capacitor C_dv/dt. At the next zero-crossing of the voltage V_T, the switch S is again turned on and a new cycle with the events described above for the time space between to and t₄begins. The switch S is turned on with a zero switch voltage V_Ti.e. a ZVS mode (Zero Voltage Switching) is ensured. Furthermore, turning on the switch S is effected with a current in the diode D of zero amperes (ZCS mode−Zero Current Switching). In consequence, high switching frequencies of the switch S are possible in the described mode of operation.

[0054] Furthermore, FIG. 3 shows two time intervals t_onmaxand t_offmin, where t_onmaxdenotes the maximum time interval for which the switch S can be turned on within a cycle. t_offmindenotes the minimum time interval in which the switch S must be turned off within a cycle. If from the beginning of a cycle (for example t=t₀) the time interval t_onmax+t_offminhas elapsed, the earliest permissible instant is reached at which the switch S is allowed to be turned on again and a new cycle may be introduced. The switch S is then turned on as soon as the voltage V_Thas reached the next zero-crossing. The value t_onmaxfollows the variation of the voltage U_inand can be selected so large as to have the current I_Lstill large enough with the smallest permissible value of U_in, to provide the maximum converter output power.

[0055] The converter is operated in critical fashion in the case according to FIG. 3. The switching frequency of the switch S depends, in essence, only on the input voltage and on the value of the inductance of the coil L and on the converter output power.

[0056] FIG. 4 shows the basic time diagrams of I_Land V_Tfor the case of a small input voltage (like in FIG. 3) and the case of partial load, in which the load present on the converter output is small (here about 10% of the nominal power). Contrary to the case represented in FIG. 3, the converter 1 works discontinuously. After the switch S has been turned off at instant t₁and a next zero-crossing of the voltage V_Thas been reached at instant t₄, since the beginning of the cycle (t=t₀) not so much time as denoted by the sum t_onmax+t_offminhas yet elapsed. Only when such a time space has elapsed can the switch S be turned on again. Since, accordingly, at instant t₄the switch S has not yet been turned off, the oscillation of V_T(activated oscillation circuit elements: L and C_dv/dt) started at instant t₂, is continued. V_T, however, cannot become negative here, because the switch S is arranged as a MOSFET transistor which even has an internal body diode (not shown) that blocks a dropping-off of the voltage V_Tto negative values, so that between the instants t₄and t₅the voltage V_Tis limited to the zero value. At the instant t₅the current I_Ioscillating since the instant t₃, which current has shown a negative half-wave in the area between t₃and t₅, begins to show a positive half-wave. At the instant t₅begins a positive half-wave of the voltage V_T, which half-wave ends at the instant t₆(at which the current I_Ijust has a negative half-wave), after which again a time space begins having V_T=0. At the instant t₆more time has elapsed since the beginning of the cycle (instant t₀) than denoted by the sum t_onmax+t_offmin, so that the condition for turning the switch S on again is satisfied. The switch is turned on, as described above, half a period duration after the current in D has become zero, thus about halfway between t₆and t₇. In the waveforms this becomes only visible when the current in the coil L has turned positive again, thus at instant t₇. In this manner, a ZVS or ZCS mode can ideally be realized. The losses occurring in the switch S and in the diode D are reduced to a minimum. The resulting switching frequency depends on t_onmaxand t_offminin the application as shown in FIG. 4.

[0057] FIG. 5 shows the basic time diagrams of I_Land V_Tfor the case of high input voltages in a second input voltage range (for example, in the range of U_net=230 volts) for all cases of load (full load and partial load).

[0058] Just like the cases shown in FIGS. 3 and 4, oscillations of the current I_Land of the voltage V_Toccur from an instant t₃onwards. The voltage V_Tagain oscillates around the voltage U_in, which adopts an accordingly larger value based on the higher converter input voltage U_net, so that V_Tno longer drops to the zero value. For minimizing the switching losses, the end of a switching cycle t₈and thus the turning-on again of the switch S is put in the next successive minimum of the voltage V_Tafter the time t_onmax+t_offminelapsed since the beginning of the cycle to.

[0059] In contrast to customary converters with a fly-back circuit structure in which, with a reduced converter input voltage, the critical operation is maintained (which leads to higher switching frequencies and a reduced maximum value of the current I_Lthat lies far below the saturation current I_L,sat), it is permitted with the converter according to the invention that during the phases in which the current I_Lrises, the switch S is turned on up to the saturation current I_I,satrepresenting the upper limit for the current I_L. The converter in this arrangement works discontinuously, so that a switching frequency reduction is effected.

[0060] The converter according to the invention provides a so-called power factor correction. The selected control principle to turn off the switch S when a current is reached, which current is determined by a regulator included in the control unit leads—considered per se—to a square-wave pattern of the input current I_net. This enables to realize powers up to several hundred watts without exceeding the permitted limits for the relative harmonic factor of the line current.

[0061] In the described converter, determining a minimum switching frequency together with the selected control principle additionally provides that the waveform of the line input current I_netis no longer square-shaped, but trapezoidal with rounded-off transitions. As a result, the harmonic content of the input current I_netis further reduced and much better performance in agreement with the respective line current regulations may be achieved.