Method of fabricating a dual metal gate having two different gate dielectric layers

[0002] This application claims the priority benefit of Taiwan application serial no. 89107440, filed Apr. 20, 2000.

[0003] 1. Field of Invention

[0004] The present invention relates to a method of fabricating integrated circuits. More particularly, the present invention relates to a method of fabricating a dual metal gate.

[0005] 2. Description of Related Art

[0006] In the present semiconductor manufacture processes, the integration required for integrated circuits is higher and the sizes of field effect transistors (FET) are smaller. When the size of the field effect transistor is less than 0.1 micron, the thickness of the gate oxide layer is less than about 20 Angstroms, that is, about six to seven layers of silicon oxide in a gate silicon oxide layer. Because the gate silicon oxide layer is pretty thin, electrons can easily diffuse through the gate silicon oxide layer and cause current leakage; furthermore, dopants might penetrate the gate silicon oxide layer through the defects and cause problems in electrical properties.

[0007] The thickness of the gate silicon oxide layer limits the size of the field effect transistor. In order to solve the problems caused by the gate silicon oxide layer, many dielectric materials with high dielectric constants are developed. These dielectric materials include: Ta₂O₅, Pb(Zr, Ti)O₃(PZT) and (Ba, Sr)TiO₃(BST), with dielectric constants of about 20-25 for Ta₂O₅, about 20-60 for BST and about 600-1000 for PZT.

[0008] However, a dielectric layer with a high dielectric constant cannot remain the original high dielectric constant, because a native oxide layer that has a lower dielectric constant is formed between the silicon substrate and the dielectric layer. This further influences the electrical performance of the minute transistor formed thereon.

[0009] As the thickness of the gate oxide layer decreases, poly depletion becomes more severe. Presently, metal gates replace polysilicon gates to prevent poly depletion and to reduce parasitic resistance. Moreover, the gate oxide layer in the peripheral region must be thicker than the gate oxide layer in the cell region, in order to increase breakdown voltage for outside circuit connections. In order to use dielectric materials with high dielectric constants for gate oxide layers in the metal gates, many difficulties must be overcome to achieve different thickness requirements for gate oxide layers in the cell region and the peripheral region and to increase the effective thickness of gate oxide layers for the high-integration IC manufacture process.

[0010] The invention provides a method of fabricating a dual metal gate. A substrate containing a cell region and a peripheral region is provided and a first dummy gate electrode and a second dummy gate electrode are formed on the substrate, respectively, in the cell region and in the peripheral region. Below the sidewalls of the first dummy gate electrode and the second dummy gate electrode, source/drains are formed in the substrate. A patterned first dielectric layer is formed above the substrate, and the layer exposes the surfaces of the first dummy gate electrode and the second dummy gate electrode. The first dummy gate electrode and the second dummy gate electrode are then removed to expose the substrate and an oxide layer is formed on the exposed substrate in the peripheral region. A remote plasma nitridation (RPN) step is performed to nitridate the surface of the exposed substrate in the cell region and to nitridate the oxide layer into a material layer in the peripheral region. A conformal second dielectric layer is formed above the substrate. A conducting layer is formed on the second dielectric layer and fills up trenches that are formed by removing the first dummy gate electrode and the second dummy gate electrode. A part of the second dielectric layer and a part of the conducting layer are removed until the surface of the first dielectric layer is exposed and a dual metal gate is completed thereon.

[0011] As embodied and broadly described herein, the RPN step is performed in an environment full of ammonia plasma or nitrogen plasma, at a temperature of about 500-800 degrees Centigrade, with a pressure less than 30 Torr, a plasma operation power of about 1000-5000 Watts and for a duration of about 30-90 seconds. Furthermore, metal silicides are formed on source/drains.

[0012] In this invention, a nitridation step is performed to nitridate the surfaces of the substrate and the surface of the oxide layer that are exposed by the trenches; therefore, the gate dielectric layer that is subsequently formed can maintain a higher dielectric constant. Moreover, gate dielectric layers of different thicknesses are formed respectively in the cell region and in the peripheral region (the effective thickness of the gate dielectric layer in the cell region is the sum of the thicknesses of the dielectric layer and the nitride layer, while the effective thickness of the gate dielectric layer in the peripheral region is the sum of the thicknesses of the dielectric layer and the material layer). Thus, this satisfies the requirement for a higher breakdown voltage in the peripheral region.

[0013] In this invention, metal gate layers are formed after metal silicide layers are formed on the source/drains; hence, the thermal budget of the manufacture process is reduced. The manufacture process of this invention is compatible with the prior art manufacture process for the gate dielectric layer; therefore, the manufacture processes can easily be integrated. In this invention, metal gate layers are formed after the source/drains are formed; therefore, the heat diffusion in the thermal process for forming source/drains does not result in contamination in the metal gate layers.

[0014] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

[0015] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

[0016] FIGS. 1A to 1G are schematic, cross-sectional views illustrating the processes for fabricating a dual metal gate according to one preferred embodiment of this invention.

[0017] Referring to FIG. 1A, a substrate 100 is provided. The substrate is, for example, a semiconductor silicon substrate. Substrate 100 contains a cell region 100aand a peripheral region 100b. In cell region 100a, a dummy gate electrode 102ais formed on substrate 100; a spacer 104ais formed on the sidewalls of dummy gate electrode 102a; a source/drain 106ais formed in substrate 100 beside spacer 104aand a metal silicide layer 108ais formed on source/drain 106a. In cell region 100b, a dummy gate electrode 102bis formed on substrate 100; a spacer 104bis formed on the sidewalls of dummy gate electrode 102b; a source/drain 106bis formed in substrate 100 beside spacer 104band a metal silicide layer 108bis formed on source/drain 106b.

[0018] A planarized dielectric layer 110 is formed above substrate 100, exposing the surfaces of dummy gate electrodes 102a, 102b. The step for forming dielectric layer 110 comprises forming a dielectric layer (not shown here) made of, for example, silicon oxide, above substrate 100 and removing a part of dielectric layer by, for example, chemical mechanical polishing, until the surfaces of the dummy gate electrodes are exposed.

[0019] Referring to FIG. 1B, dummy gate electrodes 102a, 102bare removed to form trenches 112aand 112bin cell region 100aand peripheral region 100b, respectively. An oxidation step is performed to form oxide layers 114aand 114b, respectively, in trenches 112aand 112bon exposed substrate 100. The oxidation step comprises a rapid thermal process in an environment full of oxygen, N₂O and NO, at a temperature of about 600-900 degrees Centigrade for a duration of about 5-60 seconds. Oxide layers 114aand 114bare formed thereon with a thickness of less than 15 Angstroms.

[0020] Referring to FIG. 1C, a patterned photoresist layer 116 is formed above substrate 100 to cover peripheral region 100b. Patterned photoresist layer 116 does not cover cell region 100a, and oxide layer 114ainside trench 112ais exposed. Oxide layer 114ais removed to expose the surface of substrate 100 by, for example, wet etching with a solution containing hydrogen fluoride.

[0021] Referring to FIG. 1D, photoresist layer 116 is removed to expose oxide layer 114binside trench 112bin peripheral region 100b. A nitridation step is performed to nitridate the surface of oxide layer 114binto a material layer 114cin trench 112band to form a nitride layer 118 on the surface of substrate 100 in trench 112a. Material layer 114chas a thickness less than 20 Angstroms, and nitride layer 118 has a thickness less than 10 Angstroms. A preferable process for the nitridation step is RPN. RPN is performed in an environment full of ammonia plasma or nitrogen plasma, at a temperature of about 500-800 degrees Centigrade, with a pressure less than 30 Torr, a plasma operation power of about 1000-5000 Watts and for a duration of about 30-90 seconds. RPN is performed to nitridate silicon atoms on the surfaces of substrate 100 in trench 112aand of oxide layer 114bin trench 112binto silicon nitride or silicon-oxynitride.

[0022] Referring to FIG. 1E, a conformal dielectric layer 120 is formed as a gate dielectric layer. Dielectric layer 120 consists of a material with a high dielectric constant, such as, silicon nitride, Ta₂O₅, Ta_2−XTi_XO₅or titanium nitride, formed by chemical vapor deposition (CVD).

[0023] Because dielectric layer 120 has a high dielectric constant, the effective thickness of dielectric layer 120 is greater. Therefore, the prior art problems that are caused by an overly thin gate oxide layer, such as current leakage in the gate and boron penetration, can be solved.

[0024] Before dielectric layer 120 is formed, the nitridation step is performed to nitridate the surfaces of substrate 100 and oxide layer 114bto form nitride layer 118 in trench 112aand material layer 114cin trench 112b, respectively. Therefore, native oxide layers are prevented from forming on the surfaces of substrate 100 and oxide layer 114b. This further maintains the dielectric constant and the effective thickness of dielectric layer 120 formed thereon.

[0025] Oxide layer 114ainside trench 112ain cell region 100ais removed before forming dielectric layer 120; therefore, the thickness of dielectric layer 120 and the thickness of nitride layer 118 add up to the effective thickness of the gate dielectric layer in cell region 100a. On the other hand, the thickness of dielectric layer 120 and the thickness of material layer 114cadd up to the effective thickness of the gate dielectric layer in peripheral region 100b. Consequently, the effective thickness of the gate oxide layer in cell region 100ais less than the effective thickness of the gate oxide layer in peripheral region 100b, which satisfies the requirement of higher breakdown voltage for the peripheral region to connect with outside circuits as an input/output.

[0026] Referring to FIG. 1F, after dielectric layer 120 is formed, a conformal barrier layer 122 and a conducting layer 124 are formed sequentially on substrate 100. Conducting layer 124 fills up trenches 112aand 112b. Barrier layer 122 protects underlying dielectric layer 120 from contacting the conducting material when conducting layer 124 is later formed. A material for barrier layer 122 comprises titanium nitride, tantalum nitride or tungsten nitride and is formed by sputtering. Conducting layer 124 is, for example, a tungsten metal layer that is formed by sputtering.

[0027] Referring to FIG. 1G, a part of dielectric layer 120, barrier layer 122 and conducting layer 124 are removed until the surface of dielectric layer 110 is exposed. A gate 126athat includes a dielectric layer 120a, a barrier layer 122a, a metal gate layer 124aand nitride layer 118 is formed thereon in cell region 100a. A gate 126bthat includes a dielectric layer 120b, a barrier layer 122b, a metal gate layer 124band material layer 114cis formed thereon in peripheral region 100b.

[0028] Metal silicide layers 108aand 108bare formed respectively on source/drains 106aand 106bbefore metal gate layers 124aand 124bare formed; therefore, the thermal budget of the manufacture process can be reduced. Metal gate layers 124aand 124bare formed after source/drains 106aand 106bare formed; therefore, the heat diffusion in the thermal process for forming source/drains 106aand 106bdoes not result in contamination in metal gate layers 124aand 124b.

[0029] As described broadly herein, this invention has the following advantages:

[0030] 1. In this invention, a nitridation step is performed to nitridate the surfaces of the substrate and the surface of the oxide layer that are exposed by the trenches; therefore, the gate dielectric layer subsequently formed can maintain a higher dielectric constant.

[0031] 2. In this invention, gate dielectric layers of different thicknesses are formed respectively in the cell region and in the peripheral region, so the requirement for a higher breakdown voltage in the peripheral region is satisfied.

[0032] 3. In this invention, metal gate layers are formed after metal silicide layers are formed on the source/drains; hence, the thermal budget of the manufacture process is reduced.

[0033] 4. The manufacture process of this invention is compatible with the prior art manufacture process for the gate dielectric layer; therefore, the manufacture processes can easily be integrated.

[0034] 5. In this invention, metal gate layers are formed after source/drains are formed; therefore, the heat diffusion in the thermal process for forming source/drains does not result in contamination in the metal gate layers.

[0035] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.