Scaling method and apparatus for a flat panel display

[0002] The invention relates generally to a method and apparatus for the scaling of digital image data. In particular, the invention relates to a method of enhancing image quality in images reproduced in a display format that differs from the original image format.

[0003] Digital video images such as those seen on computer display monitors are typically formatted according to industry standards (e.g., VGA, SVGA and XGA). Each standard defines various resolutions. Commonly, many different resolutions are supported by computer displays, however, flat panel displays and fixed resolution cathode ray tubes (CRTs) generally do not support multiple resolutions.

[0004] Digital image data can be scaled to make it compliant with the requirements of different standards. For example, VGA (640×480) data is scaled by a factor of 1.6 to fill a fixed XGA (1024×768) display. In some cases the source image resolution is higher than the monitor and must be scaled down. Some display devices are not capable of scaling images and thus only use a portion of the display area or a subset of the source image data.

[0005] A basic scaling technique is pixel replication which exhibits dramatic artifacts for fractional scale factors. Other traditional scaling algorithms do not provide maximum quality for fixed resolution monitors. The resulting images often appear out of focus or reveal jagged edges.

[0006] The present invention features a method and apparatus for scaling and enhancing a digital image has been developed which is useful in a wide variety of applications including, but not limited to, adapting digital image data for various video formats. The method and apparatus can be used to enhance the display of digital image data by smoothing the jagged edges inherent in digital images.

[0007] In one aspect, the invention features a method for enhancing a digital image. The method includes the steps of receiving a digital source image; selecting, for each output pixel, a block of source pixels having a center pixel which overlaps the output pixel; detecting edges in the block to generate an edge array; and processing the edge array to generate an effective source location for the output pixel. In one embodiment of the method, the step of processing the edge array includes applying a set of logic operations to detect a feature. In another embodiment, the method further includes the step of calculating an output value based on the value of at least one source pixel within the block. The step of calculating an output pixel value can include interpolating the output pixel value based on the values of four adjacent pixels within the block. In another embodiment, the method includes the additional step of modifying the effective source location to generate a modified effective source location based on a predetermined modifier function.

[0008] In another embodiment, the method includes the steps of receiving a digital source image; determining a source location for each output pixel; modifying the source location based on a predetermined modifier function to generate a modified source location; and interpolating an output pixel value based on the source pixel values of a block of four adjacent pixels relative to the modified source location.

[0009] In another aspect, the invention features an apparatus for enhancing a digital image. The apparatus includes an image buffer for receiving and storing source pixels. An edge detector module is coupled to the image buffer and receives, for each output pixel, a block of source pixels which has a center pixel that overlaps the output pixel. The edge detector generates arrays of horizontal and vertical edge values from the block. A memory buffer is coupled to the edge detector module and stores the array values. A processor is coupled to the memory buffer and generates an effective source location for each output pixel using the array values. In one embodiment, the processor also modifies the effective source location based on a predetermined modifier function. In another embodiment, the apparatus also includes a flat panel display coupled to the processor for graphically displaying the output pixel value.

[0010] The foregoing and other objects, features and advantages of the invention will become apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings. The drawings are not necessarily to scale, emphasis instead being placed on illustrating the principles of the present invention.

[0011] FIGS. 1A to 1C illustrate scaled source data using pixel replication, using bilinear interpolation, and using a combination of bilinear interpolation and an edge detection logic, respectively.

[0012] FIGS. 2A to 2C illustrate source data, scaled source data using pixel replication, and scaled source data using a combination of bilinear interpolation and edge detection logic, respectively.

[0013] FIG. 3 is a block diagram of a system for scaling red, green and blue (RGB) video data for display on an LCD panel.

[0014] FIG. 4 is a block diagram of a video scaling module according to the invention.

[0015] FIGS. 5A through 5C are pixel valid masks for determining valid source pixels for calculating output pixel values.

[0016] FIGS. 6 illustrates the relationship of a center source pixel with respect to a source pixel window.

[0017] FIGS. 7A and 7B illustrate possible vertical and horizontal edges, respectively, in a source pixel window.

[0018] FIGS. 8A and 8B illustrate the source pixel window and the four interpolation pixels, respectively, used to generate an output pixel value.

[0019] FIG. 9 is a plot of a step function offset adjustment used in generating a modified effective source location of an output pixel.

[0020] FIGS. 10A and 10B illustrate edge detection logic arrays used for identifying specific edge arrangements in source pixel array data.

[0021] FIGS. 11A and 11B are a flowchart of an iterative method of scaling digital image data according to the invention.

[0022] FIG. 1A shows script characters 12 and numerals 14 displayed as an image 10 on an XGA video monitor. The characters 12 and numerals 14 are generated from bitonal pixel values (i.e., only two possible pixel values). The source data corresponding to the characters 12 and numerals 14 were generated for display on a VGA monitor. The source data have been scaled by a factor of 1.6 to allow the characters 12 and numerals 14 to be displayed on the higher resolution XGA monitor. The smooth edges of the script characters 12 are not apparent, instead the discrete nature of the digital image can be seen as jagged edges that detract from the overall image quality.

[0023] In FIG. 1B the source data used to generate the characters 12′ and numerals 14′ of scaled image 10′ have been scaled by a value of approximately 1.6 and processed using a bilinear interpolation applied along the horizontal and vertical axes of the display. Although still observable, the jagged edges are less apparent. The result is an improved image quality.

[0024] FIG. 1C shows an enhanced image 10″ which includes enhanced script characters 12″ and numerals 14″ after processing the source data of FIG. 1B and applying the enhancement technique of the present invention. The result is an image 10″ where the discrete pixel appearance inherent in many digital images is substantially reduced.

[0025] FIG. 2A illustrates a portion of a flat panel display with a partial image 22 comprised of pixels at one of only two values (i.e., pixel on or pixel off). FIG. 2B illustrates a partial image 22′ displayed on the flat panel display having a vertical and horizontal resolution 1.6 times that of the monitor in FIG. 2A. The partial image 22′ includes features which are of different widths than the corresponding features in the partial image 22 of FIG. 2A. For example, vertical line segment 18′ which is only one pixel wide is narrower than the corresponding one pixel wide line segment 18 in the unscaled partial image 22. Vertical line segment 20′, however, is two pixels wide and thus is slightly wider than the corresponding line segment 20 in the unscaled image 22.

[0026] FIG. 2C shows an enhanced partial image 22″ on the flat panel display of FIG. 2B resulting from application of the method of the present invention. The enhanced image 22″ is, in part, the result of applying a non-linear interpolation technique to the data displayed in FIG. 2B. The data used to generate the enhanced image 22″ was also processed with an edge detection logic algorithm to determine the location of edges (i.e., sharp changes in pixel values between adjacent pixels). A comparison of the edge locations with predetermined edge arrangements (i.e., edge arrays) corresponding to known features is performed. If the comparison determines that a feature is likely contained in the data, then pixel values in the neighborhood of the feature can be adjusted. The final result is an enhanced image 22″ with a smoothing of the jagged artifacts inherent in the display of binary data. In general, the enhanced image 22″ is more acceptable to the viewer than an unenhanced image 22 or 22′ because the features more closely resemble the original image (beforescaling).

[0027] FIG. 3 shows a block diagram of a system 30 for enhancing and scaling RGB video data for compatibility with different video formats. The system 30 includes an analog-to-digital (A/D) converter 32 for receiving RGB analog source video 31a-cand converting it to RGB digital data 33a-c,respectively. After conversion to digital format, each pixel in the digital data 33a-cis represented by separate 8-bit components for red, green and blue. A video scaler module 34 receives the RGB digital data 33a-cand processes it to generate scaled pixel data 35a-c.A liquid crystal display (LCD) controller 36 receives the scaled pixel data 35a-cand drives a LCD monitor 38 displaying the enhanced image 22″. An on-screen display (OSD) module 40 is used to input character data to the video scaler module 34 where it is merged into the scaled pixel data 35a-c.A processor 42 coordinates the operations of the video scaler module 34 and OSD module 40.

[0028] FIG. 4 illustrates the components of the video scaler module 34 and processor 42. A source video interface module 46 receives input source pixels 33 (RGB digital data) from one or more A/D converters 32 or digital sources (FIG. 3) and distributes the pixels in pairs to the eight line buffers 48a-h.Each of the line buffers 48a-his sized to support the scaleable source video mode with the greatest horizontal resolution. For example, if the largest scaleable video mode is 832×624 SVGA, then each line buffer 48 can hold 832 pixels and is structured as 416 words of 48 bits each (two pixels wide). Only the source video interface module 46 can write to the line buffers 48 and only active pixels can be stored. Scaling engine 50 receives data from selected line buffers 48 as determined by buffer selector 52. An individual buffer 48 can never be accessed simultaneously by both the source video interface module 46 and the scaling engine 50.

[0029] When the number of active source pixels does not exceed 832, each line of source video is stored into a single line buffer 48 beginning at location zero. The first source line of the vertical frame is always stored in line buffer zero 48a.Subsequent source lines are stored in sequentially numbered line buffers 48, wrapping around to line buffer zero 48aafter filling the seventh line buffer 48h.The scaling engine 50 accesses five consecutive line buffers 48 at a time. When a subsequent output line requires a new source line, the five consecutive line buffers 48 beginning at the next sequentially numbered line buffer 48 are accessed, wrapping around to line buffer zero 48aafter the seventh line buffer 48his accessed. For example, the sequence of line buffers 48 accessed is (0-4), (1-5), (2-6), (3-7), (4-7, 0), etc.

[0030] When the number of active source pixels exceeds 832, each line of source video is stored in two consecutive line buffers 48. For example, XGA video mode requires 1024 horizontal pixels. In this case, the first 512 pixels of the source line are stored in line buffer zero 48abeginning at location zero. The remaining pixels of the source line are stored in line buffer one 48b. The first source line of the vertical frame is always stored in line buffers zero and one, 48aand 48b,respectively. Subsequent source lines are stored in sequentially numbered pairs of line buffers 48, wrapping around to line buffer zero 48aafter filling the seventh line buffer 48h.The scaling engine 50 only accesses one line buffer 48 at a time because enhancement must be disabled when the number of pixels in a source video line exceeds the size of a line buffer 48. The first output line of the vertical frame is read from line buffers zero and one, 48aand 48b,respectively. Each subsequent output line is accessed from the next pair of sequentially numbered line buffers 48, wrapping around to line buffer zero 48aafter the seventh line buffer 48hhas been read. For example, the sequence of line buffers 48 accessed is (0-1), (2-3), (4-5), (6-7), (1-2), etc.

[0031] A source controller 54 generates all control and timing signals related to the source pixel stream based on the source pixel clock from a phase lock loop (PLL) reference module 56 or an external source clock. In particular, the source controller 54 controls operation of the source video interface module 46 and writing to the line buffers 48. The source controller 54 communicates with an output controller 58 which is used to correctly align the source and output vertical frames. The output controller 58 controls timing for the output pixel stream based on the output pixel clock from the PLL reference module 56 or an external output clock. In particular, the output controller 58 controls the scaling engine 50, a color control module 60, an OSD mixer 62, and an output video interface module 64.

[0032] Referring to FIG. 8A, the scaling engine 50 maintains a 5×5 block 70 (i.e., array) of source pixels SP[0,0] through SP[4,4] which are used to calculate the value of an output pixel. When enhancement is enabled, all 25 pixels in the window 70 are used in determining the output pixel value. When enhancement is disabled, the value of the center pixel 74 (i.e., SP[2,2]) is used as the value of the output pixel. The output controller 58 provides data to the block 70 one column at a time as it is read from the line buffers 48. When enhancement is enabled, the values for each vertical column are obtained by accessing one pixel from each of five consecutive line buffers 48, one at a time. When enhancement is disabled, only the center row of pixels SP[1 . . . 5,2] is actually accessed from the line buffers 48.

[0033] A set of five-bit row×five-bit column pixel valid masks 72 are used by the scaling engine 50 to determine which rows and columns of the block 70 are valid (see FIG. 5A). The pixel valid masks 72 are used to identify the edges and corners of the screen. For example, for the first output pixel of a vertical frame (top left pixel), the top two rows and the leftmost two columns of the window are invalid. FIGS. 5A to 5C illustrate the pixel invalid masks corresponding to the first three pixels of the top line of the source video frame, respectively. If any of the pixels in the pixel valid mask 72 are not valid, then the scaling engine 50 generates an output pixel value equal to the value of the center source pixel 74.

[0034] For each output pixel, the scaling engine 50 also receives the position of the output pixel relative to the center source pixel 74. Referring to FIG. 6, the center of the output pixel must always lie within the boundaries of the center pixel 74. The center pixel 74 has dimensions of (1, 1) and the coordinate system uses unsigned values with the center of the center source pixel 74 at (0.5, 0.5). The four quadrants of the center pixel 74 are also defined for use in calculating the output pixel value.

[0035] The source pixel which bounds the output pixel is determined by dividing each coordinate of the output pixel by the scale factor appropriate for the video format conversion and rounding the result to the nearest integer. The horizontal scale factor is the ratio of the width of the source video in pixels to the width of the output video in pixels. Similarly, the vertical scale factor is the ratio of the height of the source video in pixels to the height of the output video in pixels. As an example, consider which source pixel to use at the center pixel 74 of the block 70 for output pixel (29,57). Assuming the source video is VGA mode (640×480 resolution) and the output video is XGA mode (1024×768 resolution), the horizontal scale factor, SF_H, and vertical scale factor, SF_V, are ${\mathrm{SF}}_H=\frac{1024}{640}=1.6$ ${\mathrm{SF}}_V=\frac{768}{480}=1.6$

[0036] Thus, the center pixel 74 is source pixel (18, 36).

[0037] The method used by the scaling engine 50 to determine the output pixel value is based on several steps. First, the pixel values of the block 70 are processed to generate horizontally and vertically detected edges between adjacent pixels. Referring to FIGS. 7A and 7B, there are a total of 40 possible edges in each block 70. The horizontally detected edges are stored in a 4×5 horizontal edge array 76 and the vertically detected edges are stored in a 5×4 vertical edge array 78. For each possible edge, a difference flag is defined and set if its corresponding edge exists. An edge exists between two adjacent pixels when the absolute difference between any of their color components exceeds a programmable edge threshold value.

[0038] The next step for determining the output pixel value is to process the horizontal and vertical edge arrays 76 and 78 with a set of predetermined logic arrays 84 shown as Pat01 to Pat24FIGS. 10A and 10B. Each logic array 84 consists of 40 logic operations corresponding to the 40 edge flags. Each logic operation generates a decision variable which can have one of three possible logical values (true, false or don't care). The decision variables for each logic array 84 are represented as follows: $\begin{array}{cc}|\mathrm{or\_}& \mathrm{edge}\mathrm{must}\mathrm{be}\mathrm{present}\mathrm{for}a\mathrm{match}\\ x& \mathrm{all}\mathrm{edges}\mathrm{must}\mathrm{be}\mathrm{absent}\mathrm{for}a\mathrm{match}\\ \mathrm{No}|,\mathrm{\_or}x& \mathrm{presence}\mathrm{or}\mathrm{absence}\mathrm{of}\mathrm{edge}\mathrm{is}\mathrm{not}\mathrm{relevant}\left(\mathrm{don}\text{'}t\mathrm{care}\right)\end{array}$

[0039] The logical values are determined according to the truth table shown in Table 1.

[0040] A logic array 84 is considered to match with a set of edge arrays 76 and 78 when all of its decision variables have true or don't-care logical values. If a match is found, a match variable is set equal to a value which uniquely describes the matched logic array (i.e., an index value). If more than one match exists, the match variable is set based on the first matched logic array. The match variable is set to zero when no match exists.

[0041] Referring to FIGS. 8A and 8B, the value of the output pixel is calculated from a 2 by 2 source pixel array 80, which is selected from the block 70 according to the quadrant of the center source pixel 74 which borders the output pixel. The four source pixels 80 selected include the center pixel 74 and the three source pixels which are the closest to the output pixel center. For example, if the output pixel is centered in the third quadrant (see FIG. 6) of the center source pixel 74 then the selected pixels are SP[1,2], SP[2,2], SP[1,3] and SP[2,3].

[0042] In another step performed by the scaling engine 50, the offset (XA, YA) of the output pixel relative to the center of the center source pixel 74 is determined. XA and YA can be conditionally adjusted if a logic array 84 is matched. Each logic array 84 defines a condition which is a function of the quadrant of the center source pixel 74 in which the output pixel center is located. If the condition is true, then the values of (XA, YA) are adjusted, effectively changing the location of the center source pixel 74 with respect to the block 70. Each offset or adjusted offset value is then modified according to a predetermined modifier function 86 as shown in FIG. 9. The predetermined modifier function 86 is defined in steps 90, 92, 94, 96 and 98 by assigning a unique offset value for each of a range of offset values. The function 86 is programmable to adapt to the requirements of a particular display application.

[0043] In another step, two 1×2 arrays (not shown) of interpolation constants, XC and YC, are defined. The quadrant of the center source pixel 74 in which the output pixel center is located based on the adjusted offset is used to determine XC and YC as follows:

[0044] Quadrant 1

[0045] XC[0]=1−XA

[0046] XC[1]=XA

[0047] YC[0]=YA

[0048] YC[1]=1−YA

[0049] Quadrant 2

[0050] XC[0]=1−XA

[0051] XC[1]=1−XA

[0052] YC[0]=YA

[0053] YC[1]=1−YA

[0054] Quadrant 3

[0055] XC[0]=1−XA

[0056] XC[1]=1−XA

[0057] YC[0]=1−YA

[0058] YC[1]=YA

[0059] Quadrant 4

[0060] XC[0]=1−XA

[0061] XC[1]=XA

[0062] YC[0]=1−YA

[0063] YC[1]=YA

[0064] If enhancement is disabled or if any of the source pixels in the block 70 are invalid due to intersection with the edges of the source bitmap, then the output pixel value is assigned the same value as the center source pixel 74. Otherwise, the output pixel value C is obtained by bilinear interpolation of the four pixels in IP as follows:

[0065] C1=(IP[0,0].C*XC[0])+(IP[1,0].C*XC[1])

[0066] C2=(IP[0,1].C*XC[0])+(IP[1,1].C*XC[1])

[0067] C=(C1*YC[0])+(C2*YC[1])

[0068] where IP[0,0].C, IP[1,0].C, IP[0,1].C and IP[1,1].C are the value for one color (e.g., red, green or blue) of the four interpolation pixels shown in FIG. 8B. This bilinear interpolation is used to generate all color values for each output pixel.

[0069] Referring to the flowchart in FIG. 11, one implementation of the method of the invention is described as a series of steps. At step 100, the next output pixel to be generated for the scaled display is determined. At step 110, the corresponding center source pixel 74 is determined by dividing the coordinates of the output pixel by the corresponding horizontal and vertical scale factors, SF_Hand SF_V, respectively, and rounding the result to the nearest integer. A valid pixel mask 72 corresponding to the center source pixel 74 is applied in step 120 and a determination as to whether all pixels are valid is made in step 130. If all the pixels are valid then horizontal and vertical edge arrays are generated in step 140. If not all the pixels are valid, however, the output pixel value is assigned the value of the center source pixel in step 150, whether any more output pixel values are to be determined is decided in step 160 and the method returns to step 100, if necessary.

[0070] After step 140 is completed, the first of the set of logic arrays 84 is applied to the edge arrays 76 and 78 in step 170. If a match is determined in step 180, then a match variable is set to indicate the matched array in step 190. If no match results from step 180 and if there is at least one more logic array 84 to be applied as determined in step 200, then the next logic array 84 is applied (steps 210 and 170). If no match results from step 180 and there are no more logic arrays 84 to be applied, then the match variable is set to zero in step 220.

[0071] At step 230, the absolute offset values of the output pixel relative to the center of the center source pixel 74 are determined. The offsets are modified in step 240 based on the match variable value. A predetermined modifier function 86 is used to adjust the offset values in step 250. The output value of the pixel is determined by bilinear interpolation in step 260 using the offset values generated in the previous step. If any more output pixel values must be determined according to step 270, another iteration is started by returning to step 100.

[0072] Equivalents

[0073] While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.