Methods for coding and decoding nibble inversion codes and block inversion codes and coding and decoding apparatus for the same

[0002] 1. Field of the Invention

[0003] The present invention relates to line codes used for a transmission, interconnection and storing apparatus, in particular to methods for coding and decoding nibble inversion codes and block inversion codes and coding and decoding apparatus for the same which are capable of implementing an easier clock recovery, using one redundancy bit for a decoding operation, providing multiple frame synchronization code words, fully providing in-band and out-band signals, adapting a basic principle of a coding operation even when source byte data is not consist of 8 bit, and being easily adaptable to a hardware in a state that there are not DC spectrum components.

[0004] 2. Description of the Conventional Art

[0005] According to the article of “Principles of digital line coding” by K. W. Cattermole, Int. J. electronics, Vol. 55, No. 1, pp. 3-33, 1983, it is known that the line coding is used for reliably recovering data bits from a serial bit stream. In addition, in the article of “A DC-balanced, partitioned-block, 8B10B transmission code” by A. X. Widmer and P. A. Franaszek, IBM J. Res. Develop., Vol. 5, pp. 440-451, 1983, the features such as a frame synchronization pattern and an in-band signal (special characters such as comma, identifier, empty character, etc.) are disclosed.

[0006] The line coding used for a physical layer in a communication transmission field requires a clock recovery and optical connection. Therefore, enough transition should be generated for a serial bit stream for the clock recovery. In addition, the DC frequency components should be 0 (zero) for implementing an AC coupling for the optical connection (R. M. Brooks and A. Jessop, “Line coding for optical fiber systems”, Int. J. Electronics. Vol. 55, No. 1, pp. 81-120, 1983).

[0007] For implementing the above-described functions, a Manchester code, a CMI (Code Mark Inversion) code, and a 5B6B code are widely used. However, the above-described codes use the redundancy bits which decrease coding efficiency, and when the above-described codes are used in systems that process the codes byte by byte, it is very complicating and inconvenient.

[0008] In the field of the communication transmission, the scrambled zero non-return (scrambled NRZ) code which maximizes the coding efficiency is widely used. However, the scrambled NRZ secures DC frequency components of 0 statistically, not perfectly. The scrambled NRZ does not provide a frame synchronization pattern and an in-band signal.

[0009] In addition, a 8B10B code which has high coding efficiency in order to overcome the above-described problems in the computer network transmission field and is capable of providing an in-band signal (or a special character) is disclosed in P. A. Franaszek and A. X. Widmer, “Byte oriented DC balanced 8B10B partitioned block transmission code”, U.S. Pat. Ser. No. 4,486,739. However, even though the above-described 8B10B code overcomes the problems encountered in the pre-codes, there are still problems that when the out-band signal or the frame synchronization pattern is inserted. In the 8B10B code, the out-band signal or the frame synchronization patterns should be inserted into a user source data field because a byte generally consists of 8 bits. Also the 8B10B code is impossible to obtain a uniform and symmetrical characteristic of coding rule when coding the source data is not consist of 8 bit such as 9-bit or 16-bit signal. Namely, since 2-bit redundancy bits are added to the 8-bit signal of the source data byte, when the frame synchronization pattern or a signal bit is inserted, it is impossible to add a redundancy bit to the code word so that user frame format should be changed. In addition, when coding the data except for the 8-bit signal, the code algorithm should be fully changed.

[0010] According to the article of W. A. Krzymein, “Transmission performance analysis of a new class of line codes for optical fiber systems”, IEEE Trans. Commun., Vol. 37, No. 4, pp. 402-404, April 1989, the Partially flipped mB (m+1)B code is disclosed. This code forms a code word of m+1 bit by inserting a 1 bit redundancy bit into a m-bit source data character. In addition, this code implements a code operation using a disparity of a source data character and a running digital sum (RDS) which are code parameters. However, this code has a good coding efficiency and is simply used, but a synchronization code and in-band and out-band are not provided. Therefore, it is impossible to obtain good coding performance of a RDS, disparity, digital sum variation (DSV) and a run length.

[0011] It is an object of the present invention to provide methods for coding and decoding nibble inversion codes and block inversion codes and coding and decoding apparatus for the same which are capable of providing transition and DC spectrum components of 0, using a 1-bit redundancy bit when a predetermined n-bit (n represents odd number) is coded, providing multiple frame patterns, providing an in-band and out-band signals enough, and detecting a bit error by a code violation detection based on a simple hardware.

[0012] In order to achieve the above objects, there are provided methods for coding nibble inversion codes and block inversion codes according to a first embodiment of the present invention which include the steps of a first step for adding a one redundancy bit to a n-bit (n represents an odd number larger than 3) source data and generating a pre-code, a second step for setting the pre-code as a code word when a disparity of the pre-code generated in the first step is 0 and the source data is not an in-band signal (or special character), a third step for inverting a half bit (nibble) including a redundancy bit among the bits (block) forming a pre-code when the disparity of the pre-code generated in the first step is 0 and the source data is a set in-band signal (or special character), setting the nibble-inverted pre-code as a code word and generating a complement code word which is a block-inverted code word version and a code word, a fourth step for nibble-inverting a pre-code when the disparity of the pre-code generated in the first step is not 0, setting a nibble-inverted pre-code as a code word when the disparity of the nibble-inverted pre-code is within a predefined value and generating a complement code word which is a block-inverted code word and a code word when the disparity of the set code word is not 0, a fifth step or nibble-inverting the pre-code when the disparity of the pre-code generated in the first step is not 0, manipulating the bits of the pre-code when the disparity of the nibble-inverted pre-code is not within a predefined value, manipulating the bits of the pre-code so that the disparity of the nibble-inverted pre-code is within a predefined value when the disparity of the manipulated pre-code is 0 and concurrently manipulated, setting the manipulated and nibble-inverted pre-code as a code word, and generating a complement code word which is a block-inverted code word version and a code word when the disparity of the set code word is not 0, a sixth step for selecting a code word in which the absolute value of the running digital sum (RDS) is decreased when the code with respect to the source data exists as two values of a complement code word and a code word, and a seventh step for combining the code words for a frame synchronization and generating a synchronization code word so that a unique pattern exists in a serial bit stream when the code word is converted from a parallel form to a serial form.

[0013] In order to achieve the above objects, there is provided a nibble inversion and block inversion code coding and decoding method according to a second embodiment of the present invention which includes the steps of a first step for decoding a source data bits except for a redundancy bit from a code word when a disparity of a code word is 0 and a redundancy bit is not inverted, a second step for nibble-inverting half bits (nibble) including a redundancy bit among the bits of the code word when the dispari ty of the code word is 0 and the redundancy bit is inverted and decoding a source data bits except for the redundancy bit of the nibble-inverted code word, a third step for nibble-inverting half bits including a redundancy bit among the bits of the code word when the disparity of the code word is not 0 and has a predefined value and decoding a source data bits except for the redundancy bits from the code word when the disparity of the nibble-inverted code word is not 0 and the redundancy bit of the nibble-inverted code word is not inverted, a fourth step for nibble-inverting when the disparity of the code word is not 0 and has a pres-set value, block-inverting the bits (block) of a decode word when the disparity of the nibble-inverted code word is not 0 and the redundancy bit of the nibble-inverted code word is inverted, a fifth step for nibble-inverting when the disparity of the code word is not 0 and has a predefined value, nibble-inverting when the disparity of the nibble-inverted code word is 0 and is a synchronization or in-band signal (or special) code word, indicating an in-band signal (or special) character signal decoding the source data using the bits except for the redundancy bit from the block-inverted code word when the redundancy bit of the nibble-inverted code word is inverted, decoding the source data bits except for the redundancy bit from the nibble-inverted code word when the redundancy bit of the nibble-inverted code word is not inverted, and indicating an in-band signal (or special) character signal, a sixth step for nibble-inverting when the disparity of the code word is not 0 and has a predefined value, nibble-inverting after searching and recovering the manipulated bits when the disparity of the nibble-inverted code word is 0 and a bit-manipulated code word, decoding a source data bits except for the redundancy bit from the block-inverted code word when the redundancy bit of the recovered and nibble-inverted code word is inverted, and decoding the source data using the bits except for the redundancy bit from the recovered and nibble-inverted code word when the redundancy bit of the nibble-inverted code word is not inverted, a seventh step for decoding based on the above-described condition and process when a predefined frame synchronization pattern is detected from the code word stream and decoding a synchronization character, and an eighth step for detecting the code word as a violation when the running digital sum exceeds a predefined value or the disparity of the code word exceeds a predefined value.

[0014] In order to achieve the above objects, there is provided a nibble inversion and block inversion code coding and decoding apparatus according to a third embodiment of the present invention which includes a disparity calculator for receiving a pre-code in which a nibble-inverted indication (NII) bit is added at the position next to the LSB of a source data of a n-bit (n represents an odd number larger than 3), computing a disparity Dpc of the pre-code, computing a disparity Dni of the odd bit nibble-inverted pre-code, decoding a code type in accordance with the value of the register and the running digital sum RDS which represent the disparity code and outputting a control signal for manipulating the bits of the pre-code; a RDS calculator for outputting a RDS which is obtained by accumulatively summing the disparity of the calculated code word by the unit of blocks for selecting a code word or a complement code word when the computed disparity Dpc is not 0; and a bit manipulator for selecting a nibble-inverted and block-inverted (NIBI) code type in accordance with a control signal from the disparity calculator, manipulating a bit of the inputted pre-code and generating a code word or a complement code word.

[0015] In order to achieve the above objects, there is provided a nibble inversion and block inversion code coding and decoding apparatus according to a fourth embodiment of the present invention which includes a disparity calculator for receiving a block synchronized code word, calculating a disparity Dcw of the code word, computing a disparity Dni of the nibble-inverted code word, decoding a NIBI decoding type in accordance with a computed disparity value and a bit pattern of a code word and generating a control signal for manipulating the bits of the code word; a RDS calculator for outputting a RDS which is obtained by accumulatively summing the disparity Dni of the computed code word by the unit of blocks; and a bit manipulator for selecting a NIBI decoding type in accordance with a control signal of the disparity calculator, manipulating a bit of the code word, and recovering the original character.

[0016] Additional advantages, objects and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims as a result of the experiment compared to the conventional arts.

[0017] The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:

[0018] FIGS. 1A through 1C are flow charts illustrating a NIBI coding operation according to the present invention;

[0019] FIGS. 2A and 2B are flow charts illustrating a NIBI decoding operation according to the present invention;

[0020] FIG. 3 is a block diagram illustrating a NIBI coding apparatus according to the present invention; and

[0021] FIG. 4 is a block diagram illustrating a NIBI decoding apparatus according to the present invention.

[0022] The technical terms used in the description of the present invention are defined as follows for providing a simple construction and operation of the present invention.

[0023] Disparity: In the code word, it represents a difference between the number of 1 (ones) and the number of 0 (zeros), and disparity is the positive integer, if the amount of 0 is more than 1, and if the amount of 0 is less than 1, disparity is the negative integer.

[0024] RDS (Running digital sum): The accumulated sum of disparities of the code words finally transmitted at a corresponding time from a predetermined set time.

[0025] Source data: Primitive data generated by machine or user.

[0026] Code word: Data word expressed by a method having a rule.

[0027] Pre-code: Code which is formed by inserting one bit to a source data for a coding operation (the inserted Bit is a logic level of 0).

[0028] Nibble: Half of the bits of a pre-code or a code word.

[0029] Block: Bits of a code word.

[0030] Character: Bits of source data.

[0031] Digital sum variation (DSV): Difference between maximum value and minimum value of the possible digital sums in a coded stream of a predetermined code.

[0032] The coding method for nibble inversion codes and block inversion codes according to the present invention will be explained.

[0033] In addition, NIBI encoding and decoding algorithm will be explained as follows.

[0034] NIBI (Nibble Inversion Block Inversion) code is related to line codes used for the transmission and interconnection. It is a transmission code with high performance as follows:

[0035] it is easy for clock recovery,

[0036] it does not have DC spectrum components,

[0037] it uses only one redundancy bit to encode,

[0038] it providing various frame synchronization patterns,

[0039] it also providing sufficient in-band and out-band signaling signals,

[0040] it follows the same coding rules even the source data byte is octet or character or word,

[0041] it is easily implemented into hardware.

[0042] NIBI coding performance is as follows: Disparity is less than 5, RDS (Running Digital Sum) is less than 7, and the maximum run 1's or 0's length is 12. The source data are 9-bit characters, a encoded code word is called a block. NIBI encoder adds NII (Nibble Inversion Indication) bit next the LSB of the character consisting of b(8:0) to generate a 10-bit pre-code. In other words, it makes a pre-code composed of b8, b7, b6, b5, b4, b3, b2, b1, b0, and NII (NII=0), where b8 is the MSB, and NII is the new LSB. The odd bit nibble is composed of b7, b5, b3, b1 and NII. The even bit nibble is composed of b8, b6, b2 and b0. The odd bit nibble inversion takes the complements of odd bit, generating b7, b5, b3, b1, and NII, where b7 is the complement of b7. If the code word is c(9:0), the block inversion is the complement of the code word, c(9:0). The NIBI coding rules are described using a flow chart in FIG. 1. For the convenience of computing disparity and the simplicity of hardware implementation, NIBI encoder calculates odd bit nibble disparity (Dpco)of the pre-code and even bit nibble disparity (Dpce) of the pre-code, and adds the odd bit nibble disparity to the even bit nibble disparity to calculate the disparity of the pre-code (Dpc). The even bit nibble disparity (Dpce) can be used to calculate disparity (Dni) for the odd bit nibble inverted pre-code. RDS sums up the disparity of the each code word; RDS of NIBI code is +6 at the maximum, and −6 at the minimum. If the disparity of a code word is not 0, the code word has the complement code word version. The complement code word is generated by block inverting the code word. The coding rules according to the NIBI coding types are as follows:

[0043] 1. If Dpc=0, the pre-code is the code word (Type 1A)

[0044] 2. If Dpc≠0, and Dni=0 or +/−2 or +/−4, the nibble inverted (where ‘nibble inverted’ means ‘odd bit nibble inverted’) pre-code is the code word. If Dni=0, the complement code word version that is block-inverted is also generated (Type 2).

[0045] 3. If Dpc0 and Dni=+/−6, it manipulates bits in the pre-code to make the zero disparity of the bit-manipulated pre-code, and to make +/−2 disparity of the bit-manipulated and nibble-inverted pre-code. And the block inverted complement code version is also generated (Type 3A, Type 3B and Type 3C).

[0046] If Dpc0 and Dni=+/−6 and Dpco=−5 and not b2=b0=0 (b20 or b00), the bit manipulator inverts b7 and b3 of the pre-code respectively. And it inverts the odd bit nibble of the pre-code to generate the code word and the block inverted complement code word version (Type 3A).

[0047] If Dpc=0 and Dni=+/−6 and Dpco=−5, the bit manipulator inverts b0 and b2 of the pre-code respectively. And it inverts odd bit nibble of pre-code to generate the code word and the block inverted complement code word version (Type 3B).

[0048] If Dpc0 and Dni=+/−6 and Dpco=−5 and b2=b0=0, the bit manipulator inverts b5, b4, b3 and b2 of the pre-code respectively. And it inverts the odd bit nibble to generate the code word and the block inverted complement code word version (Type 3C).

[0049] 4. If Dpc0 and Dni=+/−8, it manipulates bits in the pre-code to make the zero disparity of the bit manipulated pre-code, and to make +/−2 disparity of the bit manipulated and nibble inverted pre-code. And the block inverted complement code is also generated (Type 4A, Type 4B).

[0050] If Dpc=0 and Dni=+/−8 and Dpco=−5 and b4=b2=1, or if Dpc0 and Dni=+/−8 and Dpco−5 and not b5=b3=b1, the bit manipulator inverts b5, b4, b3, b2, and b1 of the pre-code respectively. And it inverts the odd bit nibble pre-code to generate the code word and the block inverted complement de word version (Type 4A).

[0051] If Dpc0 and Dni=+/−8 and Dpco=−5 and not b4=b2=1, or if Dpc0 and Dni=+/−8 and Dpco−5 and b5=b3=b1, the bit manipulator inverts b6, b5, b4, b3 and b2 of the pre-code respectively. And it inverts the odd bit nibble of pre-code to generate the code word and the block inverted complement ode word version (Type 4B).

[0052] 5. If Dpc=0 and the character is an in-band signaling/special character, the bit manipulator inverts odd bit nibble of the pre-code which is not used in Type 3A, Type 3B, Type 3C, Type 4A and Type 4B code word. As disparity of the nibble-inverted pre-code is +/−2, and the code word has a complement code version (Type 1B).

[0053] For 512 9-bit source characters, each NIBI coding type can be categorized as followings. 126 code words for Type 1A, 20 in-band signaling/special code words for Type 1B, 356 code words for Type 2, 9 code words for Type 3A, 10 code words for Type 3B, 1 code word for Type 3C, 6 code words for Type 4A, 4 code words for Type 4B. And it has 280 complement code words. If the disparity of the code word is non-zero, it decides whether the code word is selected or the complement code word is selected according to the RDS. RDS at the time of t is defined as RDS(t), the disparity sign of the time of t is defined as R(t), RDS at the time of t+1 defined as RDS(t+1), and the disparity sign of the time of t+1 defined as R(t+1), the coding rules of the code word with the complement code word are as follows:

[0054] 1. If RDS(t)>0, it selects the code word with negative disparity at the time of t+1.

[0055] 2. If RDS(t)<0, it selects the code word with positive disparity at the time of t+1.

[0056] 3. If RDS(t)=0, and R(t)=1(the disparity has positive value at the time of t), it selects the code word with negative disparity at the time of t+1.

[0057] 4. If RDS(t)=0, and R(t)=0 (the disparity has negative value at the time of t), it selects the code word with positive disparity at the time of t+1.

[0058] 5. For the synchronization codes, it does not follow the coding rules above, but follow the special coding rules described below.

[0059] As a result, RDS reaches only +/−4 if the above coding rules apply. The NIBI code provides the synchronization characters for frame synchronization or block synchronization. The synchronization characters appear as unique patterns in serial bit stream. In the NIBI code, unfortunately, unique patterns are not generated in a single character. If a combine pattern of an arbitrary in-band signaling/special code word and an arbitrary code word is unique in serial bit stream (or as comparing with other combinations of arbitrary code words), the in-band signaling/special code word and the code word can be used as synchronization characters.

[0060] Synchronization code words follow the following coding rules.

[0061] 1. If the disparity of the synchronization in-band signaling/special code word selected at the time of t is +2, the disparity of the synchronization code word selected at the moment of t+1 is +4.

[0062] 2. If the disparity of the synchronization in-band signaling (or special). code word selected at the time of t is −2, the disparity of the synchronization code word selected at the time of t+1 is −4.

[0063] The code-book according to the NIBI coding rules is shown in Table 1a.

[0064] The NIBI decoding rules are the reversed operation of the NIBI encoding rules. Source data is 9-bit character, the coded block is called the code word. The block is composed of c8, c7, c6, c5, c4, c3, c2, c1, c0, and NII. The code word is divided into the odd bit nibble and the even bit nibble. The odd bit nibble consists of c7, c5, c3, c1, and NII, the even nibble consists of c8, c6, c4, c2, and c0. The odd bit nibble inversion takes the complement of the odd bit nibble to generate c7, c5, c3, c1, and NII, where c7 is the complement of c7. If the code word is c(9:0), the block inversion is the complement of the code word, c(9:0). The NIBI decoding rules are described using a flow chart in FIG. 2.

[0065] For the convenience of computing disparity and the simplicity of implementing hardware, the NIBI decoder calculates odd bit nibble disparity (Dcw o) of the code word and even nibble disparity (Dcwe), and adds odd bit nibble disparity to even nibble disparity to calculate the disparity of the code word (Dcw). The even bit nibble disparity (Dcwe) can be used to calculate disparity (Dni) for the odd bit nibble inverted code word. RDS sums up the disparity of the each code word; RDS of NIBI code is 6 at the maximum, and −6 at the minimum. If RDS is greater than +6 or RDS is less than −6, it means that code violation occurred. The decoding rules according to the NIBI coding types are as follows:

[0066] 1. If Dcw=0 and NII=0, a decoded character is a code word except for NII bit (Type 1A).

[0067] 2. If Dcw=+/−2 or Dcw=+/−4 and Dni 0, and if NII=0, it generates a character by taking the NII bit out of the nibble inverted code words to make characters. If NII=1, it generates a character by taking the NII bit out of the code words to make characters (Type 2).

[0068] 3. If Dcw=+/−2 and Dni=0, it makes bit-comparison to distinguish whether the code word is Type 3ANB/C. And then it bit-manipulates the code word according to the type, runs process 2 described above again for the bit-manipulated code word to generate character (Type 3A, Type 3B and Type 3C).

[0069] If Dcw 0 and Dni=0 and c7=c5=c3=c1=NII and not c8=c6=c4 (c8≠c6 or c6≠c4 or c8≠c4), it inverts c7 and c3 in the code word, respectively. If NII of the bit-manipulated code word is 0, the decoded character is the bit-manipulated and nibble-bit-inverted code word except for NII. If NII=1, the decoded character is the code word except for NII (Type 3A).

[0070] If Dcw≠0 and Dni=0 and c7=c5=c3=c1=NII and c8=c6=c4, or if Dcw=+/−2 and Dni=0 and c8=c6=c4=c2=c0, it inverts c2 and c0 in the code word, respectively. If NII of the bit-manipulated code word is 0, the decoded character is the bit-manipulated and nibble-bit-inverted code word except for NII. If NII=1, the decoded character is the code word except for NII (Type 3B).

[0071] If Dcw≠0 and Dni=0 and c7=c5=c3=c2=c1=NII and c2=c1=c0=NII, if or Dcw 0 and Dni=0 and c7=c6=c5=c3=c1=NII and c2=c1=c0=NII, it inverts c5, c4, c3 and c2 in the code word, respectively. If NII of the bit-manipulated code word is 0, the decoded character is the bit-manipulated and nibble-bit-inverted code word except for NII. If NII=1, the decoded character is the code word except for NII (Type 3C).

[0072] 4. If Dcw=+/−2 and Dni=0, it makes bit-comparison on the code word to see whether the code word is Type 4A/B. And then it bit-manipulates the code according to the type, runs process 2 described above again to recover characters (Type 4A, Type 4B).

[0073] If Dcw≠0 and Dni=0 and c7=c5=c3=c2=c1=NII and, or if Dcw=+/−2 Dni=0 and c8=c7=c6=c4=c2=c0, it inverts c5, c4, c3, c2, and c1 in the code word, respectively. If NII of the bit-manipulated code word is 0, the decoded character is the bit-manipulated and nibble-bit-inverted code word except for NII. If NII=1, the decoded character is the code word except for NII (Type 4A).

[0074] If Dcw 0 and Dni=0 and c8=c6=c4=c2=c1=c0, or Dcw≠0 and Dni=0 and c7=c5=c3=c2=c1=NII and not c2=c1=c0=NII, or Dcw≠0 and Dni=0 and c7=c6=c5=c3=c1=NII and not c2=c1=c0=NII, it inverts c6, c5, c4, c3 and c2 in the code word, respectively. If NII of the bit manipulated code word is 0, it generates a character by taking the NII bit out of the nibble inverted code words to make characters. If NII=1, it generates a character by taking the NII bit out of the code words to make characters (Type 4B).

[0075] 5. If Dcw=+/−2 and Dni=0 and c3=NII and c8=c4=c0, or if Dcw=+/−2 and Dni=0 and c3=NII and c8=c2, then the code word is the in-band signaling/special code word. If NII of the bit manipulated code word is 0, it generates a character by taking the NII bit out of the nibble inverted code words to make characters. If NII=1, it generates a character by taking the NII bit out of the code words to make characters (Type 1B).

[0076] 6. If Dcw=+/−6 or Dcw=+/−8 or Dcw=+/−10, it means that there is a code violation.

[0077] 7. If |RDS|>6, it means that there is a code violation.

[0078] The coder and decoder for performing a NIBI coding method and a NIBI decoding method according to the present invention will be explained with reference to the accompanying drawings.

[0079] In the coding and decoding method for the NIBI as shown in FIG. 1 and2, it looks very difficult. Actually, it is very simple due to its symmetrical feature and a rule in the NIBI code and decode rule. The NIBI coder and decoder are not limited by the number of bits of the source data. If the number of bits of the source data is increased, it is hard to configure the hardware. In the present invention, the NIBI coder and decoder will be explained in the case that the source data is formed of 9-bit character for being applicable to a widely used byte (8-bit) unit application.

[0080] The construction and operation of the NIBI coder according to the present invention will now be explained with reference to FIG. 3.

[0081] The NIBI coder may be formed of a simple hardware. But, for easily maintaining a predetermined rule and symmetrical characteristic, the construction as shown in FIG. 3 is needed.

[0082] The 10-bit pre-code which is generated by adding the NII bit (310) into the position next to the LSB of the 9-bit character b(8:0) is inputted into the disparity calculator 300. The disparity calculator 300 is formed of an odd bit nibble summing unit 301, an even bit nibble summing unit 302, a complement nibble summing unit 303, a 3-bit adder 304, and an encoding type decoder and bit map controller 306.

[0083] The odd bit nibble summing unit 301 sums the number of 1 (ones) of the odd bit nibble, and the even bit nibble summing unit 302 sums the number of 1 (ones) of the even bit nibble. The complement nibble summing unit 303 does not compute the number of 1 (ones) of the odd bits inverting the odd bit nibble when computing the number of 1 with respect to the complement of the odd bit nibble and complements the result value of the odd bit nibble summing unit. The 3-bit adders 304 and 305 are a known 3-bit full adder. The first 3-bit adder 304 sums the result Dpco of the odd bit nibble summing unit 301 and the result Dpce of the even bit nibble summing unit 302 for thereby computing the disparity Dpc of the pre-code. The second 3-bit adder 305 sums the result Dnpco of the complement nibble summing unit 303 and the result Dpce of the even bit nibble summing unit 302 for thereby computing a disparity Dni of the odd bit nibble inverted pre-code. The code type encoding and bit map controller 306 encodes the coding type based on the NIBI coding method in accordance with the disparity Dpc of the pre-code, a disparity Dni of the nibble-inverted pre-code, the in-band signal, the disparity register, RDS(320) and a character and generates a control signal for manipulating the bits of the pre-code.

[0084] The RDS calculator 320 performs a function of accumulative summing the disparity of an individual code word generated by the unit of blocks and outputs a value of RDS for selecting the code word or the complement code word when the disparity of the code word is not 0.

[0085] The bit manipulator 330 selects the NIBI code type in accordance with a control signal of the code type decoding and bit map controller 306 and manipulates the bit of the pre-code for thereby generating a code word or complement code word.

[0086] The construction and operation of the NIBI decoder according to the present invention will be explained with reference to FIG. 4.

[0087] Next, the NIBI decoder may be formed in various structures as the case of NIBI coder. For implementing a simple hardware and a rule and symmetrical characteristic, the construction as shown in FIG. 4 may be implemented.

[0088] The frame synchronization or block synchronization is performed based on a unique pattern detection method used by a synchronization code character among the NIBI code words. Therefore, it is assumed that the code word inputted into the NIBI decoder is block-synchronized.

[0089] The block-synchronized code word c(8:0) NII is inputted into the disparity calculator 400.

[0090] The disparity calculator 400 includes an odd bit nibble summing unit 401, an even bit nibble summing unit 402, a complement nibble summing unit 403, 3-bit adders 404 and 405, and a decode type decoding and bit map controller 406.

[0091] The odd bit nibble summing unit 401 sums the number of 1(ones) of the odd bit nibble of the code word. The even bit nibble summing unit 402 sums the number of 1 (ones) of the even bit nibbles. The complement nibble adder 403 does not calculate the number of 1 (ones) of the complement of odd bit nibble but calculates the result value of the odd bit nibble summing unit when computing the number of 1 (ones) with respect to the complement of the odd bit nibble. The 3-bit adders 404 and 405 are a known 3-bit full adder. The first 3-bit adder 404 sums the result Dpco of the odd bit nibble summing unit 401 and the result Dcwe of the even bit nibble summing unit 402 for thereby computing the disparity Dcw of the code word. The second 3-bit adder sums the result Dncwo of the complement nibble summing unit 403 and the result Dcwe of the even bit nibble summing unit 402 for thereby computing the disparity Dni of the odd bit nibble-inverted code word. The decoding type decode and bit map controller decodes the decoding type based on the NIBI decoding method in accordance with a code word disparity Dcw, a nibble-inverted code word disparity Dni, and a code word bit pattern and generates a control signal for manipulating the bits of the code word. If the decoded decode type is Type 1B, it is an in-band signal (or special) code word, the signal SIG_OUT is outputted independently from the decoded character. In addition, the disparity Dcw of the code word and RDS are checked, and if |Dcw|>4 or |RDS|>6, a code violation signal is outputted.

[0092] The RDS calculator 420 performs a function of accumulative summing the disparity of the individual code word generated by the unit of the blocks. If |RDS|>6 in accordance with the NIBI decoding method, it represents that there is a code violation in the code word stream.

[0093] The bit manipulator 430 selects a NIBI decoding type in accordance with a control of the decoding type decode and bit map controller, manipulates the bits of the code word and recovers the original character.

[0094] As described above, in the coding and decoding method with respect to the code according to the present invention, the number of odd bits of the source data is not limited. In the construction and operation of the present invention, the source data formed of 9-bit is used for an easier understanding and application. In the NIBI coding method with respect to the source data, the bit arrangement may be changed in the method for manipulating the bits. However, the basic principle is not lost. Also, the nibble means only the bit-order-independent half code of the pre-code that one bit is added to the source data.

[0095] As described above, in the present invention, since the character formed of odd bits is coded as a code word, the present invention is applicable to a system for transmitting a source data and an out-band signal and a system and storing apparatus for transmitting at a near distance when the bit sum forming the character of the source data and the out-band character exceeds 8-bit. In the present invention, the clock recovery is implemented and the line code may be substituted with a line code which does not have a DC spectrum component used for the conventional transmission and interconnection. In addition, the present invention has the following advantages.

[0096] First, only one redundancy bit is used for a coding operation.

[0097] Second, even when the source byte is formed of bytes other than more than 90% of the coding method according to the present invention may be directly used.

[0098] Third, various frame synchronization patterns are available in the present invention.

[0099] Fourth, in-band signals and out-band signal are fully provided.

[0100] Fifth, since the code and decode rule has a symmetrical and repeating characteristic, it is possible to easily implement a hardware.

[0101] Sixth, since the coding and decoding operation is implemented based on the unit of characters, the process is implemented at a low speed.

[0102] Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as recited in the accompanying claims.