Efficient ground noise and common-mode suppression network

[0002] 1. Field of the Invention

[0003] This invention relates generally to a CMOS differential amplifier. More particularly, the present relates to a CMOS differential amplifier and method embodied therein in which ground noise and common mode suppression are improved.

[0004] 2. Description of the Related Art

[0005] In general, differential amplifiers require the amplification of differential voltages, in the presence of fluctuating common-mode voltages. Since the desired signal is usually the differential voltage, the response to the common-mode signal produces an error at the output that is indistinguishable from the signal. FIG. 1 is a circuit diagram of a conventional CMOS differential amplifier comprising transistors MN₁and MN₂, which are substantially the same size. As shown therein, the differential amplifier comprises a pair of differential inputs V_in1and V_in2to transistors MN₁and MN₂, respectively. A current source I₁is connected between V_ddof a power supply and first terminals of current sources I₂and I₃. The other terminal of current source I₂is connected to the drain of transistor MN₁, and the other terminal of current source I₃is connected to the drain of transistor MN₂. The sources of transistors MN₁and MN₂are connected to the other terminal of the power supply.

[0006] FIG. 1A shows the conventional circuit of FIG. 1 in common mode. In other words, the inputs of transistors MN₁and MN₂are connected to a common voltage source. The conventional CMOS differential amplifier is susceptible to insufficient common mode rejection or suppression. The equivalent circuit of FIG. 1A is shown in FIG. 1B, and the output voltage V_ois equal to (V_in−V_T)·A, where V_Tis the threshold voltage and A is the gain. FIGS. 2A and 2B illustrates the differential signal gain response and common-mode gain response, respectively, of the conventional CMOS differential amplifier.

[0007] CMOS differential amplifiers are also susceptible to ground noise. Ground noise may be due to, among other factors, digital switching devices inducing currents to the substrate through the depletion capacitances of the device in p-n junctions. In general, the amount of noise injected will be larger the larger the device, and the faster the transients. Argones and Rubio Experimental Comparison of Substrate Noise coupling Using Different Wafer Types, IEEE Journal of Solid State Circuits, Vol. 34, No. 10, October 1999 provides a more detailed discussion of substrate (ground) noise, the contents of which are herein incorporated by reference. FIG. 1C is a schematic diagram illustrating noise being injected through the ground node. FIG. 2B illustrates the response of ground noise gain of the conventional CMOS differential amplifier.

[0008] Therefore, it is an object of the present invention to overcome the aforementioned problems.

[0009] It is another object of the present invention to provide a CMOS differential amplifier with improved common mode rejection.

[0010] It is a further object of the present invention to provide a CMOS differential amplifier with improved ground noise rejection.

[0011] According to this invention, a CMOS differential amplifier comprises a current supply coupled to a first terminal of a power supply. A first CMOS transistor has a first source, a first drain and a first gate, the first drain being coupled to the current supply. A second CMOS transistor has a second source, a second drain and a second gate, the second drain being coupled to the current supply, and the first and second gates being inputs to the CMOS differential amplifier. A resistance is coupled between a second terminal of the power supply and the first source of the first transistor and the second source of the second transistor.

[0012] In accordance with a second aspect of the present invention, the current supply comprises a first current source coupled to the first terminal of the power supply, a second current source coupled to the first current source and the first drain of the first CMOS transistor, and a third current source coupled to the first current source and the second drain of the second CMOS transistor.

[0013] In accordance with a third aspect of the present invention, the resistance is greater than 6 ohms.

[0014] In accordance with a fourth aspect of the present invention, a method of forming a CMOS differential amplifieri is provided and comprises the step of forming a current supply on a substrate in which the current supply is coupled to a first terminal of a power supply. A first CMOS transistor is formed on the substrate having a first source, a first drain and a first gate, in which the first drain is coupled to the current supply. A second CMOS transistor is formed on the substrate having a second source, a second drain and a second gate, the first and second gates being inputs to the CMOS differential amplifier in which the second drain is coupled to the current supply. A resistance is provided between a second terminal of the power supply and the first source of the first transistor and the second source of the second transistor.

[0015] In accordance with a fifth aspect of the present invention, the resistance is selected to be greater than 6 ohms.

[0016] Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.

[0017] In the drawings wherein like reference symbols refer to like parts.

[0018] FIG. 1 is a schematic diagram of a conventional CMOS differential amplifier;

[0019] FIG. 1A is a schematic diagram of the conventional CMOS differential amplifier arranged in common mode;

[0020] FIG. 1B is a schematic diagram of an equivalent circuit of the conventional CMOS differential amplifier arranged in common mode;

[0021] FIG. 1C is a schematic diagram modeling ground noise being injected in the conventional CMOS differential amplifier;

[0022] FIG. 2A is a graph illustrating the differential signal gain of the conventional CMOS differential amplifier as compared to the CMOS differential amplifier in accordance with the present invention;

[0023] FIG. 2B is a graph illustrating the common-mode gain of the conventional CMOS differential amplifier as compared to the CMOS differential amplifier in accordance with the present invention;

[0024] FIG. 2C is a graph illustrating the ground noise gain of the conventional CMOS differential amplifier as compared to the CMOS differential amplifier in accordance with the present invention;

[0025] FIG. 3 is a schematic diagram of a CMOS differential amplifier in accordance with the present invention;

[0026] FIG. 3A is a schematic diagram of the CMOS differential amplifier of FIG. 3 arranged in common mode;

[0027] FIG. 3B is a schematic diagram of an equivalent circuit of the CMOS differential amplifier of FIG. 3 arranged in common mode;

[0028] FIG. 3C is a schematic diagram modeling ground noise being injected in the CMOS differential amplifier of FIG. 3; and

[0029] FIG. 4 is a more detail schematic diagram of the CMOS differential amplifier of FIG. 3.

[0030] Reference is now made to FIGS. 3, 3A, 3B and FIG. 3C. Shown therein is the preferred embodiment of the present invention.

[0031] FIG. 3 is a circuit diagram of a CMOS differential amplifier in accordance with the preferred embodiment of the present invention and comprises NMOS transistors MN₁and MN₂, which are substantially the same size. As shown therein, the differential amplifier comprises a pair of differential inputs V_in1and V_in2to transistors MN₁and MN₂, respectively. A current source I₁is connected between V_ddof a power supply (not shown) and first terminals of current sources I₂and I₃. The other terminal of current source I₂is connected to the drain of transistor MN₁, and the other terminal of current source I₃is connected to the drain of transistor MN₂. The sources of transistors MN₁and MN₂are connected through a resistance R to the other terminal of the power supply. Current source I₁, I₂, and I₃form a current supply.

[0032] FIG. 3A shows the preferred embodiment shown in FIG. 1 connected in common mode. The equivalent circuit of FIG. 3A is shown in FIG. 3B, and the output voltage V_ois equal to (V_in−V₁−V_T)·A, where V_Tis the threshold voltage, V₁is the voltage across the resistance and A is the gain. A comparison of the output voltages between the preferred embodiment and the conventional CMOS differential amplifier can be express as follows:

[0033] |(V_in−V₁−V_T)|<|(V_in−V_T)|  (1)

[0034] As can be appreciated by one of ordinary skill in the art, equation (1) illustrates that the common mode response has been degenerated or suppressed by an amount V₁.

[0035] FIGS. 2A and 2B illustrates the differential signal gain response and common-mode gain response, respectively, of the CMOS differential amplifier in accordance with the present invention with R having values of 6 ohms and 11 ohms. As can be seen in FIG. 2A, the differential signal gain response at 6 ohms or 11 ohms is generally the similar to the conventional CMOS differential amplifier throughout the frequency range of interest. Referring to FIG. 2B, the common mode gain is shown, in which there is an improvement of approximately 20 dB throughout the frequency range of interest.

[0036] FIG. 3C is a schematic representation to model ground noise. As shown therein, the inputs are connected in common mode to a bias voltage supply and a noise signal is injected through the resistance R.

[0037] FIG. 2C is a graph illustrating the ground noise gain for both a resistance of 6 ohms and one of 11 ohms as compared to the conventional CMOS differential amplifier. As is readily apparent, the present invention has approximately 15 to 20 dB improvement in ground noise gain over the conventional CMOS differential amplifier.

[0038] The value of resistance can be selected as follows

[0039] R=V_s/I,  (2)

[0040] where V_sis the source voltage, and I is the current through the resistance R. For example if V_s=240 mv and I=30 ma then R should preferably be 8 ohms, or if 200 mv and I=1 ma then R should preferably be 200 ohms.

[0041] FIG. 4 is an alternate embodiment of the present invention. As shown therein, current source I₁can be implemented by PMOS transistor MP₇. While current source I₂can be implemented as PMOS transistors MP₃and MP₅. Similarly current source I₃can be implemented as PMOS transistors MP₄and MP₆. As will be appreciated by one of ordinary skill in the art the implementation of current sources described above was shown only example purposes. As such, other appropriate CMOS current source configurations may be employed instead of the ones illustrated in FIG. 4.

[0042] Moreover, as will be understood by one of ordinary skill in the art, while the preferred embodiment is described with NMOS transistors MN₁, MN₂and PMOS transistors MP₃, MP₄, MP₃, MP₅, and MP₇, the polarities may be reversed.

[0043] While the invention has been described in conjunction with several specific embodiments, it is evident to those skilled in the art that many further alternatives, modifications and variations will be apparent in light of the foregoing description. Thus, the invention described herein is intended to embrace all such alternatives, modifications, applications and variations as may fall within the spirit and scope of the appended claims.