High bandwidth clock buffer

[0002] This invention relates generally to digital communications, and more specifically to clock buffers.

[0003] For many applications in integrated circuit (IC) design, the highest frequency operation for a digital logic design can generally be achieved by using a differential current steering logic family, such as bipolar emitter-coupled logic (ECL), GaAs source-coupled field-effect transistor logic (SCFL) or CMOS current mode logic (CML). While these topologies generally have inferior speed/power ratios compared to alternative logic families such as direct-coupled field-effect transistor logic (DCFL) or static CMOS, they generally operate at a two to four times higher maximum clock frequency.

[0004] For applications requiring use of these high-speed logic families, the maximum frequency of operation will eventually be limited by the ability to maintain adequate gain on the clock path through the circuit. This is due to the fact that the clock bandwidth requirement is generally twice that of data, and the clock signal will generally have to pass through several levels of buffering. Once the frequency of operation is increased beyond the unity gain bandwidth of the clock buffers, the clock signal will be attenuated through each stage of buffering, and the circuit will fail to function.

[0005] Conventional techniques for extending the bandwidth of integrated circuit clock buffers, however, suffer from various shortcomings. For example, in an approach commonly referred to as inductive peaking, an on-chip spiral inductor is added in series with a resistive load device of a differential amplifier. The inductor is sized so that at the specified operating frequency of the circuit, the reactance of the inductor partially cancels the reactance of the parasitic capacitance at the output of the differential pair. However, inductive peaking suffers from undesirable characteristics, including for example that it has a frequency dependent gain which may present a problem for low speed functionality. It also has a frequency dependent delay, particularly near the resonant frequency of the peaking. This can present a problem if the delay of the clock signal needs to be controlled with respect to other delays in the circuit. Also, the area of on-chip spiral inductors is generally quite large, on the order of a factor of ten times, as compared to the area of a typical logic gate. Finally, a circuit with inductive peaking is of limited use in buffering an arbitrary data signal with unknown frequency components.

[0006] Another conventional approach in CMOS technology utilizes multiple phases of a lower frequency clock signal. Multiple circuits can then be operated in parallel, each running off of a different phase of the clock. This type of circuit can be thought of as emulating a circuit with a virtual clock of frequency f_v=f_c* M, where f_cis the frequency of the multiphase clock, and M is the number of phases that are used in parallel. This second approach suffers from mismatches between each of the phases of the low speed clock. The consequence is an equivalent jitter on the “virtual” high-speed clock. Additionally, even if the potential problem of the clock needing to run at a frequency above the unity gain bandwidth of the clock buffers can be eliminated, a lack of sufficient bandwidth will still cause increased deterministic jitter on high-speed data signals. From a signal integrity point of view, this technique is inferior to a design in which the circuits have enough bandwidth to run off a single clock signal.

[0007] What is needed therefore is an apparatus and method for providing a high bandwidth clock buffer, which can significantly increase the maximum frequency at which CMOS technology can be used to perform high-speed logic functions.

[0008] The present invention provides, in a first aspect, a buffer including a differential amplifier for generating first and second amplified output signals in response to first and second differential amplifier input signals, a voltage follower comprising first and second voltage follower transistors for generating first and second buffer output signals in response to the first and second amplified output signals from the differential amplifier, and a steering circuit for steering current from current sources through whichever of the first and second voltage follower transistors is being pulled low to increase the amount of current.

[0009] In another aspect, the present invention provides a method for buffering signals, including the steps of generating first and second amplified output signals using a differential amplifier in response to first and second differential amplifier input signals, generating first and second buffer output signals in response to the first and second amplified output signals from the differential amplifier using a voltage follower comprising first and second voltage follower transistors, and steering current from current sources through whichever of the first and second voltage follower transistors is being pulled low to increase the amount of current that is available.

[0010] These and other features and advantages of this invention will become further apparent from the detailed description and accompanying figures that follow. In the figures and description, numerals indicate the various features of the invention, like numerals referring to like features throughout both the drawing figures and the written description.

[0011] FIG. 1 is a block diagram of a high bandwidth CML buffer in accordance with the present invention.

[0012] Referring to FIG. 1, a high bandwidth clock buffer 10, including a steering circuit 12, significantly increases the maximum frequency at which CMOS technology can be used to perform high speed logic functions. As described in detail below, the clock buffer 10 provides a higher unity gain bandwidth than a standard CML buffer, while maintaining a well controlled delay which will track other logic gates. Use of the clock buffer 10 can extend the maximum frequency at which CMOS technology can be used without resorting to a multiphase clocking architecture, with its inherent drawbacks.

[0013] In particular, the clock buffer 10 includes the steering circuit 12 for enhancing a voltage follower stage 14 of the clock buffer 10. The steering circuit 12 includes switching transistors 16, 18, 20 and 22 positioned between voltage follower transistors 24 and 26 and current sources 28 and 30. The steering circuit 12 switches all or substantially all of currents from both sources 28 and 30 through whichever of the two voltage follower transistors 24 or 26 is being pulled low, thus approximately doubling an amount of current that is available for slewing when an output is being pulled low. At the same time, since the voltage follower transistor 24 or 26 that is being pulled high no longer has to source a constant current I₀provided by sources 28 and 30, an effective maximum current that can be supplied to charge up a load capacitance is increased by I₀.

[0014] As illustrated in FIG. 1, an input signal B and its complementary input BN are coupled to a differential amplifier 38, which includes a pair of differential amplifier transistors 40 and 42 that in conjunction with load resistors 44 and 46 provide a voltage gain of input signals B and BN. In particular, the input signal B is coupled to a gate 50 of the differential amplifier transistor 42 and the complementary input signal BN is coupled to a gate 48 of the differential amplifier transistor 40. Drains 52 and 54 of the differential amplifier transistors 40 and 42 are coupled to differential amplifier output signals ZA 56 and ZAN 58, respectively. The drains 52 and 54 are also coupled to a VDD supply 60 via load resistors 44 and 46, respectively. The load resistor 44 is coupled to the differential amplifier transistor 40 and the voltage follower transistor 24. The load resistor 46 is coupled to differential amplifier transistor 42 and voltage follower transistor 26. Load resistors 44 and 46 are typically implemented as PMOS devices biased in the linear region. Source terminals 62 and 64 of the differential amplifier transistors 40 and 42 are coupled at a junction 66 so as to share a common current I_d68 coupled to a VSS supply 70.

[0015] The differential amplifier output signals ZA 56 and ZAN 58 drive the low output impedance voltage follower 14, which produces clock buffer output signals ZB 80 and ZBN 82. In a typical configuration, a substantial portion of the gain for the clock buffer 10 occurs in the differential amplifier stage 38.

[0016] In particular, the voltage follower 14 includes the voltage follower transistors 24 and 26, drains 72 and 74 of which are coupled to the VDD supply 60. Gates 76 and 78 of the voltage follower transistors 24 and 26 are coupled to the differential amplifier output signals ZA 56 and ZAN 58. The voltage follower stage 14 of the clock buffer 10 has no mechanism for gain, and thus has a gain which is at most unity. Due mainly to a body effect in CMOS, however, the gain is typically limited to approximately 0.9.

[0017] In operation, when the voltage follower transistor 24 is pulled high, it must temporarily source more current than I₀. This excess current, defined approximately by an equation (I_M3−I₀), is responsible for charging a load capacitance of a clock buffer output signal ZB 80. A maximum slew rate when the output signal ZB 80 is being pulled high is degraded by I₀. Similarly, when the voltage follower transistor 24 is pulled low, it must temporarily source a current less than I₀, and this difference in current, defined approximately by an equation (I₀−I_M3), is used to discharge the load capacitance of the clock buffer output signal ZB 80. The maximum slew rate when the output signal ZB 80 is being pulled low is thus set by the constant current I₀. The voltage follower transister 26 operates in an identical manner to charge and discharge a load capacitance of a complementary clock buffer output signal ZBN 82.

[0018] In accordance with the present invention, the voltage follower 14 is enhanced by adding the steering circuit 12 between the voltage follower transistors 24 and 26 and the current sources 28 and 30. In particular, the steering circuit 12 includes steering transistors 16, 18, 20 and 22 positioned between the voltage follower transistors 24 and 26 and the current sources 28 and 30. Source terminals 84 and 86 of the voltage follower transistors 24 and 26 provide the clock buffer output signals ZB 80 and ZBN 82. The source terminals 84 and 86 are also coupled to the steering circuit 12, which includes the switching transistors 16, 18, 20 and 22.

[0019] In accordance with an advantage of the present invention, the steering transistors 16, 18, 20 and 22 switch all or approximately all of the current from both sources 28 and 30 through whichever of the two voltage follower transistors 24 or 26 is being pulled low, thus approximately doubling the amount of current that is available for slewing when the corresponding clock buffer output signal is being pulled low. At the same time, since the voltage follower transistor 24 or 26 that is being pulled high no longer has to source the constant current I₀, the effective maximum current that can be supplied to charge up the corresponding load capacitance is increased by I₀.

[0020] As illustrated in FIG. 1, a drain 92 of the switching transistor 16 is coupled to a gate 98 of the switching transistor 18, and a drain 94 of the switching transistor 18 is coupled to a gate 96 of the switching transistor 16. Current sources 88 and 90 are coupled to the drains 92 and 94 so that the voltage follower transistors 24 and 26 do not completely shut off when they are in a static logic high state. This prevents output nodes from going to a high impedance state in which an output voltage level would not be well controlled.

[0021] The additional current sources 88 and 90 need only be a fraction of a size of the main current sources 28 and 30 and are coupled to common VSS supply 70. Source terminals 100 and 102 of switching transistors 16 and 18 are coupled at junction 104 so as to share a common current coupled to the common VSS supply 70.

[0022] Drains 106 and 108 of the steering transistors 20 and 22 are coupled to the sources 84 and 86 of the voltage follower transistors 24 and 26 and the drains 92 and 94 of the steering transistors 16 and 18. The input signal B and the complementary input signal BN are coupled to the steering transistors 22 and 20 which provide a voltage gain of the input signals B and BN. The input signal B is coupled to a gate 116 of the steering transistor 22 and the complementary input signal BN is coupled to a gate 114 of the steering transistor 20. The drains 106 and 108 of the steering transistors 20 and 22 are coupled to the clock buffer outputs ZB 80 and ZBN 82. Sources 110 and 112 of the steering transistors 20 and 22 are coupled at a junction 118 so as to share a common current coupled to the VSS supply 70.

[0023] From a DC standpoint, a current steering accomplished by the steering transistors 16, 18, 20 and 22 could be controlled by either the input signals B and BN or the clock buffer output signals ZB 80 and ZBN 82, since both of these differential signals have the same or approximately the same DC values. To balance rise and fall times of the clock buffer output signals ZB 80 and ZBN 82, half of the current steering in the voltage follower stage 14 is controlled by the input signals B and BN, and the other half by the clock buffer output signals ZB 80 and ZBN 82. The rise time of the output signals is dominated by the amplified signals ZA 56 and ZAN 58 while the fall time is dominated by the switching transistors 16, 18, 20 and 22. Since the input signals B and BN are ahead of the amplified signals ZA 56 and ZAN 58 in time, and the clock buffer output signals ZB 80 and ZBN 82 are behind the amplified signals ZA 56 and ZAN 58 in time, the combination of both the input signals B and BN and the clock buffer output signals ZB 80 and ZBN 82 to control the current steering in the voltage follower stage 14, approximately balances the rise and fall times of the clock buffer output signals ZB 80 and ZBN 82.

[0024] In a typical operation, the clock buffer 10 possesses a gain greater than approximately 1.0 in the voltage follower stage 14. The transistors 40, 42, 24, 26, 16, 18, 20 and 22 are preferably FET transistors although one skilled in the art will recognize that the clock buffer 10 can be adapted such that other types of transistors may be used as well.

[0025] Having now described the invention in accordance with the requirements of the patent statutes, those skilled in this art will understand how to make changes and modifications in the present invention to meet their specific requirements or conditions. For example, one skilled in the art will recognize that the components identified above may be coupled directly or indirectly to each other. Such changes and modifications may be made without departing from the scope and spirit of the invention as set forth in the following claims.