CMOS dynamic logic circuitry using quantum mechanical tunneling structures

[0002] This application claims priority under 35 USC §119(e)(1) of provisional application Ser. No. 60/154,290 filed Sep. 19, 1999.

[0004] The present invention relates, in general, to logic circuitry used in electronic devices, and in particular, to dynamic logic circuitry designed for a Complementary Metal Oxide Semiconductor (CMOS) process including quantum mechanical tunneling structures.

[0005] The continual demand for enhanced transistor and integrated circuit performance has resulted in improvements in existing devices, such as silicon, bipolar, and Complementary Metal Oxide Semiconductor (CMOS) transistors and Galium Arsenide (GaAs) transistors, and also in the introduction of new device types and materials. In particular, scaling down device sizes to enhance high frequency performance leads to observable quantum mechanical effects, such as carrier tunneling through potential barriers. These effects led to development of alternative device structures which take advantage of such tunneling phenomenon; such as tunneling, and resonant tunneling, diodes and transistors. For ease of reference, all such structures are hereafter collectively referred to as tunneling diodes (TDs).

[0006] Tunneling diodes are generally two terminal devices with conduction carriers tunneling through potential barriers to yield current-voltage curves with portions exhibiting negative differential resistance (NDR). This negative differential resistance characteristic has been used as the basis for a wide range of high performance designs.

[0007] Conventionally, tunneling and resonant tunneling diodes have been limited in implementation to GaAs and other high performance processes. Conventional methods have focused on building TDs in GaAs for several reasons; mainly because the speed characteristics and small process features of GaAs processes were conducive to tunneling mechanics. However, performance considerations such as difficulty controlling peak current in TDs, limited their practical application and use. Additionally, since GaAs processes were not practical or cost efficient for high-volume, consumer-related production, TDs were generally limited in application to research and developmental applications.

[0008] Previously, the feature sizes of standard silicon processes, such as CMOS, were not conducive to producing such tunneling structures. Other conventional methods of utilizing tunneling structures in conjunction with standard silicon processes entailed fabrication of a TD structure in a non-silicon process, followed by transferring and bonding (or electrically coupling) the TD structure to a host silicon substrate. While certain performance issues may have thus been addressed, such a process required extra design time and processing steps. The additional design and fabrication costs associated with these approaches is therefore not commercially viable for large volume logic device production.

[0009] Thus, conventional implementations of tunneling structures have been used only in discrete form and niche applications, such as high speed pulse and edge generation; produced in costly, high-performance processes. Limitations to conventional tunneling structures include the difficulty in controlling peak current and the lack of an integrated circuit process capable of commercially producing tunneling structures in a commercially viable format.

[0010] In the absence of commercially viable TDs, conventional CMOS logic circuit designs have utilized functional components readily available in the CMOS process, such as inverters and logic and transmission gates. Conventional methods have focused on optimizing the design of these components individually, and improving their efficiency when utilized within larger circuits. Still, such conventional methods inevitably yield device inefficiency; due mainly to layout area, power consumption, and operational speed limits resulting from standard CMOS components.

[0011] As performance demands have increased and feature sizes for CMOS processes have decreased, fabrication of tunneling structures in a production CMOS process becomes feasible. Tunnel diode growth on silicon is relatively immature. Recently, CMOS compatible tunnel diodes have been demonstrated to show that a wide range of current densities can be obtained; addressing requirements for imbedded memory and signal processing applications.

[0012] Therefore, a system of logic circuitry designs incorporating tunneling structures for a CMOS process is now needed; providing enhanced design performance and efficiency while overcoming the aforementioned limitations of conventional methods.

[0013] Dynamic logic circuitry is used extensively in modern electronics systems and devices. Dynamic logic, being denser and more efficient than static logic implementations typical of CMOS designs, is widely used in demanding high-performance applications. As such, dynamic logic is prevalent in the design of systems such as signal processing units, encoding and decoding devices, and circuitry performing intensive mathematical operations.

[0014] In the present invention, dynamic logic circuitry is designed for a CMOS process including quantum mechanical tunneling structures; providing circuit layout area, power consumption, and operational speed advantages over conventional methods. NDR and current-voltage (I-V) characteristics of tunneling structures are exploited to provide high-performance, high functionality logic circuitry. Tunneling structures are utilized, replacing conventional CMOS components, to address MOS leakage and hold data state in dynamic logic circuits.

[0015] In one embodiment of the present invention, a dynamic logic network is designed incorporating tunneling diodes. The tunneling diodes replace a number of components used in conventional designs, providing high system performance with optimum design overhead.

[0016] For a more complete understanding of the features and advantages of the present invention, reference is now made to the detailed description of the invention along with the accompanying figures in which corresponding numerals in the different figures refer to corresponding parts and in which:

[0017] FIG. 1 is a schematic of a prior art CMOS dynamic logic circuit;

[0018] FIG. 2 is a schematic of a prior art CMOS dynamic logic circuit;

[0019] FIG. 3 is an illustrative embodiment of a CMOS dynamic logic circuit incorporating tunneling diodes according to the present invention;

[0020] FIG. 4 is a graph illustrating characteristics of the circuit of FIG. 3.

[0021] While the making and using of various embodiments of the present invention are discussed in detail below, it should be appreciated that the present invention provides many applicable inventive concepts which can be embodied in a wide variety of specific contexts. The specific embodiments discussed herein are merely illustrative of specific ways to make and use the invention and do not delimit the scope of the invention.

[0022] The present invention defines logic circuitry employing tunneling structures in a homogenous silicon process; providing increased performance and design optimization. The present invention provides reduced circuit complexity for dynamic logic circuits; decreasing the number of circuit components used, the number of interconnects, and the number of delay stages. The present invention thus realizes a significant reduction in layout area, operation delay, and power consumption over conventional methods. NDR and current-voltage (I-V) characteristics of tunneling structures are exploited to provide high-performance, high functionality logic circuitry.

[0023] For purposes of illustration, dynamic logic network circuitry utilizing resonant tunneling diodes (RTDs) is provided. However, the principles and applications of the present invention are not limited to just resonant tunneling diodes; being applicable to tunneling structures in general and hereafter collectively referred to as tunneling diodes (TDs). TDs are desirable for use in high performance logic circuit applications due to the fact that their switching speed is generally faster than standard MOS structures. TDs are well-known for their intrinsic bi-stability and high-speed switching capability due to their negative differential resistance (NDR) characteristic. High current density, low capacitance, and the NDR of TDs make them very fast non-linear circuit elements. These same device characteristics can be exploited in high-speed, low-power, digital logic circuits. Thus, in most general purpose applications, where a large fraction of the circuits may be idle at any given time, the present invention provides a significant advantage over conventional methods because CMOS structures have lower tunnel power dissipation due to very low static power consumption.

[0024] Referring now to FIG. 1, a schematic representative of a prior art dynamic logic circuit 100 is shown. Circuit 100 implements an np-CMOS type of dynamic logic circuit, comprising multiple, serially-chained, stages such as n-type stage 102 and p-type stage 104. Stage 102 comprises pre-charge element 106 intercoupled between node 108 and a supply voltage (V_CC), and discharge element 110 intercoupled between node 108 and ground. Pre-charge element 106 comprises transistor 112 having a first terminal coupled to V_CC, a second terminal coupled to node 108, and an inverting base terminal coupled to a clock (CK) input 114. Discharge element 110 comprises an evaluation transistor 116 in combination with a network of transistors 118, 120, and 122. Transistor 116 has a first terminal coupled to node 124, a second terminal coupled to ground, and a base terminal coupled to clock input 114. Transistors 118 and 120 are coupled serially between nodes 108 and 124, having base inputs A and B, respectively. Transistor 122 is coupled between nodes 108 and 124 in parallel to transistors 118 and 120, and has base input C. Transistors 118-122 thus implement the Boolean condition 126 shown with the circuit.

[0025] Upon appropriate timing as relayed by clock input 114, typically referred to as the pre-charge phase, element 106 operates to raise the output voltage for stage 102, as measured at node 108, to a desired level(e.g. high or “1”). Responsive to input 114, circuit 100 then transitions into an evaluation phase, in which discharge element 110 plays a part. During evaluation phase, transistor 116 turns on, effectively evaluating the status of condition 126 as implemented by transistors 118-122. If condition 126 is satisfied, a path from node 108 to ground will be established through transistor 116 and either transistor 122 or the combination of transistors 118 and 120. Once this path to ground is established, the voltage at node 108 will be discharged to a low level, shifting the output of stage 102. Stage 104 is structured and operates similarly to stage 102, responsive to inverse clock input 128.

[0026] Such a design suffers negative impacts of MOS leakage. Circuit 100 as shown requires frequent refreshing to maintain the desired level at node 108. If circuit 100 is not so refreshed, voltage at node 108 my erroneously transition due to leakage, leading to data errors and system reliability issues. Consistent refresh ultimately results in significant increases in power consumption for such conventional systems.

[0027] FIG. 2 illustrates a prior art attempt at dynamic logic circuitry 200 to overcome the limitations of circuits such as circuit 100. Circuit 200 implements a domino type of CMOS dynamic logic circuit, comprising multiple, serially-chained, stages such as stages 202 and 204. Stage 202 comprises essentially the same elements as stage 102 of FIG. 1 does; including pre-charge element 106 intercoupled between node 108 and a supply voltage (V_CC), and discharge element 110 intercoupled between node 108 and ground. Additionally, stage 202 comprises a charge hold element 206 intercoupled between node 108 and node 208. Output voltage for stage 202 is measured at node 208. Charge hold element 206 comprises transistor 210 having a first terminal coupled to V_CC, a second terminal coupled to node 108, and an inverting base terminal coupled to node 208. Hold element 206 further comprises inverter element 212 having an input coupled to node 108 and an output coupled to node 208. As described in reference to FIG. 1, transistors 118 and 120 are coupled serially between nodes 108 and 124, having base inputs A and B, respectively, and transistor 122 is coupled between nodes 108 and 124 in parallel to transistors 118 and 120 having base input C. Transistors 118-122 implement the Boolean condition 216 shown with the circuit.

[0028] Stage 202 operates through the pre-charge and evaluation modes responsive to clock input 114 as previously described. Transistor 210 and inverter 212 effectively form a loop used to address MOS leakage current effects on the node 108 voltage. Thus, once node 108 has been pre-charged, hold element 206 operates to keep the voltage at node 108 stable until condition 216 is satisfied and discharge element 110 discharges that voltage to a low level.

[0029] Although overcoming some of the power and reliability limitations of designs without charge hold elements, these designs still suffer negative effects of additional circuit elements. Design layout area is increased; negatively impacting device size, speed, and power consumption for such CMOS designs.

[0030] In contrast to these conventional approaches, FIG. 3 illustrates a dynamic logic circuit 300 according to the present invention. For purposes of illustration, circuit 300 implements an np-CMOS type of dynamic logic circuit, comprising multiple, serially-chained, stages including n-type stage 302 and p-type stage 304. As should be apparent to those of skill in the art, the principles and teachings of the present invention will be equally applicable to other dynamic logic circuits and configurations. Stage 302 comprises pre-charge element 306 intercoupled between node 308 and a supply voltage (V_CC), and discharge element 310 intercoupled between node 308 and ground. Pre-charge element 306 comprises transistor 312 having a first terminal coupled to V_CC, a second terminal coupled to node 308, and an inverting base terminal coupled to a clock (CK) input 314. Discharge element 310 comprises an evaluation transistor 316 in combination with a network of transistors 318, 320, and 322. Transistor 316 has a first terminal coupled to node 324, a second terminal coupled to ground, and a base terminal coupled to clock input 314. Transistors 318 and 320 are coupled serially between nodes 308 and 324, having base inputs A and B, respectively. Transistor 322 is coupled between nodes 308 and 324 in parallel to transistors 318 and 320, and has base input C. Transistors 318-322 thus implement the Boolean condition 326 shown with the circuit.

[0031] During pre-charge phase, element 306 operates to raise the output voltage for stage 302, as measured at node 308, to a desired level(e.g. high or “1”). Stage 302 further comprises charge hold element 328 intercoupled between node 308 and V_CC. Element 328 comprises a resonant tunneling diode 330 having a first terminal coupled to node 308 and a second terminal coupled to V_CC. Element 328 operates to keep the voltage at node 308 stable until condition 326 is satisfied, discharging that voltage to a low level. Responsive to input 314, circuit 300 transitions into evaluation phase, in which transistor 316 turns on, effectively evaluating the status of condition 326 as implemented by transistors 318-322. If condition 326 is satisfied, a path from node 308 to ground will be established through transistor 316 and either transistor 322 or the combination of transistors 318 and 320. Once this path to ground is established, the voltage at node 308 will be discharged to a low level, shifting the output of stage 302. Stage 304 is structured and operates similarly to stage 302, responsive to inverse clock input 332.

[0032] Thus, by the present invention, diode 330 provides a state hold functionality compensating MOS leakage currents, stabilizing node 308 voltage, and providing a high reliability system.

[0033] FIG. 4 illustrates one advantage of the present invention. A current-voltage plot 400 shows critical characteristics of circuit 300.

[0034] Referring now jointly to FIGS. 3 and 4, curve 402 represents collective leakage current effects of transistors 316-322 while curve 404 represents the current-voltage characteristic of diode 330. Equilibrium state 406 represents a point at which the tunneling diode current equals the leakage current. Diode 330 thus compensates for the leakage current; the high peak current of diode 330 holds the voltage at node 308 at a high level. Errors resulting from leakage current are thus eliminated. The present invention thus provides high stability and overall design reliability.

[0035] With the present invention, a tunneling diode structure eliminates unnecessary inverter and transistor circuitry from a dynamic logic circuit. This results in CMOS/TD dynamic logic designs by the present invention having substantially smaller area, substantially higher speed, and substantially lower power consumption in comparison with conventional CMOS counterparts.

[0036] While this invention has been described in reference to illustrative embodiments, this description. is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.