Digital calibration method and apparatus for A/D or D/A converters

[0002] Digital Calibration Method and Apparatus for A/D or D/A Converters

[0003] The present invention relates generally to calibration methods and apparatus for calibrating A/D (Analog-to-Digital) or D/A (Digital-to-Analog) converters, and more particularly to an improved calibration method and apparatus for performing digital calibration on A/D and D/A converters employed in IC testers which test various electrical characteristics of IC (Integrated Circuit) devices.

[0004] In order to ship factory-fabricated IC devices as final products with performance and quality assurances, it is generally necessary to extract some or all of the IC devices and examine predetermined electrical characteristics of the extracted IC devices at manufacturing and testing stages in the factory. Normally, the electrical characteristics of the IC devices are examined by the so-called IC testers. Typically, the IC tester first sends predetermined test pattern data to each of the IC devices to be tested (hereinafter “to-be-tested IC device”) and then reads output data produced from the IC device in response to the test pattern data sent thereto, on the basis of which the tester examines the IC device's electrical characteristics and determines whether or not the to-be-tested IC device has any trouble with its essential behavior and functions.

[0005] The tests performed by the IC testers can be roughly classified into a direct current test (i.e., DC measurement test) and a function test. In the direct current test, each to-be-tested IC device is checked for presence of trouble with its essential behavior by a DC measurement section applying a predetermined voltage or current to input/output terminals of the IC device. In the function test, on the other hand, predetermined test pattern data is fed from a pattern generation section to the input terminal of the to-be-tested IC device and output data produced from the IC device in response to the test pattern data is analyzed to determine whether the to-be-tested IC device has any trouble with its essential behavior and functions. More specifically, the function test supplies the to-be-tested IC device with various input signals, such as an address, data, write-enable signal and chip-select signal, while variously changing input conditions of the signals and then inspects timing, amplitudes, etc. with which the IC device generates output signals in response to the input signals. Because many A/D and D/A converters are generally employed in each of such IC testers, accurate adjustment or calibration (including gain calibration and offset calibration) of these A/D and D/A converters is extremely essential for high-accuracy tests of the factory-fabricated IC devices.

[0006] So far, the adjustment or calibration of the AD and D/A converters has been performed either in a manual manner based on manipulation of a trimmer resistor by a human operator or in an analog manner using an auxiliary D/A converter and digital potentiometer.

[0007] However, the above-mentioned manual calibration scheme using the trimmer resistor is disadvantageous in that it would take considerable amounts of time and human labor and thus can not be used suitably for the IC testers requiring calibration of many A/D and D/A converters. The analog calibration scheme, on the other hand, often proves very efficient because it can be performed automatically without any human labor. But, the accuracy of the analog calibration tends to deteriorate due to the nature of analog components or elements used. Further, because the analog calibration scheme calculates calibration coefficients through the “binary search” or “least square” method, it would take an extra amount of time for the calculation of the calibration coefficent.

[0008] It is therefore an object of the present invention to provide a digital calibration method and apparatus which can perform calibration of A/D and/or D/A converters in a digital manner. More specifically, the object of the present invention is to provide a digital calibration method and apparatus which can perform digital calibration of a great number of A/D and/or D/A converters at increased efficiency.

[0009] To accomplish the above-mentioned object, the present invention provides a digital calibration method for an analog-to-digital converter, which comprises the steps of: inputting at least two different reference analog signals to an analog-to-digital converter to be adjusted or calibrated; calculating calibration parameters on the basis of digital converted signals outputted by the analog-to-digital converter in response to input of the corresponding reference analog signals thereto; and performing calibrating arithmetic operations on an output digital signal from the analog-to-digital converter using the calibration parameters calculated by the calculating step. In the present invention, the above-mentioned calibration parameters may include an offset calibration value and gain calibration coefficient.

[0010] According to the present invention, predetermined calibration parameters, such as an offset calibration value and gain calibration coefficient, are calculated on the basis of digital converted signals outputted by the analog-to-digital converter in response to input of the corresponding reference analog signals, and then an output digital signal from the analog-to-digital converter is digitally adjusted or calibrated on the basis of the thus-calculated calibration parameters. With such arrangements, the present invention can eliminate a need for analog components or elements and thus can avoid unwanted influences, such as measurement errors, that would be caused by such analog elements. Further, because the offset calibration value and gain calibration coefficient are determined on the basis of the digital converted signals corresponding to the two reference signals, the calibration can be performed with increased accuracy at increased speed as compared to the conventional binary search or least square method. Therefore, the present invention can significantly reduce the necessary calibrating time even in a case where the calibration is performed on a great number of A/D converters employed in an IC tester or the like.

[0011] The present invention also provides a digital calibration method for a digital-to-analog converter, which comprises the steps of: inputting at least two different reference digital signals to a digital-to-analog converter to be calibrated; calculating calibration parameters on the basis of analog converted signals outputted by the digital-to-analog converter in response to input of the corresponding reference digital signals thereto; and performing calibrating arithmetic operations on the basis of an input digital signal to the digital-to-analog converter using the calibration parameters calculated by the calculating step. The above-mentioned calibration parameters may include an offset calibration value and gain calibration coefficient. Further, the aforementioned step of calculating may include a step of converting, into a digital signal, each of the analog converted signals outputted by the digital-to-analog converter in response to input of the corresponding reference digital signal and a step of calculating the calibration parameters on the basis of each of the digital signals provided by the step of converting.

[0012] According to this method, predetermined calibration parameters, such as an offset calibration value and gain calibration coefficient, are calculated on the basis of analog converted signals outputted by the digital-to-analog converter in response to input of the corresponding reference digital signals, and then an input digital signal to the digital-to-analog converter is digitally adjusted or calibrated on the basis of the thus-calculated calibration parameters. With such arrangements, the inventive method can eliminate a need for analog elements and thus can avoid unwanted influences, such as measurement errors, that would be caused by such analog elements. Further, the inventive method can significantly reduce the necessary calibrating time even in a case where the calibration is performed on a great number of D/A converters employed in an IC tester or the like.

[0013] The present invention may be implemented not only as a method invention as set forth above but also as an apparatus invention. The present invention may also be practiced as a program for execution by a processor such as a CPU or DSP, as well as a storage medium storing such a program.

[0014] For better understanding of the object and other features of the present invention, its preferred embodiments will be described in greater detail hereinbelow with reference to the accompanying drawings, in which:

[0015] FIG. 1 is a block diagram showing an exemplary setup and behavior of a digital calibration apparatus in accordance with a preferred embodiment of the present invention which performs digital calibration on an A/D converter;

[0016] FIG. 2 is a graph explanatory of the digital calibration of the present invention, which shows examples of ideal and actual conversion characteristics of an A/D converter to be calibrated;

[0017] FIG. 3 is a flow chart showing an example of a calibrating program executed by a CPU of FIG. 1;

[0018] FIG. 4 is a block diagram showing an exemplary setup and behavior of a digital calibration apparatus of the present invention which performs digital calibration on a D/A converter; and

[0019] FIG. 5 is a flow chart showing an example of a calibrating program executed by a CPU 4 of FIG. 4.

[0020] FIG. 1 is a block diagram showing an exemplary setup and behavior of a digital calibration apparatus in accordance with a preferred embodiment of the present invention which performs digital calibration on an A/D converter (ADC) 1. In the illustrated example of FIG. 1, the A/D converter 1 receives an analog signal and converts it into digital representation to thereby output digital signal D1 corresponding to the analog signal. Adder 2 adds together the digital signal D1 from the A/D converter 1 and offset calibration value DO given from an offset register 6 and supplies a multiplier 3 with digital signal D2 that is indicative of the added result. The multiplier 3 multiplies the digital signal D2 from the adder 2 by gain calibration coefficient DG given from a gain register 7 and outputs, to a tester bus (T-BUS) 5, digital signal D3 that is indicative of the multiplication result. The digital signal D3 thus output to the tester bus 5 is then delivered to a predetermined arithmetic operator section for necessary arithmetic processing.

[0021] The following paragraphs describe how the above-mentioned offset calibration value DO and gain calibration coefficient DG are calculated in the preferred embodiment, with reference to FIG. 2. Specifically, FIG. 2 shows an ideal conversion characteristic LO and actual conversion characteristic L1 of the A/D converter. Namely, it is assumed here that the A/D converter 1 of FIG. 1 actually indicates the conversion characteristic L1 deviating from the ideal conversion characteristic L0 as shown here in FIG. 2. Thus, in the preferred embodiment, offset calibration value DO and gain calibration coefficient DG are calculated on the basis of the ideal conversion characteristic L0 and actual conversion characteristic L1, and the digital converted signal D1 output from the A/D converter 1 is converted into digital signal D3 conforming to the ideal conversion characteristic L0 shown in FIG. 2.

[0022] For example, according to the ideal conversion characteristic L0 of FIG. 2, a digital signal of predetermined value V12 (“7FFF” in the hexadecimal notation) is supposed to be output from the A/D converter in response to input of a positive full-scale analog signal voltage 10V, and a digital signal of predetermined value V11 (“8000” in the hexadecimal notation) is supposed to be output from the A/D converter in response to input of a negative full-scale analog signal voltage −10V. However, let's assume here that the actual A/D converter 1 outputs the digital signal D1 of digital value V02, different from the above-mentioned ideal value V12, in response to input of the analog signal voltage of 10V and outputs the digital signal D1 of digital value V01, also different from the above-mentioned ideal value V11 in response to input of the analog signal voltage of −10V.

[0023] Thus, in the illustrated example of FIG. 1, a CPU 4 first stores offset calibration value DO (=“0”) and gain calibration coefficient DG (=“1”) into the offset register 6 and gain register 7, respectively. Then, the CPU 4 inputs a predetermined first reference analog signal, e.g. positive full-scale analog signal voltage 10V, to the A/D converter 1 and then receives digital converted signal D1 that is output from the A/D converter 1 in response to input of the first reference analog signal, namely, digital signal D3 (=V02) output from the multiplier 3. Next, the CPU 4 inputs a predetermined second reference analog signal, e.g. negative full-scale analog signal voltage 10V, to the A/D converter 1 and then receives digital converted signal D1 output from the A/D converter 1 in response to input of the second reference analog signal, namely, digital signal D3 (=V01) that is output from the multiplier 3. Upon receipt of the digital signals D3 (=V02 and V01) corresponding to the positive and negative full-scale analog signals, the CPU 4 calculates offset calibration value DO and gain calibration coefficient DG using the following equations:

[0024] DO=(V02+V01)/2

[0025] DG=(V12−V11)/(V02−V01)

[0026] The thus-calculated offset calibration value DO and gain calibration coefficient DG are then stored into the offset register 6 and gain register 7, respectively. From that time on, the output signals DO and DG stored in the registers 6 and 7 will be fed to the adder 2 and multiplier 3 as calibration parameters.

[0027] In this way, each digital signal D1 subsequently output from the A/D converter 1 is adjusted or calibrated in accordance with the calibration parameters DO and DG via the adder 2 and multiplier 3, so as to present the ideal A/D conversion characteristic L0 as shown in FIG. 2. Thus, according to the preferred embodiment of the present invention, the necessary calibration can be performed automatically by the CPU 4 in a digital fashion, so that it is possible to eliminate a need for human labor. Further, because no analog components or elements are employed for the calibration, the preferred embodiment can avoid degradation of the calibrating accuracy that would result from various drifts and limitations to accuracy of the analog elements (appearing as an offset, resistance error, etc.). Furthermore, because the calibration can be performed with increased accuracy at increased speed as compared to the conventional binary search or least square method, the preferred embodiment can significantly reduce the necessary calibrating ti me even in a case where the calibration is performed on a great number of A/D converters employed in an IC tester or the like. In such a case, the above-mentioned registers 6 and 7 store the calibration parameters DO and DG for each of the A/D converters, and the same CPU 4 can be shared among the A/D converters.

[0028] For reference purposes, FIG. 3 shows a n example of a calibrating program that is executed by the CPU 4 of FIG. 1 to carry out the above-mentioned arithmetic operations. At first step S1, the calibration parameters DO and DG are set to values “0” and “1”, respectively, and then stored into the respective registers 6 and 7. At next step S2, it is ascertained whether or not first reference analog signal Vr1 has been input to the A/D converter 1. Note t hat the input of the first reference analog signal Vr1 may be performed either manually or automatically under the control of the CPU 4. For the automatic input, it is only necessary that an instruction for generating the reference analog signal Vr1 be given at this step S2 so that an analog voltage generator or reference D/A converter (not shown) is caused to generate the reference analog signal Vr1. For the manual input, on the other hand, an analog voltage generator or reference D/A converter (not shown) generates the reference analog signal Vr1 to be input to the A/D converter 1, then input confirmation information is given to the CPU 4 via user's activation of a predetermined switch or otherwise, and this step S2 checks whether or not the input confirmation information has been actually given to the CPU 4. When it is ascertained at step S2 that the reference analog signal Vr1 has been input to the A/D converter 1, the program proceeds to step S3, where digital converted signal D1 generated by the A/D converter 1 converting the reference analog signal Vr1, i.e. digital signal D3 processed through the adder 2 and multiplier 3, is supplied to the CPU 4 and stored as digital value V01. In this case, a condition of “D1=D2=D3” has been established because the offset calibration value DO is currently set at “0” and the gain calibration coefficient DG is currently set at “1”. In the above-described example, the first reference analog signal Vr1 has a voltage value of −10V, and digital converted signal V01 corresponding to the first reference analog signal Vr1 can not take a correct or ideal digital value of 31 10V as shown in FIG. 2 as long as the A/D converter 1 has a conversion error.

[0029] Then, at step S4, it is ascertained whether or not second reference analog signal Vr2 has been input to the A/D converter 1. Similarly to the above-mentioned first reference analog signal Vr1, the input of the second reference analog signal Vr2 may be performed either manually or automatically under the control of the CPU 4. At next step S5, digital converted signal D1 generated by the A/D converter 1 converting the second reference analog signal Vr2, i.e. digital signal D3 processed through the adder 2 and multiplier 3, is supplied to the CPU 4 and stored as digital value V02. At following step S6, ideal digital values V11 and V12 corresponding to the first and second reference analog signals Vr1 and Vr2 are acquired. These ideal digital values V11 and V12 are determined automatically depending on the specific values of the first and second reference analog signals Vr1 and Vr2. Then, at step S7, the same arithmetic operations as noted earlier are performed, on the basis of the stored digital values V01 and V02 and ideal digital values V11 and V12, to calculate offset calibration value DO and gain calibration coefficient DG. At next step S8, the offset calibration value DO and gain calibration coefficient DG thus calculated at step S7 are stored into the respective registers 6 and 7. Once these calibration parameters have been determined in the above-mentioned manner, the offset calibration value DO and gain calibration coefficient DG stored in the registers 6 and 7 are used in the adder 2 and multiplier 3, respectively, so that each digital signal output subsequently from the A/D converter 1 is adjusted in accordance with the calibration parameters.

[0030] FIG. 4 is a block diagram showing an exemplary setup and behavior of a digital calibration apparatus of the present invention which performs digital adjustment or calibration on a D/A converter (DAC) 11. In the illustrated example of FIG. 4, the D/A converter 11 receives a digital signal and converts it into analog representation to thereby output analog signal An. Adder 12 adds together digital signal D5 supplied from a CPU 4 by way of a tester bus 15 and offset calibration value Do given from an offset register 16 and then supplies a multiplier 13 with digital signal D6 that is indicative of the added result. The multiplier 13 multiplies the digital signal D6 from the adder 12 by gain calibration coefficient Dg from a gain register 17 and supplies the D/A converter 11 with digital signal D7 that is indicative of the multiplication result. The analog signal An output from the D/A converter 11 may be supplied to a predetermined IC to be tested or the like.

[0031] The analog signal An output from the D/A converter 11 is delivered to an A/D converter 18 for conversion into digital signal D8, and the digital converted signal D8 is fed back to the CPU 4. This is for the purpose of calculating the offset calibration value Do and gain calibration coefficient Dg to be used for the D/A converter 11. The same algorithm as set forth above in relation to the A/D converter 1 of FIG. 1 can be used to calculate the offset calibration value Do and gain calibration coefficient Dg. First, the CPU 4 stores offset calibration value Do of “0” and gain calibration coefficient Dg of value “1” into the offset register 16 and gain register 17, respectively. Then, a positive full-scale digital signal voltage is given to the adder 12 as a first reference signal, and digital converted value D8+obtained by converting the analog signal An from the D/A converter 11 is passed to the CPU 4. Then, a negative full-scale digital signal voltage is given to the adder 12 as a second reference signal, and digital converted value D8-obtained by converting the analog signal An from the D/A converter 11 is passed to the CPU 4. Upon receipt of the digital values D8+ and D8− corresponding to the positive and negative full-scale voltages, the CPU calculates offset calibration value Do and gain calibration coefficient Dg and stores them into the offset register 16 and gain register 17, respectively. In this way, the D/A converter 11 will then output analog signal An conforming to the ideal D/A conversion characteristic.

[0032] For reference purposes, FIG. 5 shows an example of a calibrating program that is executed by the CPU 4 of FIG. 4 to carry out the above-mentioned arithmetic operations. At first step S11, the calibration parameters DO and DG are set to values “0” and “1”, respectively, and then stored into the respective registers 16 and 17. At next step S12, first reference digital signal Dr1 is output as signal D5 via the bus (T-BUS) 15. This first reference digital signal Dr1 corresponds to, for example, the negative full-scale value. Because Do=0 and Dg=1, the digital signal D5 (=Dr1) from the bus 15 is input to the D/A converter 11 as it is (i.e. without being changed). Analog converted signal output from the D/A converter 11 in response to the input of the first reference digital signal Dr1 is further converted by the A/D converter 18 into digital signal D8, which is passed to the CPU 14. The CPU 14 receives the digital signal D8 and stores it as first reference converted value V01. At following step S14, second reference digital signal Dr2 is output as signal D5 via the bus (T-BUS) 15. This second reference digital signal Dr2 corresponds to, for example, the positive full-scale value. Analog converted signal output from the D/A converter 11 in response to the input of the second reference digital signal Dr2 is further converted by the A/D converter 18 into digital signal D8, which is passed to the CPU 14. The CPU 14 receives the digital signal D8 and stores it as second reference converted value V02, at step S15.

[0033] At next step S16, the CPU 4 calculates offset calibration value Do and gain calibration coefficient Dg on the basis of the thus-stored reference converted values V01 and V02 and reference digital signals Dr1 and Dr2, using the following equations that are generally similar to the ones set forth above in relation to the program of FIG. 3:

[0034] Do=(V02+V01)/2

[0035] Dg=(Dr2−Dr1)/(V2−V01)

[0036] The thus-calculated offset calibration value Do and gain calibration coefficient Dg are stored into the offset register 16 and gain register 17, respectively, at step S17. Once these calibration parameters have been determined in the above-mentioned manner, the offset calibration value Do and gain calibration coefficient Dg stored in the registers 16 and 17 are used in the adder 12 and multiplier 13, respectively, so that each digital signal subsequently input to the D/A converter 11 is adjusted in accordance with the calibration parameters.

[0037] Whereas the preferred embodiments of the present invention have been described above in relation to the case where positive and negative full-scale reference signals are fed to the A/D and D/A converters in order to calculate calibration parameters, the present invention is not so limited, and voltages near such positive and negative full-scale reference signals or any other suitable voltages may of course be fed to the A/D and D/A converters for calculation of the calibration parameters. Further, although the positive and negative full-scale voltages have been described as being of a same absolute value “in a symmetrical relation to each other about the zero value”), they may of course be of different absolute values “non-“symmetrical”); in such a case, it is only necessary that the two full-scale voltages be subjected to arithmetic operations so as to have a same absolute value and the offset calibration value be calculated using the results of such arithmetic operations.

[0038] In summary, the digital calibration technique of the present invention affords the superior benefit that it can perform digital calibrate on a great number of A/D and D/A converters with increased accuracy at increased speed.