Buffer

[0002] The present invention is directed to a buffer, and more particularly, a buffer capable of transferring an input signal at high speed for the case of a high-to-low transition as well as a low-to-high transition.

[0003] Conventional digital buffers are commonly optimized for fast data transfer during either a high-to-low transition or a low-to-high transition, but not both. Accordingly, when a buffer is optimized for high-speed high-to-low transitions of an input signal, a low-to-high transition in the signal output will occur at a relatively low speed. The inverse is also true—when a buffer is optimized for high-speed low-to-high transitions of an input signal, a high-to-low output signal transition will occur at a relatively low speed.

[0004] FIG. 1 is a circuit diagram illustrating an embodiment of a conventional buffer, comprising an inverter I1 which includes a PMOS transistor P1 and an NMOS transistor SN1, and an inverter I2 which includes a PMOS transistor SP1 and an NMOS transistor N1. As shown in FIG. 1, SN1 and SP1 denote small-sized NMOS and PMOS transistors, respectively. The small-sized NMOS transistor SN1 and PMOS transistor SP1 are provided in order to increase the signal output buffering speed in the case of a high-to-low transition of an input signal IN.

[0005] FIG. 2 is a timing diagram illustrating an operation of the circuit shown in FIG. 1. The signal output transition time is relatively fast in the case where the input signal IN transitions from a high level to a low level at a high speed (see reference 92). On the contrary, the transition time is relatively slow in case where the input signal IN transitions from a low level to a high level (see reference 94).

[0006] FIG. 3 is a circuit diagram illustrating another embodiment of a conventional buffer, comprising an inverter I3 which includes a PMOS transistor SP2 and an NMOS transistor N2, and an inverter I4 which includes a PMOS transistor P2 and an NMOS transistor SN2. As shown in FIG. 3, SN2 and SP2 denote small-sized NMOS and PMOS transistors, respectively. The small-sized NMOS transistor SN2 and PMOS transistor SP2 are provided in order to increase the signal output buffering speed in the case of a low-to-high transition of an input signal IN.

[0007] FIG. 4 is a timing diagram explaining an operation of the circuit shown in FIG. 3. The signal output transition time is relatively fast in the case where the input signal IN transitions from a low level to a high level at a high speed (see reference 96). On the contrary, the transition time is relatively slow in case where the input signal IN transitions from a high level to a low level (see reference 98).

[0008] In this manner, the conventional buffer is capable of relatively fast signal propagation of the output signal OUT in either case of a low-to-high transition or a high-to-low transition of the input signal IN. However, the conventional buffer is not capable of efficient propagation of both low-to-high and high-to-low transitions of the input signal IN.

[0009] It is an object of the present invention to provide a buffer suitable for increasing speed in generation of a signal output for both cases of a high-to-low transition and a low-to-high transition of an input signal.

[0010] In one aspect, the present invention comprises a buffer, comprising a pull-down means for generating an output signal that transitions to a first state when an input signal transitions from a first state to a second state in response to a control signal of a first control state. A pull-up means generates the output signal that transitions to a second state when the input signal transitions from the second state to the first state in response to the control signal being of a second control state. A control signal generator generates the control signal in response to the state of the output signal.

[0011] In a preferred embodiment, the pull-down means comprises a first pull-up transistor having a source to which a power supply is applied, and a gate to which the control signal is applied. A second pull-up transistor has a source which is connected to a drain of the first pull-up transistor, a gate to which the input signal is applied, and a drain which generates the output signal. A first pull-down transistor includes a drain which is connected to the drain of the second pull-up transistor, and a gate to which the input signal is applied. A second pull-down transistor includes a drain which is connected to a source of the first pull-down transistor, a gate to which an inverted signal of the control signal is applied, and a source to which a ground voltage is applied, the second pull-up transistor being smaller than the first pull-up transistor and the first and second pull-down transistors.

[0012] In another preferred embodiment, wherein the pull-up means comprises a third pull-up transistor having a gate to which the inverted signal of the control signal is applied, and a source to which a power supply is applied. A fourth pull-up transistor includes a source which is connected to the drain of the third pull-up transistor, a gate to which the input signal is applied, and a drain in which the output signal is generated. A third pull-down transistor includes a source which is connected to the drain of the fourth pull-up transistor, and a gate to which the input signal is applied. A fourth pull-down transistor includes a drain which is connected to the source of the third pull-down transistor, a gate to which the control signal is applied, and a source to which a ground voltage is applied, the third pull-down transistor being smaller than the third and fourth pull-up transistors and the fourth pull-down transistor.

[0013] In another preferred embodiment, the pull-down means comprises a fifth pull-up transistor having a source to which a power supply is applied, and a gate to which the input signal is applied. A fifth pull-down transistor includes a drain which is connected to a drain of the fifth pull-up transistor, a gate to which the input signal is applied, and a source which is connected to a ground voltage. A first CMOS transfer gate transfers a signal output from the drain of the fifth pull-down transistor as the output signal in response to the control signal being in a first state, the fifth pull-up transistor being smaller than the fifth pull-down transistor.

[0014] In another preferred embodiment, the pull-up means comprises a sixth pull-up transistor having a source to which a power supply is applied, and a gate to which the input signal is applied. A sixth pull-down transistor includes a drain which is connected to a drain of the sixth pull-up transistor, a gate to which the input signal is applied, and a source which is connected to a ground voltage. A second CMOS transfer gate transfers a signal output from the drain of the sixth pull-up transistor as the output signal in response to the control signal being in a second control state, the sixth pull-down transistor being smaller than the sixth pull-up transistor.

[0015] The control signal generator preferably comprises a first inverter for inverting the output signal of the pull-up or pull-down means. A delay means generates the control signal by delaying an output signal of the first inverter for a predetermined time duration. A second inverter generates the inverted control signal by inverting an output signal of the delay means.

[0016] In another aspect, the present invention is directed to a buffer comprising a pull-down means for pulling down an input signal, and for generating an output signal in response to a control signal and an inverted signal of the control signal. A pull-up means pulls-up the input signal and generates the output signal in response to signals with an opposite phase of the control signal and the inverted signal of the control signal. A control signal generator generates the control signal and the inverted signal of the control signal in response to the output signal.

[0017] In another aspect, the present invention is directed to a buffer comprising a pull-down means for outputting a pull-down signal which, in response to an input signal undergoing a transition from a low state to a high state, generates an output signal that is pulled down from a high state to a low state, and, in response to an input signal undergoing a transition from a high state to a low state, generates an output signal that is pulled up from a low state to a high state, the pull-down of the output signal occurring at a faster rate than the pull-up of the output signal, the pull-down means being activated in response to a control signal being in a first control state. A pull-up means for outputs a pull-up signal which, in response to an input signal undergoing a transition from a low state to a high state, generates an output signal that is pulled down from a high state to a low state, and, in response to an input signal undergoing a transition from a high state to a low state, generates an output signal that is pulled up from a low state to a high state, the pull-up of the output signal occurring at a faster rate than the pull-down of the output signal, the pull-down means being activated in response to the control signal being in a second control state. A control signal generator generates the control signal as a function of the output signal.

[0018] The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.

[0019] FIG. 1 is a circuit diagram illustrating an embodiment of a conventional buffer.

[0020] FIG. 2 is a timing diagram illustrating operation of the conventional buffer circuit shown in FIG. 1.

[0021] FIG. 3 is a circuit diagram illustrating another embodiment of a conventional buffer.

[0022] FIG. 4 is a timing diagram explaining operation of the conventional buffer circuit shown in FIG. 3.

[0023] FIG. 5 is a block diagram illustrating an embodiment of a buffer according to the present invention.

[0024] FIG. 6 is a circuit diagram illustrating embodiments of the fast pull-up and fast pull-down circuits of the buffer FIG. 5, in accordance with the present invention.

[0025] FIG. 7 is a timing diagram explaining operation of the circuit shown in FIG. 6, in accordance with the present invention.

[0026] FIG. 8 is a block diagram illustrating another embodiment of a buffer according to the present invention.

[0027] FIG. 9 is a circuit diagram illustrating embodiments of the fast pull-up and fast pull-down circuits of the buffer shown in FIG. 8, in accordance with the present invention.

[0028] FIG. 10 is a timing diagram explaining operation of the circuit shown in FIG. 9, in accordance with the present invention.

[0029] FIG. 5 is a block diagram illustrating an embodiment of a buffer according to the present invention. The buffer comprises a fast pull-down means 100, a fast pull-up means 200, invertors 15 and 16 and a delay circuit 14. The fast pull-down means 100 includes a PMOS transistor P3, a fast pull-down circuit 10 and a NMOS transistor N3. The fast pull-up means 200 includes a PMOS transistor P4, a fast pull-up circuit 12 and a NMOS transistor N4.

[0030] Operation of the circuit of FIG. 5 will now be described. The PMOS transistor P3 is active low, that is, activated, or turned on, in response to a control signal C at a low level. The NMOS transistor N3 is active high, and is therefore turned on in response to an inverted control signal CB at a high level. The fast pull-down circuit 10 is enabled by activating the PMOS transistor P3 and the NMOS transistor N3 (in response to a control signal C at a LOW level) and rapidly pulls-down an intermediate signal A from a high level to a low level in response to an input signal IN that transitions from a low level to a high level. Similarly, PMOS transistor P4 is active low, and therefore is turned on in response to an inverted control signal CB at a low level. The NMOS transistor N4 is active high, and is turned on in response to a control signal C at a high level. The fast pull-up circuit 12 is enabled by activating the PMOS transistor P4 and the NMOS transistor N4 (in response to a control signal C at a HIGH level) and rapidly pulls-up the intermediate signal A from a low level to a high level in response to an input signal IN that transitions from a high level to a low level. Inverter 15 outputs an output signal OUT by inverting the intermediate signal A of the fast pull-down circuit 10 and the fast pull-up circuit 12. The delay circuit 14 produces the control signal C by delaying the output signal OUT for a predetermined length of time. The control signal C is applied to the gates of the PMOS transistor P3 and the NMOS transistor N4. Inverter 16 generates an inverted control signal CB by inverting the control signal C. The inverted control signal CB is applied to gates of the NMOS transistor N3 and the PMOS transistor P4.

[0031] Assuming the output signal OUT to be at a low level from a previous operation, the control signal C and the inverted control signal CB are at a low level and a high level, respectively. Accordingly, the PMOS transistor P3 and NMOS transistor N3, and therefore, the fast pull down circuit 10, are activated. In the embodiment shown, the fast pull-down circuit 10 rapidly pulls down intermediate signal A from a high level to a low level when the input signal IN transitions from a low level to a high level. It follows that if the output signal OUT is at a low level, a previous input signal IN is at a low level. Accordingly, the fast pull-down circuit 10 continues to generate the output signal A at a high level when input signal IN remains at a low level. As soon as the input signal IN transitions to a high level, the fast pull-down circuit 10 is in an active state, and is available to rapidly transition the intermediate signal A from a high level to a low level. During the aforementioned scenario, the fast pull-up circuit 12 is inactive and does not operate.

[0032] Assuming the output signal OUT to be at a high level from a previous operation, the control signal C and the inverted control signal CB are at a high level and a low level, respectively. Accordingly, the PMOS transistor P4 and NMOS transistor N4, and therefore, the fast pull up circuit 12, are activated. In the embodiment shown, the fast pull-up circuit 12 rapidly pulls up intermediate signal A from a low level to a high level when the input signal IN transitions from a high level to a low level. It follows that if the output signal OUT is at a high level, a previous input signal IN is at a high level. Accordingly, the fast pull-up circuit 12 continues to generate the output signal A at a low level when input signal IN remains at a high level. As soon as the input signal IN transitions to a low level, the fast pull-up circuit 12 is in an active state, and is available to rapidly transition the intermediate signal A from a low level to a high level. During the aforementioned scenario, the fast pull-down circuit 10 is inactive and does not operate.

[0033] In this manner, the circuit configuration of the buffer of the present invention provides for rapid data transition at its output, for both high-to-low and low-to-high input transitions.

[0034] FIG. 6 is a circuit diagram illustrating the embodiment of FIG. 5, wherein the fast pull-down circuit 10 comprises a PMOS transistor SP3 and a NMOS transistor N5, and the fast pull-up circuit 12 comprises a PMOS transistor P5 and a NMOS transistor SN3. Other components are identical with the configuration illustrated in FIG. 5. In FIG. 6, SN3 and SP3 denote the small-sized NMOS and PMOS transistors, respectively.

[0035] The fast pull-down circuit 10 shown in FIG. 6 includes a PMOS transistor SP3 of a small size with respect to the sizes of the PMOS transistor P3 and the NMOS transistors N3 and N5 in order to increase the high-to-low transition speed of the signal output A in the case of a low-to-high transition of the input signal IN. The fast pull-up circuit 12 includes an NMOS transistor N4 of a small size relative to the sizes of the PMOS transistors P4 and P5 and the NMOS transistor N4 in order to increase the low-to-high transition speed of the intermediate signal A in the case of a high-to-low transition of the input signal IN.

[0036] Accordingly, the intermediate signal A transition speed in the case of both a high-to-low transition and a low-to-high transition of the input signal IN is relatively fast, since the buffer includes both the fast pull-down circuit 10 and the fast pull-up circuit 12 as shown in FIG. 6.

[0037] FIG. 7 is a timing diagram explaining the operation of the circuit illustrated in FIG. 6. When the output signal OUT is previously at a low level, the delay circuit 14 receives and delays the output signal OUT for a predetermined time period, and generates the control signal C. The inverter 16 inverts the control signal C and generates an inverted control signal CB at a high level. Accordingly, the PMOS transistor P3 and the NMOS transistor N3 are activated, and their counterpart transistors P4, N4 in the pull-up circuit are deactivated. While the input signal IN is at a low level, the PMOS transistor SP3 is turned on so that the fast pull-down circuit 10 maintains the intermediate signal A at a high level. When the input signal IN transitions to a high level, the NMOS transistor N5 is turned on, and the fast pull-down circuit 10 generates an intermediate signal A which rapidly transitions to a low level at a relatively high speed, and remains low over the time interval of T1.

[0038] Similarly, while the output signal OUT is at a high level over the time interval T1, the delay circuit 14 receives and delays the output signal OUT for a predetermined time period, and generates the control signal C at a high level. The inverter 16 inverts the control signal C and generates an inverted control signal CB at a low level. Accordingly, the PMOS transistor P4 and the NMOS transistor N4 are activated, and their counterpart transistors P3, N3 in the fast pull-down circuit 100 are deactivated. While the input signal IN is at a high level, the NMOS transistor SN3 is turned on so that the fast pull-up circuit 10 maintains the intermediate signal A at a low level. When the input signal IN transitions to a low level, the PMOS transistor P5 is turned on, and the fast pull-up circuit 10 generates an intermediate signal A which rapidly transitions to a high level at a relatively high speed, and remains high over the time interval of T2.

[0039] FIG. 8 is a block diagram illustrating another embodiment of a buffer according to the present invention, comprising a fast pull-down means 110, a fast pull-up means 210, invertors 15 and 16, and a delay circuit 14. The fast pull-down means 110 includes a fast pull-down circuit 20 and a CMOS transmission gate T1. The fast pull-up means includes a fast pull-up circuit 22 and a CMOS transmission gate T2.

[0040] Operation of the circuit illustrated in FIG. 8 will now be described. When the output signal OUT is at a low level, the control signal C and the inverted control signal CB are at a low level and a high level, respectively. Accordingly, the CMOS transmission gate T1 is turned on. The fast pull-down circuit 20 generates an intermediate signal A by transferring a pull-down signal PD through the CMOS transmission gate T1. When the output signal OUT is at a low level, the input signal IN is likewise at a low level. Accordingly, the fast pull-down circuit 20 maintains the pull-down signal PD at a high level while the input signal IN is low. When the input signal IN transitions to a high level, the fast pull-down circuit 20 responds by generating a pull-down signal PD that rapidly transitions to a low level. The CMOS gate T1 passes this low-level pulled-down signal to provide intermediate signal A. The corresponding pull-up signal PU of the fast pull-up circuit 22 is not transmitted since the corresponding CMOS transmission gate T2 is turned off.

[0041] While the output signal OUT is at a high level, the inverted control signal CB and the control signal C transition to a low level and a high level, respectively. Accordingly, the CMOS transmission gate T2 is turned on (and T1 is turned off). The fast pull-up circuit 22 generates an intermediate signal A by transferring a pull-up signal PU through the CMOS transmission gate T2. When the output signal OUT is at a high level, the input signal IN is likewise at a high level. Accordingly, the fast pull-up circuit 22 maintains the pull-up signal PU at a low level while the input signal IN is high. When the input signal IN transitions to a low level, the fast pull-up circuit 22 responds by generating a pull-up signal PU that rapidly transitions to a high level. The CMOS gate T2 passes this high-level pulled-up signal to provide intermediate signal A. The corresponding pull-down signal PD of the fast pull-down circuit 20 is not transmitted since the corresponding CMOS transmission gate T1 is turned off.

[0042] FIG. 9 is a circuit diagram illustrating the embodiments shown in FIG. 8, wherein the fast pull-down circuit 20 includes a PMOS transistor SP4 and an NMOS transistor N6, and the fast pull-up circuit 22 includes a PMOS transistor P6 and an NMOS transistor SN4. Other components are identical with those shown in the configuration shown in FIG. 8.

[0043] In FIG. 9, SP4 and SN4 denote relatively small-sized PMOS and NMOS transistors, respectively, as compared to the sizes of transistors N6 and P6. That is, the fast pull-down circuit 20 includes the PMOS transistor SP4 of a small size relative to the NMOS transistor N6 in order to increase the signal output transition speed in the case of a low-to-high transition of the input signal IN. The fast pull-up circuit 22 includes the NMOS transistor SN4 of a small size relative to the PMOS transistor P6 in order to increase the signal output transition speed in the case of a high-to-low transition of the input signal IN. Accordingly, the signal output transition speed for both high-to-low transitions and a low-to-high transitions of the input signal IN can be relatively fast since the buffer includes both the fast pull-down circuit 20 and the fast pull-up circuit 22. That is, the pull-up signal PU of the fast pull-up circuit 22 is provided as the intermediate signal A when the output signal OUT is at a high level, and the pull-down signal PD of the fast pull-down circuit 20 is output as the intermediate signal A when the output signal OUT is at a low level.

[0044] FIG. 10 is a timing diagram for illustrating operation of the circuit shown in FIG. 9. When the output signal OUT is at a low level, the delay circuit 14 generates a control signal C at a low level after delaying the output signal OUT for a predetermined time period. The inverter 16 generates an inverted control signal CB at a high level. Accordingly, the CMOS transfer gate T1 is turned on. The fast pull-down circuit 20 generates a pull-down signal PD at a high level while the input signal IN is at a low level. When the input signal IN transitions to a high level, the NMOS transistor N6 is turned on so that the fast pull-down-circuit 20 generates a pull-down signal PD that transitions to a low level at a high speed. At the same time, the NMOS transistor SN4 is turned on so that the fast pull-up circuit 22 generates the pull-up signal PU that transitions to a low level at a relatively low speed. However, since the CMOS transfer gate T1 is turned on, and its counterpart gate T2 is turned off, only the pull-down signal PD of the fast pull-down circuit 20 is transferred as intermediate signal A. Therefore, the pull-down circuit 20 generates an intermediate signal A that transitions to a low level at a high speed, during the end of time interval T2.

[0045] When the output signal OUT is at a high level, the delay circuit 14 generates a control signal C at a high level after delaying the output signal OUT for a predetermined time period. The inverter 16 generates an inverted control signal CB at a low level. Accordingly, the CMOS transfer gate T2 is turned on. The fast pull-up circuit 22 generates a pull-up signal PU at a low level while the input signal IN is at a high level. When the input signal IN transitions to a low level, the PMOS transistor P6 is turned on so that the fast pull-up circuit 22 generates a pull-up signal PU that transitions to a high level at a high speed. At the same time, the PMOS transistor SP4 is turned on so that the fast pull-down circuit 20 generates a pull-down signal PD that transitions to a high level at a relatively low speed. However, since the CMOS transfer gate T2 is turned on, and its counterpart gate T1 is turned off, only the pull-up signal PU of the fast pull-up circuit 22 is transferred as intermediate signal A. Therefore, the pull-up circuit 22 generates the intermediate signal A that transitions to a high level at a high speed, during the end of time interval T1.

[0046] The buffer according to the present invention can transfer an input signal at a high speed in the case of a high-to-low transition of the input signal as well as a low-to-high transition of the input signal. Accordingly, a semiconductor memory device can be operated at a high speed by adopting the buffer according to the present invention.

[0047] While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made herein without departing from the spirit and scope of the invention as defined by the appended claims.