CCD image sensor

[0002] This invention relates to a charge-coupled device (COD) image sensor with a vertical-overflow drain (VOD) for antiblooming protection, and more particularly, to low voltage electronic shuttering of solid-state CCD image sensors.

[0003] Prior art structures for improving the electronic shuttering characteristics of image sensors provide confined regions of higher doping concentration directly beneath the individual detector elements of an interline (IL) CCD imager as shown in FIG. 4. This reduces the depletion spreading into the substrate thereby increasing capacitive coupling from the substrate to the so-called overflow point. This increased capacitive coupling allows the overflow barrier (potential difference between the storage region of the photodetector and the overflow point) to be pulled down more easily, i.e., with less voltage on the substrate.

[0004] However, processing is made difficult in the prior art by the fact that these regions are confined to the area directly under each individual detector. Implanting these n+ regions relatively late in the process (e.g., around the same time the photodiodes are formed) would require extremely high energy or a reduced p-well depth. A reduced p-well depth would reduce photosensitivity at longer wavelengths, and is therefore undesirable. The currently available high-energy implantation equipment is not capable of providing energies high enough for this approach. Another problem with high-energy implantation is maintaining purity of the beam which makes process control difficult. Implanting these regions early in the process and driving them also would be difficult since registration of various layers would be poor (i.e., self alignment would not be possible).

[0005] Prior art CCD image sensors of the type shown in FIG. 3, but not for type shown in FIG. 4, however, typically require relatively large substrate voltages (around 40 volts) to affect electronic shutter action.

[0006] The prior art sensor shown in FIG. 9 is illustrated similar as in U.S. Pat. No. 5,014,132.

[0007] This prior art device has improved voltage characteristics for electronic shutter operation which results from heavily doping the substrate 91 as compared to n-type layer 92. P-well 93 is provided within which imaging layers are created. However, the device in FIG. 9 does not result in desirable internal gettering characteristics because oxygen precipitation is more difficult to induce when the n-type dopant concentration is increased.

[0008] It can be seen from the foregoing discussion that their remains a need within the art for a device having improved low voltage characteristics for the electronic shutter that is built on a substrate that is easy to getter internally.

[0009] We have invented a structure that provides a reduction in the voltage required to operate electronic shutters while maintaining sufficiently easy gettering within the sensor. The resulting performance eases the demands on off-chip support circuitry required to operate this sensor. The present invention provides an improved pixel structure that allows for a reduction in this voltage required to operate the electronic shutter. The improved structure is provided with a simplified manufacturing process compared to conventional processes used by other CCD manufacturers. The invention improves upon the prior art, to alleviate the previously discussed difficulties, by providing between an n-type substrate and a p-type well, a uniform, deep n+ layer underneath the entire area of the device as shown in FIG. 2. Although this layer could be implanted early in the process, we have found it more convenient and easier to control by creating the deep n+layer via epitaxial growth. Additionally, the invention provides another n-type layer above the n+ layer.

[0010] It is also envisioned, that variations in the doping levels within the layer structures can be employed to achieve low voltage operation while maintaining internal gettering characteristics. This is provided by an image sensor structure that has a substrate of n-type conductivity, a first laterally uniform, deep n-layer on top of the substrate and underneath the entire area of the image sensor and a second laterally uniform n-layer on top the first laterally uniform n-layer that extends to the top surface of the device, and a laterally uniform, lightly doped p-layer formed in the second laterally uniform n-layer, such that the p-layer is located beneath image sensor and above the n-substrate and the first deep n-layer.

[0011] The above and other objects of the present invention will become more apparent when taken in conjunction with the following description and drawings wherein identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.

[0012] The present invention has advantages over the prior art providing low voltage shuttering while retaining a simple fabrication process.

[0013] FIG. 1 is a top view of an interline CCD image sensor;

[0014] FIG. 2 is a cross section of a pixel illustrating the present invention;

[0015] FIG. 3 is a view of a prior art CCD sensor without improved voltage characteristics for electronic shutter operation;

[0016] FIG. 4 is a view of a prior art CCD sensor with an n+ region formed directly underneath the photodetectors;

[0017] FIG. 5 shows the photodiode's doping profile of the invention of FIG. 2;

[0018] FIG. 6 shows the photodiode's doping profile of the prior art device of FIG. 3;

[0019] FIG. 7 shows the photodiode's barrier to overflow versus substrate voltage for FIG. 2 and prior art FIG. 3;

[0020] FIG. 8 shows the VCCD's potential profile versus depth for FIG. 2;

[0021] FIG. 9 shows another prior art device having uniform layers but with heavily doped substrate.

[0022] We have discovered that low voltage electronic shuttering can be provided for an image sensor while maintaining internal gettering characteristics. The preferred method of practicing the invention is by incorporating the elements into an interline device. While an interline device is preferred, use of the present invention within frame transfer devices is also envisioned. FIG. 1 schematically shows the general organization of an interline area image sensor having an array of photodiode sensor elements. Several of the sensor elements 17 which are shown in FIG. 1 are identified as A, B, C, D, E, F, G, H and I. The elements are arranged in columns and rows. Photocharge is integrated in each photodiode and, at a predetermined time, appropriate bias voltage pulse signals are applied to the transfer gate electrodes causing the charge to transfer from the photodiode to a vertical CCD shift register 25.

[0023] Referring now to FIG. 2, which is a cross section of the interline sensor 10 shown in FIG. 1 taken along the line A—A, the preferred embodiment of the present invention illustrates the improved structure that provides low voltage electronic shuttering while maintaining gettering characteristics. Additionally, the pinned photodiode of sensor 10 eliminates image lag while the npn structure of the photodiode provides blooming protection through a vertical overflow drain. A substrate 12 with a top surface 1 and bottom surface 2, is fabricated to have an array of photodiodes, a plurality of vertical CCDs for transferring charge in said image sensor, including a plurality of transfer gate electrodes, each transfer gate electrode 32 being formed over an area of the substrate top surface 1 corresponding to a particular photodiode and extending over a substrate transfer region positioned adjacent to a corresponding photodiode and responsive to a voltage signal for transferring charge from its corresponding photodiode to its particular CCD cell.

[0024] The substrate 12 is created from n-type material. Above the n-substrate 12 is a laterally uniform, highly doped n-+layer 14, that can be created either as an epitaxial layer or as an implant. Above the layer 14 is a more lightly doped n-type layer 16, that is also laterally uniform and again can be created as either an epitaxial layer or as an implant. On top of layer 14, light p-well 18 is formed in a laterally uniform manner, such that it forms a p-n junction spaced from the top surface 1 of the substrate 12 by a predetermined amount.

[0025] This structure provides a vertical antiblooming overflow drain having a local potential minima which is confined to be deep in the uniform p-well to maintain high quantum efficiency, and reduces the voltage demands of off-chip circuitry required to operate the image sensor by virtue of layer 14.

[0026] The photodiode 21 and pinning layer 24 as well the elements required to create a charge-transfer device are then placed within p-well 18 as explained below. A laterally uniform, lightly doped n-well 22 is formed near the top 1 of the substrate 12 on top of the uniform p-well 18. A plurality of localized n-layers 23 is formed in the n-well 22 in an array corresponding to the array of the photodiodes 21 and a separate localized p-layer formed at the surface of each n-layer to create a pinning layer 24 to form a pinning photodiode for collecting photocharge and eliminating image lag. The pinning layer 24 being connected to a predetermined potential via the channel stop 33.

[0027] A plurality of p-stripes formed in the uniform lightly doped n-well 22 to form a heavily doped p well 28 that it is adjacent the photodiodes 21 and having a portion formed under each area to be the CCD and a thermally diffused portion providing sufficient doping beneath a transfer gate electrode, but not extending to an adjacent photodiode 21 to enable charge collected in the photodiode 21 to be transferred to its CCD leaving the photodiode 21 completely depleted when the desired voltage level is applied to the transfer gate electrode 32.

[0028] One p-stripe for each CCD is formed under the polysilicon gate electrode 32. It extends upward to the gate oxide, and extends laterally toward the corresponding photodiode 21. The heavy p-well becomes the body for construction of the CCD shift registers. The buried-channel CCD region 26 is an n-type region constructed within the heavy p-well 28, and the CCD gate electrode 32 is clocked with voltages with reference to the heavy p-well 28.

[0029] The substrate 12 can be heated to thermally drive both wells 28 and 22 into substrate 12 or alternatively suitable implants can be used. As a result of the careful choice of implant parameters and thermal processing, the narrow, laterally uniform, lightly doped p-well 18 is provided typically with a junction depth several micrometers below the substrate top surface 1. Thereafter, p- and n-layers (respectively 24 and 23) are formed in n-well 22 for a fully depletable photodiode. The above arrangement provides pinned photodiode with a vertical-overflow drain structure. A thermal oxide 34 is formed on the top surface 1 of substrate 12. However, some other insulating layers may be used instead as would be understood by those skilled in the art. The pinned photodiode has two p-n junctions, one formed by the uniform layer that is the n-well 22 with uniform p-layer that is p-well 18, and the second formed by localized n-layer that forms photodiode 21 with the localized layer that forms the p-type pinning layer 24. In response to light, charge is collected in the cathode of the photodiode.

[0030] The photodiode isolation in the vertical direction is accomplished by appropriate channel stops 30 comprised of a thick oxide 31 with p-type implant 33 beneath. Other isolation technology could also be used. Such isolation is part of the standard CCD process. The p-layers 24 and 33 are physically contiguous and are electrically connected to ground potential.

[0031] Preferably, the n-type substrate 12 is provided with a doping level on the order of 10¹⁴cm⁻³with a first epitaxial layer 14 having a doping level on the order of 10¹⁶cm⁻³, a second epitaxial layer having a doping level on the order of 10¹⁴cm⁻³, and a p-well having a doping level on the order of 10¹⁵cm⁻³. This preferred configuration, or the like, has been found to be effective in maintaining a simple process for internal gettering. Also, whereas the first and second epitaxial layers (14 and 16, respectively) are uniform underneath the entire area of sensor 10, it should be noted that the present invention can be practiced using wells in place of the double epitaxial layers shown in FIG. 2.

[0032] FIG. 3 shows prior art CCD image sensor 50. Sensor 50 comprises n-type substrate 62 having a uniform n-type epi layer 64. Substrate 62 defines top and bottom surfaces 41 and 42, respectively. Uniform lightly doped p-well 68 is then implanted into the top portion 41 of the n-epi 64. The remaining portions of device 50 are similar to those shown in FIG. 2. The structure of the type shown in FIG. 3 will typically have an n-type substrate doped to around 10¹⁴cm⁻³. The epitaxial layer 64 is typically provided with n-type doping material at around 10¹⁴cm⁻³. This structure, while providing a vertical overflow drain function, lacks the desirable low voltage electronic shutter operation achieved by the structure of the present invention as illustrated in FIG. 2.

[0033] FIG. 4 shows another prior art interline CCD image sensor 70 that is similar to the prior art with an additional n-region 72 which is a region of higher doping concentration (relative to the n-type epi layer 64) directly beneath individual photodiodes 21 of sensor 70. This structure allows the overflow barrier to be pulled down more easily with less voltage on the substrate. However, manufacturing the structure requires a difficult process in that each n-region 72 is confined only directly below each individual detector. This would typically require high energy implantation or reduced p-well depth. The present invention provides a uniform layer that can be implanted early in the process or via epitaxial growth.

[0034] FIGS. 5 and 6 show the doping profiles (down the center of the photodiode) and FIG. 7 shows the barrier-to-overflow versus substrate voltage for the two structures, indicated as 130 and 131 for FIGS. 2 and 3, respectively. The barrier-to-overflow is defined as the maximum potential in the n-region 23 of the diode (FIG. 2) minus the minimum potential in the light p-well region 18. In FIG. 5 the concentration of the pinning layer is indicated as 124, that of the n photodiode region is 123, of the p-well as 118 as the n type epi layer as 114. The magnitude of the barrier-to-overflow is related to the photodiode's charge capacity, which drops as the barrierto-to-overflow approaches a few multiples of kT/q, where k is Boltzmann's constant, T is the absolute temperature and q is the charge of an electron. Therefore, for a low voltage shutter, it is desirable to have this parameter approach zero at a low shutter voltage, yet have it be large enough at lower substrate voltage levels to maintain adequate charge capacity, i.e., a curve with a steep slope is desirable. All the charge in the photodiode will be lost to the substrate as this barrier approaches a few kT/q. Note that the new structure of the present invention reduces the substrate voltage required for shuttering (complete reset) by about a factor of 2. This can be seen by comparing the prior art p-well 68 concentration, indicated as 168, and n-region concentration indicated as 164, with those of FIG. 5. Here, the shape of the curves in FIG. 7 depends on the doping profiles of the photodetector. However, for a given doping profile for the device structure shown in FIG. 2, increasing the doping concentration of the n+ first epitaxial layer 14 will increase the slope of the barrier versus substrate voltage curve, and making this layer deeper, will move the curve to the right. This preferred doping level is shown as 114 in FIG. 5. Therefore, choosing the appropriate n+ first epitaxial layer 14 doping, thickness and depth can easily be tailored for a given, existing process using readily available computer-aided design software.

[0035] An important concern with this new structure is that an adequate barrier be maintained between the CCD and substrate so that charge is not inadvertently lost from the CCD shift registers during the shutter pulse. FIG. 8 shows the potential profile versus well filling down through the center of the CCD shift register at a substrate bias of Vsub=20V for the new structure. FIG. 8 shows that an adequate charge capacity is maintained in the CCD and that charge is not lost to the substrate under these conditions since the barrier to the substrate, ØB indicated as 182, is over 4V at full well. This follows from the expression for current into the substrate as given by the expression (I=I_oe^−ØB/nkT); where n is the non-ideality factor. The advantage of this structure over the prior art is that a reduced electronic shutter voltage can be obtained with a simple process. The difficulties encountered in the prior art device of FIG. 4, associated with feature registration (i.e., alignment of the deep n+ region) and high energy implantation are avoided.

[0036] While the best mode known to the inventors for carrying out the invention has been described above, various options are envisioned by the inventors as other preferred embodiments. Among these options is the preferred embodiment of growing a heavily doped epitaxial layer on top the substrate and then changing to a more lightly doped epitaxial layer. An alternative, is to grow a lightly doped epitaxial layer, stop the growth and create an implant, then continue the growth of the lightly doped epitaxial layer, or before implant create a diffusion and then continue the growth. Still another alternative, is to grow the epitaxial layer, and create a sufficiently high energy implant to produce a buried N+ layer.

[0037] The invention has been described with reference to a preferred embodiment. However, it will be appreciated that variations and modifications can be effected by a person of ordinary skill in the art without departing from the scope of the invention.

[0038] Parts list:

[0039] 1 Top surface of the silicon substrate

[0040] 2 Bottom surface of silicon substrate

[0041] 10 Image sensor of the present invention

[0042] 12 n-type substrate

[0043] 14 n⁺ epitaxial layer

[0044] 16 n⁻ epitaxial layer

[0045] 17 Sensor elements of FIG. 1

[0046] 18 P-well

[0047] 21 n-type photodiode

[0048] 22 light n-well

[0049] 23 localized n-layers

[0050] 24 p-type Pinning layer

[0051] 25 Vertical CCD (VCCD) of FIG. 1

[0052] 26 n-type Buried channel

[0053] 27 Horizontal CCD (HCCD) of FIG. 1

[0054] 28 Heavy p-well

[0055] 30 Channel stops

[0056] 31 Thick oxide

[0057] 32 Gate electrode

[0058] 33 p+ channel stop implant

[0059] 34 Oxide

[0060] 41 Top of device of FIG. 3

[0061] 42 Bottom of device of FIG. 3

[0062] 50 Device of FIG. 3

[0063] 62 Substrate for FIG. 3 and 4.

[0064] 64 N type epitaxial layer of FIG. 3 and 4

[0065] 68 P well of FIG. 3

[0066] 70 Device of FIG. 4

[0067] 72 n+ layer of FIG. 4

[0068] 90 Device illustrated in FIG. 9

[0069] 91 n++ substrate of device of FIG. 9

[0070] 92 n layer of device of FIG. 9

[0071] 93 p-well of device of FIG. 9

[0072] 114 doping profile of n-type layer of FIG. 5

[0073] 118 doping profile of p-well of FIG. 5

[0074] 123 doping profile of photodiode region of FIG. 5.

[0075] 124 doping profile of pinning layer of FIG. 5.

[0076] 130 doping profile of center of photodiode of FIG. 2.

[0077] 131 doping profile of center of photodiode of FIG. 3.

[0078] 168 prior art p-well concentration

[0079] 182 substrate barrier in FIG. 8