Method of fabricating dual damascene structure using a hard mask

[0002] This application claims priority benefit of Taiwan application Serial no. 87100935, filed Jan. 23, 1998, the full disclosure of which is incorporated herein by reference.

[0003] 1. Field of the Invention

[0004] The invention relates to a method of fabricating dual damascene structure, and more particularly to a method of fabricating dual damascene structure which can improve the reliability of devices.

[0005] 2. Description of the Related Art

[0006] FIGS. 1A-1D is a cross sectional view of the conventional method of fabricating dual damascene structure. Referring to FIG. 1A, a substrate 100 having devices (not shown) is provided, and a defined conductive layer 102, is formed on the substrate 100. An oxide layer 104 and a silicon nitride layer 106 are deposited respectively on the substrate 100. Referring to FIG. 1B, the silicon nitride layer 106 is patterned by photolithography and an opening is then formed. An insulating layer 108 is formed on the substrate 100. The pattern of photoresist 110 anisotropically is used to define the insulating layer 108 by dry etching. When the insulating layer 108 is etched, using the silicon nitride layer 106aas a masking layer, and the oxide layer 104 which isn't covered by the silicon nitride layer 106ais etched until the conductive layer 102 is exposed. A trench 112, as shown in FIG. 1C, is then formed within the insulating layer 108aand the oxide layer 104a.A metal layer 114 is formed on the insulating layer 108aand the trench 112 is filled with the metal layer 114. The metal layer 114 is then planarized by chemical mechanical polishing (CMP) so a structure of the trench 114 filled up with metal layer 114 as shown in FIG. 1D is formed.

[0007] In the prior art as described above, the silicon nitride layer 106 is used to form on the oxide layer 104. The silicon nitride layer 106 is used as not only a barrier layer but also a masking layer for etching. Because the material characteristics of the silicon nitride layer 106, electrons can be easily trapped at the interface of the silicon nitride layer 106 and the oxide layer 104, and a semi-conduction layer is formed at the interface. When voltage is applied on the wiring lines, the semi-conduction layer induces crosstalk or short circuit and the reliability of devices decreases.

[0008] It is therefore an object of the invention to provide a method of fabricating dual damascene structure without the formation of the silicon nitride layer. The occurrence of leakage current, crosstalk or short circuit between metal layers can be prevented. The device reliability can be improved and the process can be simplified.

[0009] To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method of fabricating dual damascene structure. A substrate having devices and a defined conductive layer is provided. A dielectric layer and a hard mask material layer are formed respectively over the substrate. An opening is defined within the hard mask material layer. Because of the different selectivity of the hard mask material layer and the dielectric layer, a trench is formed within the dielectric layer by defining the hard material mask layer and a portion of dielectric layer until the conductive layer is exposed. The cross shape of the trench has a wider opening and a narrower bottom. A metal layer is then formed and the trench is filled up with the metal layer. The process of dual damascene structure is accomplished.

[0010] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

[0011] FIGS. 1A-1D is a cross sectional view of the conventional method of fabricating dual damascene structure.

[0012] FIGS. 2A-2D schematically illustrate processing steps in the formation of dual damascene structure in accordance with preferred embodiments of the present invention.

[0013] FIGS. 2A-2D schematically illustrate processing steps in the formation of dual damascene structure in accordance with preferred embodiments of the present invention.

[0014] Referring to FIG. 2A, a substrate 200 is provided and devices (not shown) such as a MOS transistor are formed thereon. A defined conductive layer 202 such as a metal layer or a polysilicon layer is formed on the substrate 200. A first dielectric layer 204, a second dielectric layer 206 and a hard mask material layer 208 are formed successively on the substrate 200 by chemical vapor deposition (CVD) or sputtering. The first dielectric layer 204 and the second dielectric layer 206 include oxide or other low k dielectric material. The material characteristic of hard mask material layer 208 is different from that of the oxide as used in the dielectric layers 204, 206. The hard mask material 208 includes titanium, titanium nitride, polysilicon or other metals and to a thickness in a range about 100 to 2000 Å. In addition, the first dielectric layer 204 and the second dielectric layer 206 can be used instead of a thicker dielectric layer and the thickness of the thicker dielectric layer corresponds to the first dielectric layer and the second dielectric layer.

[0015] Referring to FIG. 2B, the contact or via pattern is defined by photoresist 210 on the hard mask material layer 208a.By using anisotropic dry etching, a portion of hard mask material layer 208ais removed and a contact or via opening 212 is formed within the hard mask material layer 208a.The opening 212 is over the conductive layer 202 and the second dielectric layer 206ais exposed when the opening 212 is formed. A portion of the second dielectric layer 206ais usually etched to make sure the hard mask material layer 208ais removed completely.

[0016] If a thicker dielectric layer is used instead of the first dielectric layer 204 and the second dielectric layer 206, it is still necessary to etch a portion of the thicker dielectric layer as the opening is formed.

[0017] The metal pattern is then defined by photolithography with photoresist 214 on the hard mask material layer 208b.A high selectivity and anisotropic dielectric etch is performed to etch the second dielectric layer 206band partial first dielectric layer 204awith hard mask material 208bas the mask. A low selectivity (to hard mask material) and anisotropic dielectric etch is then followed to clear hard mask material 208band the second dielectric layer 206bwith photoresist 214 as the mask, as shown in FIG. 2C. Along the opening 216, a trench 216 is formed within the second dielectric layer 206band the first dielectric layer 204aand the conductive layer 202 is exposed while defining the hard mask material layer 208band the second dielectric layer 206b.Because of the different selectivity of hard mask material layer 208band the second dielectric layer 206b,the first dielectric layer 204ais not overetched when the second dielectric layer 206bis etched by anisotropic etching process. Therefore, the cross shape of the trench has a wider opening and a narrower bottom. The photoresist 214 is then removed.

[0018] A thicker dielectric layer can be used instead of the first dielectric layer 204 and the second dielectric layer 206. Because of the selectivity of the hard mask material layer 208band the thicker dielectric layer, the thicker dielectric layer is not etched through thoroughly as the thicker dielectric layer is defined. A trench is formed with the dielectric layer and the conductive layer 202 is exposed. The cross shape of the trench has a wider opening and a narrower bottom.

[0019] Referring to FIG. to 2D, the trench is filled up with a metal layer 218, which is formed on the hard mask material layer 208aby sputtering. The excess metal layer 218 and the hard mask material layer 208bare removed from the surface of the second dielectric layer 206bby chemical mechanical polishing and the second dielectric layer 206bis exposed. The metal layer 218 is therefore planarized.

[0020] This invention is directed towards provision of a hard mask material on the dielectric layer. Because of the different selectivity of the hard mask material layer and the dielectric layer, the dual damascene structure can be accomplished without a silicon nitride layer. Therefore, short circuit in the conductive layer can be prevented and the device reliability can be enhanced.

[0021] Other embodiment of the invention will appear to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples to be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.