Method for reducing PN junction leakage

[0002] This application is a divisional application of U.S. patent application Ser. No. 09/028,472 now U.S. Pat. No. 6,137,142, entitled “MOS Device Structure and Method for Reducing PN Junction Leakage” of James B. Burr, filed on Feb. 24, 1998, and which is incorporated herein by reference in its entirety.

[0003] 1. Field of the Invention

[0004] The present invention generally relates to semiconductor devices, and in particular, the present invention relates device structures and methods which reduce junction leakage particularly in lightly doped devices. Although not limited thereto, the invention is especially applicable to low-voltage CMOS (LVCMOS), or ultra-low power CMOS (ULP), implementations, as well as to SOI (silicon-on-insulator) buried well configurations.

[0005] 2. Description of the Related Art

[0006] There are a number of factors which contribute to the magnitude of a transistor device's threshold voltage. For example, to set a device's threshold voltage near zero, light doping and/or counter doping in the channel region of the device may be provided. However, due to processing variations, the exact dopant concentration in the channel region can vary slightly from device to device. Although these variations may be slight, they can shift a device's threshold voltage by a few tens or even hundreds of millivolts. Further, dimensional variations (such as channel width and especially channel length), charge trapping in the materials and interfaces, and environmental factors such as operating temperature fluctuations can shift the threshold voltage. Still further, low threshold devices may leak too much when their circuits are in a sleep or standby mode. Thus, particularly for low-threshold devices, it is desirable to provide a mechanism for tuning the threshold voltage to account for these and other variations. This can be accomplished using back biasing, i.e. controlling the potential between a device's well and source. See James B. Burr, “Stanford Ultra Low Power CMOS,” Symposium Record, Hot Chips V, pp. 7.4.1-7.4.12, Stanford, Calif. 1993, which is incorporated herein by reference for all purposes.

[0007] A basic characteristic of back-biased transistors resides in the ability to electrically tune the transistor thresholds. This is achieved by reverse biasing the bulk of each MOS transistor relative to the source to adjust the threshold potentials. Typically, the potential will be controlled through isolated ohmic contacts to the source and well regions together with circuitry necessary for independently controlling the potential of these two regions.

[0008] However, in any semiconductor structure having biased and abutting n and p regions, diode leakage through the pn junction is possible. Junction leakage is a function of junction bias and junction doping. The greater the junction bias, the wider the depletion region, and thus the greater the leakage. The amount of leakage also increases for lightly doped junctions which are accompanied by wide depletion regions. Conversely, leakage decreases for more heavily doped junctions having relatively narrow depletion regions. Also, while a larger depletion region is accompanied by a larger leakage, the capacitance of the junction is lower.

[0009] The problems associated with leakage current can be particularly acute for low-threshold voltage devices having intrinsic or nearly intrinsic channels. As mentioned above, such devices are characterized by the provision of as little dopant as possible to achieve high mobility in the channel region. This is accomplished by the use of near-intrinsic silicon on the substrate side of the source/drain junctions.

[0010] FIG. 1(a) illustrates an example of a back-biased n-well configuration. That is, in the exemplary CMOS configuration of FIG. 1(a), each of an NFET 101 and a PFET 102 essentially constitutes a four-terminal device. The NFET 101 is made up of an n-region source 103, a gate electrode 104, an n-region drain 105, and a p⁻bulk substrate 106. The NFET 101 may also include a p-well 107 as shown. Similarly, the PFET 102 includes p-region source 108, a gate electrode 109 and a p-region drain 10 formed in an n-well 111. Reference numeral 112 is a p⁺plug which forms a bulk terminal or well tie for the bulk material 106, and reference numeral 113 is an n⁺plug forming a well tie for the n-well 111.

[0011] In the back-biased CMOS design of FIG. 1(a), the well contact 112 of the bulk material 106 is split off from the source terminal 103 of the NFET 101 by providing a separate metallic rail contact 116 which is spaced from the metallic rail contact 114 of the source terminal 103. Rail contact 116 is connected to a bias voltage source Vpw. Likewise, the well contact 113 of the n-well 111 is split off from the source terminal 108 of the PFET 102 by providing a separate metallic rail contact 118 which is spaced from the metallic rail contact 115 of the source terminal 108. Rail contact 118 is connected to a bias voltage source Vnw. Thus, in this example, the substrate bias potential of the NFET 101 is set by Vpw, and that of the PFET 102 is set by Vnw.

[0012] FIG. 1(b) illustrates a similar design, except that the substrate or bulk of the NFET 101 is biased to Vpw by way of a metallic back plane 119, rather than by way of the well tie 116 shown in FIG. 1(a).

[0013] As mentioned above, in order to provide near-zero threshold voltages, the channel regions of the devices should be constituted of near intrinsic semiconductor material. In typical non-near-zero threshold devices, surface dopant concentrations in the channel regions will be on the order of 1e17 (per cm³), thus allowing for the selection of a base material on the order of 1e16. In the context of FIGS. 1(a) and 1(b), this would mean that the bulk material 106 would have a concentration of about 1e16 and the p-well 107 and the n-well 111 would have a concentration (particularly at the surface regions) of about 1e17. Even at these concentrations, leakage is present between the n-well 111 and the p-bulk 106. Moreover, for low threshold voltage devices, a surface dopant concentration on the order of 1e15 is desired, meaning that a bulk material is selected having a concentration of about 1e14. These reduced concentrations widen the depletion regions at the p-n junctions, and thus further exacerbate the problem of leakage currents at the p-n junctions. Such leakage is illustrated in FIGS. 1(a) and 1(b) by the multiple arrows extending across the boundary between the n-well 111 and the p-bulk 106.

[0014] Junction leakage can present problems in other configurations as well. For example, FIG. 2 is a simplified view of an SOI buried well device. This particular to device is characterized by a buried n-well 202 (i.e., an inverse well) implanted beneath a buried oxide layer 204. The buried well 202 is an n+ region forming a back gate electrode. The oxide layer 204 is buried in a p-substrate material 206 which is lightly doped to accommodate the concentration characteristics needed for the channel region located above the oxide layer 204 and between source and drain regions 208 and 210. Reference number 207 is an isolation oxide. As an example, the n-well may have a concentration of about 1e17, and the p-substrate 206 may have a concentration on the order of 1e16. As illustrated by the multiple arrows in FIG. 2, the device suffers junction leakage between the n-well 202 and the p-substrate 206.

[0015] It is thus an object of the present invention to provide a semiconductor device structure and method which reduce junction leakage across p-n junctions.

[0016] It is a further object of the present invention to provide a semiconductor device structure and method which reduce junction leakage in MOS device structures, and particularly in lightly doped back biased circuits having near-zero threshold voltages, and/or in SOI buried well devices.

[0017] According to one aspect of the present invention, a semiconductor device is provided which includes a semiconductor bulk material of a first conductivity type and having a first dopant concentration; a semiconductor well of a second conductivity type contained in the semiconductor bulk material; and a semiconductor region of the first conductivity type and having a second dopant concentration which is greater than the first dopant concentration, the semiconductor region interposed between a bottom wall of the semiconductor well and the semiconductor bulk material to reduce leakage across a junction between the bottom wall of the semiconductor well and the semiconductor bulk material.

[0018] According to another aspect of the present invention, the semiconductor device further includes at least one second semiconductor region of the first conductivity type and having a third dopant concentration which is greater than the first dopant concentration, the at least one second semiconductor region interposed between at least one side wall of the semiconductor well and the semiconductor bulk material to reduce leakage across a junction between the at least one side wall of the semiconductor well and the semiconductor bulk material.

[0019] According to yet another aspect of the invention, the semiconductor device further includes source and drain regions of the first conductivity type formed in the semiconductor well to define a channel region therebetween.

[0020] According to still another aspect of the present invention, a dopant concentration of the semiconductor well is greater at a boundary with the semiconductor region than at the channel region.

[0021] According to still another aspect of the present invention, the semiconductor well is buried within the bulk material, and the semiconductor device further includes an insulator layer interposed between a top wall of the semiconductor well and a top surface of the semiconductor bulk material, and source and drain regions of the second conductivity type extending from the top surface of the semiconductor bulk material and a top wall of the insulator layer.

[0022] According to another aspect of the present invention, a semiconductor device is provided which includes a semiconductor bulk material of a first conductivity type and having a first dopant concentration; a semiconductor well of a second conductivity type contained in the bulk material; a first transistor formed in the semiconductor bulk material, the first transistor having source and drain regions of the second conductivity type and defining a first channel region therebetween; a second transistor formed in the semiconductor well, the second transistor having source and drain regions of the first conductivity type and defining a second channel region therebetween; means for biasing the first and second channel regions; and a semiconductor region of the first conductivity type and having a second dopant concentration which is greater than the first dopant concentration, the semiconductor region interposed between a bottom wall of the semiconductor well and the semiconductor bulk material to reduce leakage across a junction between the bottom wall of said semiconductor well and the semiconductor bulk material. The first and second transistors may have near-zero threshold voltages.

[0023] According to yet another aspect of the present invention, a method is provided for reducing junction leakage in a semiconductor device having a semiconductor well of a first conductivity formed in a semiconductor material of a second conductivity, the method including implanting a semiconductor region of the first conductivity so as to be interposed between a bottom wall of the semiconductor well and the semiconductor material, wherein a dopant concentration of the semiconductor region is greater than that of the semiconductor material so as to reduce the width of a depletion region at a junction between the bottom wall of the semiconductor well and the semiconductor material.

[0024] The above and other features and advantages of the present invention will become readily apparent from the description that follows, with reference to the accompanying drawings, in which:

[0025] FIGS. 1(a) and 1(b) illustrate conventional back-biased CMOS configurations;

[0026] FIG. 2 is a simplified view of an SOI buried well device;

[0027] FIGS. 3(a) and 3(b) illustrate examples of back-biased CMOS configurations employing buried p+ regions for reducing junction leakage at a bottom wall of an n-well according to the present invention;

[0028] FIG. 4 illustrates an example of a device in which an n-well is retrograded to further reduce junction leakage;

[0029] FIG. 5 illustrates an example of a device in which buried p+ regions are employed to reduce junction bias at a bottom wall and side walls of an n-well according to the present invention;

[0030] FIG. 6 shows an SOI buried well configuration employing a buried p+ region for reducing junction bias at a bottom wall of an buried n-well; and,

[0031] FIG. 7 shows an SOI buried well configuration employing p+ regions for reducing junction bias at a bottom wall and side walls of an buried n-well.

[0032] The present invention is at least partially characterized by the implantation of a high concentration (p+ or n+ ) region at the junction boundary for which leakage current is to be reduced. In the case of MOS n-well designs, the p+ dopant is preferably buried at a depth sufficient to result in a junction capacitance less than 20% of the gate capacitance (for performance optimization) and will arrest depletion region growth as a function of back bias. Also, the high concentration region should preferably have a dopant level which is higher than that of the surrounding bulk material by a factor of about 10 or more.

[0033] Attention is now directed to FIG. 3 for an explanation of the invention as it may be applied to a CMOS device. In this example, each of an NFET 301 and a PFET 302 essentially constitutes a four-terminal device. The NFET 301 is made up of an n-region source 303, a gate electrode 304, an n-region drain 305, and a p bulk substrate 306. The NFET 301 may also include a p-well 307 as shown. Similarly, the PFET 302 includes p-region source 308, a gate electrode 309 and a p-region drain 310 formed in an n-well 311. Reference numeral 312 is a p⁺plug which forms a bulk terminal or well tie for the p-well 307 or bulk material 306, and reference numeral 313 is an n⁺plug forming a well tie for the n-well 311.

[0034] In the back-biased CMOS design of FIG. 3(a), the well contact 312 of the bulk material 306 is split off from the source terminal 303 of the NFET 301 by providing a separate metallic rail contact 316 which is spaced from the metallic rail contact 314 of the source terminal 303. Rail contact 316 is connected to a bias voltage source Vpw. Likewise, the well contact 313 of the n-well 311 is split off from the source terminal 308 of the PFET 302 by providing a separate metallic rail contact 318 which is spaced from the metallic rail contact 315 of the source terminal 308. Rail contact 318 is connected to a bias voltage source Vnw. Thus, in this example, the substrate bias potential of the NFET 301 is set by Vpw, and that of the PFET 302 is set by Vnw.

[0035] FIG. 3(b) illustrates a similar design, except that the substrate or bulk of the NFET 301 is biased to Vpw by way of a metallic back plane 319, rather than by way of the well tie 316 shown in FIG. 3(a).

[0036] As should be readily apparent, the configurations of FIGS. 3(a) and 3(b) are similar to those of FIGS. 1(a) and 1(b) discussed previously, except for the provision of buried p+ regions 320 at the bottom wall junction between n-well 311 and the p-bulk 306. The p+ regions 320 are heavily doped regions (i.e., p+ regions), and thus reduce the width of the depletion region at the p-n junction of the n-well 311 and the p-bulk 306. The reduced depletion region is accompanied by reduced leakage through the bottom wall of the n-well 320.

[0037] In this example, the devices are configured as near-zero voltage threshold devices. As such, the dopant concentrations of the n-well 311 (particularly in the channel region) is on the order of 1e15, and that of the p-bulk 306 is about 1e14, and the dopant concentration of the p+ regions 320 could be on the order of 1e17, thereby substantially reducing the width of the depletion region at the p-n junction.

[0038] The depletion region width can be further reduced by adopting a retrograde n-well structure in which the dopant concentration in the n-well increases with depth. That is, while it is important that any low or near-zero voltage threshold device be near intrinsic at the channel region, such is not necessary deep within the n-well. This is illustrated in FIG. 4 which shows n-well 411 having two n-regions 411aand 411b.The region 411aabuts the p+region 420 and has a dopant concentration, for example, of about 1e16, whereas the region 411bis partially contained within the channel region of the device and has a dopant concentration, for example, of about 1e15. As such, the concentrations at the p-n junction are 1e16 for the n-region 411aand 1e17 for the p-region 420, thus reducing the width of depletion region as compared to the example above in which the n-region at the junction has a concentration of 1e15.

[0039] Also, although not shown in the retrograde well configuration of FIG. 4, the well 411 can be subjected to lateral grading as well (or lateral grading alone) to reduce p-n junction leakage at the sidewalls of the well 411. As opposed to the retrograde profile which can be done with appropriate dose and energy, the lateral grading would be accomplished by an additional implant in which the channel region is masked.

[0040] According to the present invention, leakage is reduced along p-n junctions by elevating the dopant concentration on one or both sides of the junction. Typically, one side will have a higher concentration than the other, such as an n-well in a p-substrate, so only p-enhancement is necessary. However, in some cases, especially in low threshold devices, the well is sufficiently lightly doped that both p-enhancement and n-enhancement are necessary. This enhancement may be applied to the bottom or sidewalls or both. In standard devices it may not be necessary to increase dopant concentration at the junctions due to the higher dopant concentrations resulting from the high thresholds. However, it becomes much more important in low threshold devices, especially when a potentially large back bias is applied.

[0041] A technique for further reducing n-well leakage is illustrated in FIG. 5. In this example, the sidewalls of the n-well 511 are surrounded by p+ regions 520. Again, the p+ regions 520 are high concentration regions which reduce the width of the depletion region at the sidewall boundaries. For example, the dopant concentration of the p+ regions 520 may be about 1e17, while those of the p-bulk 506 and the n-well 511 may be on the order of 1e14 and 1e15, respectively. Also, the retrograde well of FIG. 4 may be adopted in the configuration of FIG. 5, to even further reduce junction leakage.

[0042] FIG. 6 illustrates an example in which the technique of the present invention is applied to an SOI buried well device. This device includes a buried n-well 602 (i.e., an inverse well) implanted beneath a buried oxide layer 604. The buried well 602 is an n+ region forming a back gate electrode. The oxide layer 604 is buried in a p-substrate material 606 which is lightly doped to accommodate the concentration characteristics needed for the channel region located above the oxide layer 604 and between source and drain regions 608 and 610. Reference numeral 607 is an isolation oxide. As an example, the n-well 602 may have a concentration of about 1e17, and the p-substrate 606 may have a concentration on the order of 1e16. In order to reduce leakage between the buried n-well 602 and the p-substrate 606, the device further includes a high concentration region 612 interposed between a bottom wall of the n-well 602 and the p-substrate 606. Continuing with the same example, the region 612 may have a dopant concentration on the order of 1e17, thus reducing the width of the depletion region at the bottom wall p-n junction.

[0043] In another example shown in FIG. 7, the sidewalls of the buried n-well 702 are surrounded by a p+ regions 712. Again, the p+ regions 712 are high concentration regions which reduce the width of the depletion region at the sidewall boundaries. For example, the dopant concentration of the p+ regions 712 may be about 1e17, while those of the p-substrate 706 and the n-well 702 may be on the order of 1e16 and 1e17, respectively.

[0044] It is noted that in each of the embodiments described above, the p+ regions for arresting leakage may be formed to either abut or overlap the n-region of the p-n junction for which leakage is to be reduced. Implantation techniques for forming buried layers of different conductivities and concentrations within semiconductor materials are well known in the art and may be readily applied in forming the various structures described above. Also, the invention is equally applicable to arresting leakage of p-wells using highly doped n+ regions.

[0045] The technique of the present invention at least partially resides in the provision of high concentration regions at low concentration p-n junctions to reduce the width of the depletion regions of the p-n junctions. This in turn reduces leakage across the p-n junctions. Many structural variations for realizing such high concentration regions for arresting p-n junction leakage may be contemplated by those skill in the art. In this respect, the present invention has been described by way of specific exemplary embodiments, and the many features and advantages of the present invention are apparent from the written description. Thus, it is intended that the appended claims cover all such features and advantages of the invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation as illustrated and described. Hence all suitable modifications and equivalents may be resorted to as falling with the scope of the invention.