Frequency modulator

[0002] This invention relates to a frequency modulator and a transmitter and transceiver incorporating a frequency modulator for a digital radio communication device.

[0003] Many digital radio communication systems, such as cellular, cordless and data transmission systems, use FSK, GFSK or GMSK modulation techniques. These types of modulation techniques are in fact simply frequency modulation (FM) with the radio frequency (RF) signal envelope constant.

[0004] Since there is no amplitude modulation (AM) involved in these types of modulation, the voltage controlled oscillator (VCO) frequency of the transmitters can be directly modulated by the baseband signal, as is typical in regular analog FM transmitters, such as in analog cellular systems. Significant cost reductions can be obtained by directly modulating the VCO frequency so that such arrangements are particularly desirable in digital applications where low cost is a strategic factor. For example, the overall cost of a digital solution such as DECT must be very low to be competitive with well known analog systems such as CT0.

[0005] For analog systems, the voice spectrum, 300 to 3000 Hz or more, is compatible with the lock-up time of the PLL synthesizer when the modulation is applied to the VCO. The lock-up time is generally never less than 5 or 6 ms. However, when applying this low cost technique in digital systems, the baseband signal, which modulates the VCO, is the filtered No-Return-to-Zero (NRZ) data stream coming from the logic section of the transmitter device. This baseband signal has a very low frequency content in its spectrum (from a few Hz). Since the required lock-up time for the PLL synthesizer is around few microseconds, it is not compatible with the spectrum of the baseband signal. The low frequencies of the modulation are considered like VCO drifts and so are corrected by the PLL loop. This incompatibility problem means that either the low frequency content of the baseband signal is lost or the speed of the PLL loop, which determines the speed for channel selection, is compromised.

[0006] Thus, before this low cost technique can be advantageously applied in digital systems, the problem of ensuring compatibility with the PLL synthesizer lock-up time needs to be resolved and further requirements have to be considered.

[0007] For example, in order to avoid any inter symbol interferences which could corrupt the eyes pattern and degrade the Bit Error Rate of the transmission in the digital system, the group delay on the modulation path has to be kept constant in all the spectrum of the baseband signal.

[0008] Furthermore, in order to meet the applicable radio specifications, the spectral purity of the RF signal source to be transmitted should be maintained as near the carrier signal as possible for phase noise and modulation accuracy, and as far from the carrier signal as possible for harmonics, noise floor, discrete spurious signals. Should this last requirement be sufficiently met, filters and duplexers would no longer be needed which would provide a drastic reduction in cost of the transmitter. Being able to reduce the filters and duplexers is significant in keeping the overall cost of the digital system down which improves the competitiveness of the digital solution compared to the analog solution.

[0009] Several modulation techniques which modulate the VCO in a digital system are known.

[0010] For example an I/Q modulator has been used in a direct or heterodyne architecture. This type of modulator is driven by two RF signals in quadrature coming from an external oscillator which is tuned on the transmitted frequency (direct architecture) or on an intermediate frequency (heterodyne architecture) and by two complex baseband signals, calculated from the data stream (I and Q signals). With such architectures, the RF oscillator(s) or synthesizer(s) are independent of the modulation process so that the lock-up time can be chosen independently from the baseband signal spectrum. However, such architectures are complex and require an expensive ‘I/Q’ interface in the baseband which can be justified for very accurate GMSK systems, like GSM, but not in standards like DECT or CT2, where the modulation index can vary by large amounts and where cost is strategic. A further disadvantage with these techniques it that they are noisy and so do not allow for the filters and duplexers to be removed.

[0011] A different but well known technique uses a heterodyne arrangement with a fixed modulated local oscillator. A channel synthesizer which meets the lock-up time requirements is mixed with a crystal oscillator or a very slow synthesizer able to handle the modulation. This type of arrangement is very efficient and robust and allows zero blind slots because the channel synthesizer is fast enough. In other words, with this type of arrangement every slot can be used. However, it always generates many mixing products out of the bandwidth of the signal to be transmitted, which have to be strongly filtered, increasing the cost of the transmit path.

[0012] Another technique called the ‘open loop’ technique has been used with cordless standards such as DECT or CT2. As mentioned above, a problem with applying the modulation to the VCO is that the low frequency part of the FM modulation will be corrected by the loop of the synthesizer as it does for frequency drift of the VCO. In order to avoid this, the open loop technique opens the loop during a transmission slot so that the VCO is working in a free-run mode without any feedback and can be modulated without any correction from the loop. After the transmission slot, the loop is closed again and the VCO resynchronized. Resynchronization is however difficult to achieve. In fact, it is so difficult to achieve, that the VCO must typically work at half the final frequency and must be followed by a frequency doubler to be properly buffered against transients and frequency drifts. This requires many filters which increases the overall cost of the transmitter device. A further disadvantage of the open loop technique is that it does not allow for zero blind slots because of the frequency drift due to the free-run mode.

[0013] In addition, the phase detector of the synthesizer for the open loop technique is very hard to design because of the low leakage current required.

[0014] In fact, the open loop technique cannot be used in ‘high-end’ standards, such as GSM or MOBITEX, where parasitic drifts due to the free-run mode periods are not allowed by the respective specifications. The open loop technique can be implemented for standards such as DECT and CT2, but due to its difficult resynchronisation, only half of the available slots can be used. This is a problem for public base stations or for range improvement.

[0015] There is therefore a need to provide an improved low cost frequency modulator for a digital radio communication device which overcomes the above described problems.

[0016] In accordance with the present invention there is provided a frequency modulator for modulating a carrier signal according to a modulation data signal to provide a modulated output signal, the frequency modulator comprising:

[0017] a reference signal generator coupled to receive the modulation data signal for generating a reference signal modulated according to the modulation data signal; and

[0018] a main synthesizer coupled to receive the modulated reference signal and the modulation data signal for providing the modulated output signal at an output, and wherein the reference signal generator comprises an auxiliary synthesizer having a lock-up time which is substantially greater than that of the main synthesizer, the auxiliary synthesizer comprising:

[0019] an auxiliary phase detector having a first input for receiving a fixed reference signal having a fixed frequency, a second input and an output for providing an error signal representing the difference in phase between the fixed reference signal and a signal at the second input; and

[0020] an auxiliary VCO coupled to receive the error signal and the modulation data signal for generating the modulated reference signal at an output, the output of the auxiliary VCO being coupled to the main synthesizer and to the second input of the auxiliary phase detector.

[0021] Thus, by modulating the reference signal supplied to the main synthesizer with the modulation data signal and by applying the modulation data signal to the main synthesizer, the present invention ensures that the modulation process to provide the modulated output signal is independent of the speed of the main synthesizer. This means that the low frequency components of the modulation data signal are not lost nor is the speed of the main synthesizer compromised.

[0022] Preferably, the modulated reference signal has a first modulation gain and the modulated output signal has a modulation gain which is substantially proportional to the first modulation gain. This results in the modulated output signal RFout having a response which is flat in amplitude and group delay, and independent of modulating frequency.

[0023] In a preferred arrangement, the main synthesizer for generating the modulated output signal and for controlling the frequency of the carrier signal, comprises:

[0024] a phase detector having a first input for receiving the modulated reference signal, a second input and an output for providing an error signal representing the difference in phase between the modulated reference signal and a signal at the second input;

[0025] a VCO coupled to receive the error signal and the modulation data signal for generating the modulated output signal at an output of the VCO; and

[0026] a variable divider coupled between the output of the VCO and the second input of the phase detector for dividing the modulated output signal by a selectable value so as to vary the frequency of the carrier signal. With such an arrangement, the first modulation gain is preferably arranged to be substantially equal to the gain of the modulated output signal divided by the selectable value of the variable divider.

[0027] Two frequency modulators in accordance with the present invention, a transceiver and a transmitter, both incorporating frequency modulators in accordance with the invention, will now be described, by way of example only, with reference to the accompanying drawings in which:

[0028] FIG. 1 is a block schematic diagram of a transceiver incorporating a frequency modulator in accordance with the present invention;

[0029] FIG. 2 is a block schematic diagram of a frequency modulator;

[0030] FIG. 3 is a block schematic diagram of a first frequency modulator in accordance with the present invention;

[0031] FIG. 4 is a block schematic diagram of a second frequency modulator in accordance with the present invention;

[0032] FIG. 5 is a schematic diagram showing the frequency components of a PLL loop in which the VCO is modulated;

[0033] FIG. 6 is a schematic diagram showing the frequency components of a PLL loop in which the reference signal is modulated; and

[0034] FIG. 7 is a schematic diagram showing the frequency components of a PLL loop in which the VCO and the reference signal is modulated by the modulation data signal in accordance with the present invention.

[0035] Referring firstly to FIG. 1, part 2 of a transceiver device incorporating a frequency modulator 3 in accordance with the present invention is shown comprising a transmit path TX and a receive path RX coupled via a switch 4 and a low-pass filter 8 to an antenna 6.

[0036] The frequency modulator 3 has an input 5 for receiving a modulation data signal which is generated from a data stream using a modulation technique, such as FSK, GFSK or GMSK, as is well known in the art. The data stream may include voice information. For GMSK modulation, the modulation data signal or baseband signal is an analog voltage generated by a GMSK analog filter (not shown). The frequency modulator 3 generates a carrier signal having a selectable frequency and modulates the carrier signal using the modulation data signal to provide a modulated output signal RFout at an output. The modulated output signal RFout is then amplified by the RF power amplifier 10 before being coupled to the antenna 6. The structure and function of the frequency modulator 3 will be described in more detail below.

[0037] The receive path RX includes a first bandpass filter 12, a low noise amplifier (LNA) 14, a second bandpass filter 16, a mixer 18 and an IF filter 20. The mixer 18 mixes the RF signal received at the antenna 6 with a reference signal which may be generated by a local oscillator (not shown) or by the frequency modulator 3 as shown in FIG. 1 so as to produce an intermediate frequency signal IF. Using the signal generated by the frequency modulator 3 avoids the need for an additional local oscillator.

[0038] Although the frequency modulator 3 in accordance with the present invention has been shown in FIG. 1 as part of a transceiver, it will be appreciated that the frequency modulator 3 in accordance with the present invention may be used in a transmitter.

[0039] Referring now firstly to FIG. 2, a frequency modulator 50 comprises a main synthesizer 52 and a reference signal generator 54. The modulation data signal received at an input 51 of the frequency modulator 50 is coupled to the main synthesizer 52 and the reference signal generator 54. The main synthesizer 52 provides at an output the modulated output signal RFout and the reference signal generator 54 generates a modulated reference signal Fr which is supplied to the main synthesizer 52.

[0040] The reference signal generator 54 comprises a crystal oscillator 64 and a variable gain control 66. The modulation data signal is applied directly to the crystal oscillator so as to provide the modulated reference signal Fr. The variable gain control 66 is set so that the modulated reference signal Fr has a first modulation gain Kr.

[0041] The main synthesizer 52 comprises a phase detector 56, a loop filter 58, voltage controlled oscillator (VCO) 60 and a variable divider 62 arranged in a typical phase-locked loop (PLL) arrangement. The variable divider 62 divides the modulated output signal RFout at an output of the VCO 60 by a selectable value n so as to provide a divided modulated output signal. The selectable value n determines the frequency of the carrier signal which is generated by the VCO 60. In other words, the variable divider 62 is the channel selector of the main synthesizer 52.

[0042] The phase detector 56 has a first input for receiving the modulated reference signal Fr, a second input for receiving the divided modulated output signal and an output for providing an error signal representing the difference in phase between the modulated reference signal and the divided modulated output signal. The error signal is then filtered by the loop filter 58 before being applied to the VCO 60.

[0043] The filtered error signal, which is a voltage signal, is applied directly to the VCO 60 so as to generate a carrier signal whose frequency depends on the filtered error signal.

[0044] A disadvantage of such a frequency modulator 50 is that the crystal oscillator 64 itself is modulated and so cannot be used for other parts of the transceiver device. A device incorporating the frequency modulator 50 would therefore require additional crystal oscillators which would increase the cost of such a device. A further disadvantage of the frequency modulator 50 is that for wideband modulation (i.e. high data rates), the technique of modulating the crystal oscillator cannot be used.

[0045] Referring now to FIG. 3, a first frequency modulator 150 in accordance with a first embodiment of the present invention comprises a main synthesizer 152 and a reference signal generator 154. The modulation data signal received at an input 151 of the frequency modulator 150 is coupled to the main synthesizer 152 and the reference signal generator 154. The main synthesizer 152 provides at an output the modulated output signal RFout and the reference signal generator 154 generates a modulated reference signal Fr which is supplied to the main synthesizer 152.

[0046] The reference signal generator 154 comprises an auxiliary synthesizer 155 coupled to a crystal oscillator 164 and to receive the modulation data signal at the input 151 such that the modulation data signal modulates an auxiliary VCO 170 of the auxiliary synthesizer 155. The output of the auxiliary VCO 170 provides the modulated reference signal to the main synthesizer 152.

[0047] The main synthesizer 152 comprises a phase detector 156, a loop filter 158, voltage controlled oscillator (VCO) 160 and a variable divider 162 arranged in a typical phase-locked loop (PLL) arrangement. The variable divider 162 divides the modulated output signal RFout at an output of the VCO 160 by a selectable value n so as to provide a divided modulated output signal. The selectable value n determines the frequency of the carrier signal which is generated by the VCO 160. In other words, the variable divider 162 is the channel selector of the main synthesizer 152.

[0048] The phase detector 156 has a first input for receiving the modulated reference signal Fr, a second input for receiving the divided modulated output signal and an output for providing an error signal representing the difference in phase between the modulated reference signal and the divided modulated output signal. The error signal is then filtered by the loop filter 58 before being applied to the VCO 160.

[0049] Normally, the filtered error signal, which is a voltage signal, is applied directly to the VCO 160 so as to generate a carrier signal whose frequency depends on the filtered error signal. However, in the preferred embodiment, the modulation data signal, in addition to the filtered error signal, is applied to the VCO 160, for example by combining the modulation data signal, which as mentioned above is an analog baseband voltage, with the filtered error signal, such that the analog baseband voltage and the error voltage determines the output of the VCO 160.

[0050] In order to apply the filtered error signal and the modulation data signal to the VCO 160, the VCO may have two control inputs or one control input. Preferably, the filtered error signal and the modulation data signal are combined by applying the modulation data signal to a modulation varicap diode of the VCO 160 and the filtered error signal to a tuning diode of the VCO 160. In a further embodiment, both the modulation data signal and the filtered error signal may be applied to the tuning varicap diode, such as diode 168.

[0051] By modulating the VCO 170 rather than the crystal oscillator, the first embodiment has an advantage in that the reference frequency signal Fr′ generated by the crystal oscillator 164 can be re-used for different purposes within the transceiver. This is not possible with the frequency modulator 50 since the crystal reference is modulated directly. Moreover, in same applications, particularly those where the modulation index is high such as in DECT systems, there can be problems in modulating the frequency of the crystal oscillator. Using an auxiliary synthesizer to make a copy of the signal from the crystal oscillator 164 avoids this problem.

[0052] The auxiliary synthesizer 154 comprises an auxiliary phase detector 174, an auxiliary loop filter 176, an auxiliary VCO 170 and a divider 172 arranged in a typical phase-locked loop (PLL) arrangement. The divider 172 divides the modulated reference signal Fr at an output of the auxiliary VCO 170 by a fixed value so as to provide a divided modulated reference signal.

[0053] The auxiliary phase detector 174 has a first input for receiving the reference signal Fr′ generated by the crystal oscillator 164, a second input for receiving the divided modulated reference signal and an output for providing an error signal representing the difference in phase between the reference signal Fr′ and the divided modulated reference signal. The error signal is then filtered by the auxiliary loop filter 176 before being applied to the auxiliary VCO 170 together with the modulation data signal. These signals are combined in similar manner to that described above for VCO 160. For example, the modulation data signal and filtered error signal are both applied to a tuning varicap diode 178 of the VCO 170. The modulation data signal is coupled to the auxiliary synthesizer 155 via a variable gain control 166 so that the VCO 170 is modulated with a first modulation gain Kr to provide the modulated reference signal Fr at the output of the VCO 170.

[0054] The modulation gain KV of the VCO 160 is preferably adjustable by having an attenuator (not shown) coupled between the input 151 of the second frequency modulator 150 and an input of the VCO.

[0055] Referring now also to FIG. 4, a second frequency modulator 250 in accordance with a second embodiment of the present invention comprises a main synthesizer 252 and a reference signal generator 254. A data stream received at an input 251 of the second frequency modulator 250 is coupled to the main synthesizer 252 and the reference signal generator 254. In the embodiment shown in FIG. 4, GMSK modulation is used. The data stream received at input 251 is thus filtered in a GMSK analog filter 253 before being coupled to the main synthesizer 252 as a modulation data signal. The main synthesizer 252 provides at an output the modulated output signal RFout and the reference signal generator 254 generates a modulated reference signal Fr which is supplied to the main synthesizer 252.

[0056] The reference signal generator 254 in accordance with the second embodiment comprises a direct digital synthesizer (DDS), such as the AD9830 DDS supplied by Analog Devices. The DDS 254 has a digital input coupled directly to the data stream before filtering which allows for the reference frequency generated to be digitally modulated by the modulation data signal and an output for providing the modulated reference signal Fr to the main synthesizer 252. This modulation in the DDS 254 can be performed by an auxiliary look-up table 255, computing on N bits, for each clock period, the modulation trajectory, N giving the accuracy of the process (the greater is N, the greater is the accuracy). A channel or a sub-channel increment can be performed through the regular N bits adressing bus of the main look-up table 257, after addition to the modulation N bits result, in order to vary slightly if needed, the centre of the reference frequency Fr, and consequently, the centre vlaue of the modulated output signal Rfout. The operation of the DDS is well known in the art.

[0057] The main synthesizer 252 comprises a phase detector 256, a loop filter 258, voltage controlled oscillator (VCO) 260 and a fixed divider 263 arranged in a typical phase-locked loop (PLL) arrangement.

[0058] The operation of the main synthesizer 252 is the same as described above with reference to FIG. 3. Like components to those of FIG. 3 are reference by the same reference numeral plus the number one hundred.

[0059] The basic principle of operation of the frequency modulator in accordance with the present invention is to apply the modulation data signal to the VCO of the main synthesizer and also to the reference signal with a correct level balance between the two paths.

[0060] In order to understand completely this basic principle, a theoretical analysis will now be given with reference to FIGS. 5-7. FIG. 5 is a schematic diagram showing the frequency components of a PLL loop in which the VCO is modulated only, FIG. 6 is a schematic diagram showing the frequency components of a PLL loop in which the reference signal is modulated only and FIG. 7 is a schematic diagram showing the frequency components of the PLL loop in which the VCO and the reference signal is modulated by the modulation data signal in accordance with the present invention.

[0061] Referring firstly to FIG. 5, the voltage signal e which is applied to the varicap diode of a VCO 600 to generate a modulated output signal OUT is given by the following equation: $\begin{array}{cc}e=A+\mathrm{em}=\frac{e\left(\mathrm{KV}*KØ*F\left(p\right)\right)}{\mathrm{np}}+\mathrm{em}& \left(1\right)\end{array}$

[0062] where em is the modulation data signal

[0063] Fconst is a constant reference signal

[0064] KV is the modulation gain of the VCO 600 in Hz per Volts

[0065] KØ is the gain of the phase detector 560 in Volts per Radians

[0066] F(p) is the transfer function of the loop filter 580 (low pass filter)

[0067] n is the divide ratio of the variable divider 620

[0068] From equation 1, the transfer function for the modulation on the VCO loop is: $\begin{array}{cc}\frac{e}{\mathrm{em}}=\frac{1}{1-\frac{\left(\mathrm{KV}*KØ*F\left(p\right)\right)}{\mathrm{np}}}& \left(2\right)\end{array}$

[0069] This transfer function represents a high pass behaviour.

[0070] Referring now also to FIG. 6, for a modulated reference signal Fmod, the error signal Σ at the output of a phase detector 560 is given by the following equation: $\begin{array}{cc}\Sigma =\frac{\mathrm{Fmod}}{p}-e\frac{\mathrm{KV}}{\mathrm{np}}& \left(3\right)\end{array}$

[0071] The voltage signal e is given by:

[0072] e=−KØ*F(p)*Σ  (4)

[0073] By combining equations (3) and (4), the transfer function for the modulation on the reference signal loop is: $\begin{array}{cc}\frac{e}{\mathrm{Fmod}}=\frac{n*KØ*F\left(p\right)}{\left(KØ*F\left(p\right)*\mathrm{KV}\right)-\mathrm{np}}& \left(5\right)\end{array}$

[0074] This represents a low pass behaviour.

[0075] Referring now to FIG. 7, the voltage signal e which is applied to the varicap diode of the VCO 160 of FIG. 3 or the VCO 260 of FIG. 4 to generate the modulated output signal RFout is given by the following equation:

[0076] e=em−KØ*F(p)*Σ(6)

[0077] Since the error signal Σ at the output of a phase detector 56 is: $\begin{array}{cc}\Sigma =\mathrm{em}\frac{\mathrm{Kr}}{p}-e\frac{\mathrm{KV}}{\mathrm{np}}& \left(7\right)\end{array}$

[0078] where em is the modulation data signal

[0079] Fr is the modulated reference signal

[0080] KV is the modulation gain of the VCO 60, 160 in Hz per Volts

[0081] KØ is the gain of the phase detector 56, 156 in Volts per Radians

[0082] F(p) is the transfer function of the loop filter 58, 158 (low pass filter)

[0083] n is the divide ratio of the variable divider 62, 162

[0084] Kr is the first modulation gain of the modulated reference signal Fr

[0085] By substituting equation (7) in equation (6), then: $\begin{array}{cc}\frac{e}{\mathrm{em}}=\frac{1-\frac{\left(\mathrm{Kr}*KØ*F\left(p\right)\right)}{p}}{1-\frac{\left(\mathrm{KV}*KØ*F\left(p\right)\right)}{\mathrm{np}}}& \left(8\right)\end{array}$

[0086] From equation (8), $\mathrm{when}\mathrm{Kr}=\frac{\mathrm{KV}}{n},\mathrm{then}\frac{e}{\mathrm{em}}=1$

[0087] Thus, from the above theoretical analysis when the first modulation gain Kr of the modulated reference signal Fr is equal to the modulation gain KV of the VCO of the main synthesizer divided by n, there is no low pass and high pass behaviour. In practice, it has been found that substantially the same effect can be achieved when the first modulation gain Kr of the modulated reference signal Fr is close to the modulation gain KV of the VCO of the main synthesizer divided by n; that is, when the first modulation gain Kr of the modulated reference signal Fr is proportional to the modulation gain KV.

[0088] Though the first modulation gain Kr is adjusted with the selectable value n and hence with the carrier frequency, the system is broadband enough to require only one trimming point within a 100 Mhz bandwidth or more at 2 GHz.

[0089] As mentioned above, the principle of operation of the frequency modulator in accordance with the present invention is to apply the modulation data signal to the VCO of the main synthesizer and also to the reference signal with a correct level balance between the two paths. Correct balance occurs when the values of the modulation gains Kr and KV are selected so that the first modulation gain Kr of the modulated reference signal Fr is substantially proportional to the modulation gain KV of the VCO. This results in the modulated output signal RFout having a response which is flat in amplitude and group delay, and independent of modulating frequency.

[0090] For the first frequency modulator 150, it is also necessary to ensure that the bandwidth of the auxiliary synthesizer 155 is substantially less than the bandwidth of the main synthesizer 152 or in other words, that the lock-up time of the auxiliary synthesizer 155 is substantially greater than that of the main synthesizer 152. The reference signal generator 154 then performs a low frequency modulation process, and the VCO of a main synthesizer 152 is involved in the high frequency modulation process with a result that the combination covers the whole bandwidth of the modulation data signal. Since the low frequency components of the modulation data signal modulate the reference signals, these components are not lost in the main synthesizer's PLL loop as they would be if only the main VCO was modulated. These low frequency components are then combined with the high frequency components of the modulation data signal which components are outside the bandwidth of the main synthesizer loop so as to provide the modulated output signal.

[0091] By utilising an auxiliary synthesizer 154 having a greater lock-up time than the main synthesizer 152 and by modulating the auxiliary VCO 170 by the modulation data signal, the main synthesizer 152 can be fast enough to be used as a channel selector and meet the lock-up time specification as required for the high frequency components.

[0092] Thus, from the above analysis it is clear that by modulating the reference signal supplied to the main synthesizer and the VCO of the main synthesizer with the modulation data signal, the present invention ensures that the modulation is independent of the speed of the main synthesizer. This means that the low frequency components of the modulation data signal are not lost nor is the speed of the main synthesizer compromised. Moreover, since the present invention ensures that the modulation is independent of the speed of the main synthesizer, there is substantially no limitation on the speed for the channel selection.

[0093] Since the present invention applies the modulation data signal directly to the main VCO 160, 260 which is coupled to the antenna via a power amplifier but not via mixers or other noisy components as with the prior art systems, the present invention provides a low noise and direct synthesis process which means that filters and duplexers are no longer needed in the transmit path and a lower cost power amplifier can be used. This represents a drastic cost reduction compared to known digital systems, some of which are described above in the introduction.

[0094] An additional advantage of the frequency modulator in accordance with the present invention, as can be seen from the first 150 and second 250 frequency modulators described above, is that it can be realised with low cost component blocks.

[0095] A further advantage is that the main synthesizer is always locked which means that every slot can be used in TDMA systems allowing data transmission or real range improvement.

[0096] Since the present invention ensures that the speed of the main synthesizer of the frequency modulator is optimised, the same main synthesizer can be used for the receive path RX in a transceiver. As mentioned above, such an arrangement avoids the need for an additional synthesizer in the receive path.

[0097] Although the present invention has been described above with reference to digital radio communication devices, the principle of the present invention could also be applied to analog radio communication devices.