US 6,344,980 B1Grant
Universal pulse width modulating power converter
Issue Date:2002-02-05
•15 Claims
•16 Drawing Sheets
Abstract
A controller for a pulse width modulating (PWM) power converter. The controller monitors an output voltage and a current through a magnetic element for modulating a duty cycle of a main power switch. The controller is an eight-pin integrated circuit which controls either a forward converter or a post regulator without internal modifications. The monitored current of the forward converter forms a positive sensing signal. The monitored current of the post regulator forms a negative sensing signal. A current sense circuit of the controller forms an absolute value of either sensing signal. A soft-start circuit of the controller forms a start-up voltage ramp which is proportional to the level of a VCCsupply without requiring an external capacitor. A duty cycle of the main switch is gradually increased by comparing the start-up voltage ramp to the absolute value of the sensing signal. A pulse skipping circuit of the controller disables switching of the main switch under light load conditions. An error signal representative of a difference between the output voltage and a desired output voltage is compared to a pulse skip reference voltage. When the error signal falls below the reference voltage, the main switch is disabled. Because the pulse skip reference voltage is inversely related to the VCCsupply, pulsing of the main switch under light load conditions is spread out in time. A clock signal utilized to control switching of the main switch is generated internally or externally to the integrated circuit.
Metadata
Assignee
- Fairchild Semiconductor Corporation
Inventors
- Jeffrey Hwang
- Calvin Hsu
Application Information
Application Number:US 09/436,074
Filing Date:1999-11-08
Priority Date:1999-01-14
Art Unit:7
Classifications
IPC:
H02M 3335
Field of Search:
363 16363 20363 2101363 2104363 2105363 2107363 2112363 2113363 2115363 95363 97363131323222
Patent Drawings (16 sheets)
Description
Related Application
[0002] This application is a continuation-in-part of U.S. patent application Ser. No. 09/231,523, filed, Jan. 24, 1999, and entitled, “INTERLEAVED ZERO CURRENT SWITCHING IN A POWER FACTOR CORRECTION BOOST CONVERTER”, now U.S. Pat. No. 6,091,233, the contents of which are hereby incorporated by reference.
Field of the Invention
[0003] The invention relates to the field of switching electrical power converters. More particularly, the invention relates to the field of pulse width modulating forward converters and post regulators.
Background of the Invention
[0004] FIG. 1 illustrates a schematic block diagram of a conventional pulse width modulating (PWM) forward converter. As illustrated in FIG. 1, a voltage source VSis coupled to a first terminal of a primary winding of a transformer T. A second terminal of the primary winding of the transformer T is coupled to a drain of a MOS transistor M. A source of the transistor M is coupled to a first terminal of a resistor RSENSE. A second terminal of the resistor RSENSEis coupled to a first ground node. A voltage signal ISENSEformed at the first terminal of the resistor RSENSEis representative of a level of current passing through the primary winding of the transformer T when the transistor M is active.
[0005] A first terminal of a secondary winding of the transformer T is coupled to an anode of a diode D. A cathode of the diode D is coupled to a first terminal of a capacitor C1, to an output node, and to a first terminal of a resistor R1. A second terminal of the secondary winding of the transformer T and a second terminal of the capacitor C1are coupled to a second ground node. A second terminal of the resistor R1is coupled to a first terminal of a resistor R2and to an inverting input of an error amplifier A. A second terminal of the resistor R2is coupled to the second ground node. The resistors R1and R2form a resistive divider for supplying the amplifier A with a signal which is proportional to an output voltage VOUTat the output node. The amplifier A can include optical elements so as to optically isolate the first ground node from the second ground node.
[0006] A non-inverting input of the amplifier A is coupled to a reference voltage VREF. The reference voltage VREFis representative of a desired level for the output voltage VOUT. An output of the amplifier A forms an error signal VEAand is coupled to a non-inverting input of a comparator CMP1. The error signal VEAis representative of a difference between the output voltage VOUTand a desired level for the output voltage. The first terminal of the resistor RSENSEis coupled to an inverting input of the comparator CMP1and to an inverting input of a comparator CMP2. An output of the comparator CMP1is coupled to a first input of a logic NAND gate U1. A current source is coupled to a first terminal of a capacitor C2and to a non-inverting input of the comparator CMP2. A second terminal of the capacitor C2is coupled to the first ground node. A voltage signal VSTARTis formed at the first terminal of the capacitor C2.
[0007] An output of the comparator CMP2is coupled to a second input of the NAND gate U1. An output of the NAND gate U1is coupled to a set input S of a flip-flop U2. A reset input R of the flip-flop U2is coupled to receive a clock signal VCLK. An inverted output {overscore (Q)} of the flip-flop U2is coupled to a gate of the transistor M.
[0008] When the transistor M is active (turned on), current flows from the source VSand through the primary winding of the transformer T. This stores energy as an electromagnetic field associated with the primary winding of the transformer T. When the transistor M is inactive (turned off), the electromagnetic field collapses. By turning the transistor M on and off, energy is transferred to the secondary winding of the transformer T which induces a current to flow in the secondary winding. The current in the secondary winding of the transformer T is rectified by the diode D so as to form a voltage across the capacitor C1. A duty cycle utilized for operating the transistor M controls the level of the output voltage VOUTformed at the output node.
[0009] FIGS. 2a-billustrate timing diagrams for the signals VEA, ISENSEand VCLKof the PWM forward converter illustrated in FIG. 1. When the clock signal VCLKtransitions from a logical low voltage to a logical high voltage, the output {overscore (Q)} of the flip-flop U2transitions to a logic high voltage. This turns on the transistor M. Under these conditions, current flows through the transistor M and the resistor RSENSE, as illustrated in FIG. 2aby the signal ISENSEramping up. When the signal ISENSEreaches the level of the error signal VEA, this causes the output of the comparator CMP1to change from a logic high voltage to a logic low voltage. As a result, the output of the NAND gate U1changes from a logic low voltage to a logic high voltage and the output {overscore (Q)} of the flip-flop U2transitions from a logic high voltage to a logic low voltage. This turns off the transistor M. Upon a next transition of the clock signal VCLK, this cycle repeats. Note that as the error signal VEAincreases, the transistor M stays on for a longer portion of each cycle of the clock signal VCLKbecause more time is required for the signal ISENSEto exceed the error signal VEA. Conversely, as the error signal VEAfalls, the transistor M stays on a smaller portion of each cycle of the clock signal VCLKbecause less time is required for the error signal ISENSEto exceed the error signal VEA. Accordingly, the output voltage at the node VOUTis regulated to the desired level by adjusting the duty cycle of the transistor M according to requirements of a load (not shown) which can be coupled to the output node to receive the output voltage VOUT.
[0010] Under normal operating conditions, the voltage VSTARTis at a higher level than the error signal VEA. Accordingly, the output of the comparator CMP2is a logic high voltage when the output of the comparator CMP1changes. Therefore, under normal operating conditions, the output of the comparator CMP2does not affect the duty cycle of the transistor M and the PWM converter operates as described above.
[0011] Upon start up, however, the output voltage VOUTis low. As a result, the error signal VEAis relatively large. In absence of soft-start circuit elements, including the current source I, the capacitor C2and the comparator CMP2, this large error signal would result in the transistor M being held on for a large portion of each cycle of the clock signal VCLKwhile the forward converter attempted to rapidly increase the output voltage to the desired level. As a result, excessive current would flow through the transistor M which would tend to cause premature failure of the transistor M.
[0012] Instead, upon start up, the current source I is turned on and the signal VSTARTslowly ramps up. Before the level of the signal VSTARTexceeds the level of the signal VEA, the duty cycle of the transistor M is not influenced by the signal VEA, but by the signal VSTART. As a result, the duty cycle of the transistor M gradually increases until the level of the signal VSTARTexceeds the level of the error signal VEA.
[0013] While the soft-start circuit elements of FIG. 1 provide a useful function, they also result in a disadvantage, especially when elements of the forward converter are incorporated into an integrated circuit. More particularly, so that the signal VSTARTramps up slowly, the current produced by the current source I must be small in relation to the size of the capacitor C2. This constraint either requires that the capacitor C2be external to the integrated circuit, which increases the pin count of the integrated circuit and, thus, the cost of producing the integrated circuit, or requires that the current produced by the current source I be so small as to be easily overwhelmed by noise and other transient signals, which reduces reliability.
[0014] Therefore, what is needed is improved soft-start technique for a PWM power converter.
[0015] Further, prior integrated circuits for controlling PWM power converters have been specifically tailored to the intended application. For example, a different integrated circuit design is utilized for a PWM forward converter than is utilized for a PWM post-regulator. This requirement of multiple integrated circuit designs tends to increase the costs associated with each.
[0016] Therefore, what is needed is a universal integrated circuit for controlling a PWM power converter.
Summary of the Invention
[0017] The invention is a universal controller for a pulse width modulating (PWM) power converter. The controller monitors an output voltage of the power converter and a current through a magnetic element of the power converter for modulating a duty cycle of a main power switch of the power converter. The main power switch is closed in response to a transition in a clock signal. When the main power switch is closed, the current through the magnetic element forms a sensing signal (current ramp) representative of the current through the main power switch. The sensing signal is compared to an error signal representative of a difference between the output voltage and a desired level for the output voltage. When the sensing signal exceeds the error signal, the main power switch is opened. Opening and closing of the main power switch draws power from an input voltage source for forming the output voltage. In this manner, the duty cycle of the main power switch is controlled in a feedback loop. In a preferred embodiment, the controller is implemented as an eight pin integrated circuit.
[0018] According to an aspect of the present invention, the controller can be utilized for a power converter which is either a PWM forward converter or a PWM post regulator where differences between the PWM forward converter and the PWM post regulator are exclusively in circuitry external to the controller. In particular, the magnetic element of the power converter is a transformer; the main power switch for the PWM forward converter controls a current through a primary side of the transformer, whereas, the main power switch for the PWM post regulator controls a current through the secondary side of the transformer. When the power converter is a PWM forward converter, the sensing signal is positive in polarity, whereas, when the power converter is a PWM post regulator, the sensing signal is negative is polarity. A current sense circuit included in the controller forms a signal which is representative of the absolute value of the sensing signal for comparison to the error signal.
[0019] According to another aspect of the present invention, the controller includes a soft-start circuit which gradually increases a duty cycle of the main power switch upon start-up of the power converter. The soft-start circuit monitors the ramping up of a VCCpower supply and, in response, forms a start-up voltage ramp. The start-up voltage ramp begins ramping when the VCCpower supply reaches a first predetermined voltage level and is substantially proportional to a level of the VCCpower supply as the level of VCCexceeds the first predetermined voltage level. In a preferred embodiment, the start-up voltage ramp is formed by generating a current which is substantially proportional to the level of the VCCsupply (minus the first predetermined voltage level) and by applying this current to a resistor, such that the start-up voltage ramp is formed across the resistor. During start-up, the start-up voltage ramp is compared to the current ramp for controlling the duty cycle of the main power switch. As a result, the duty cycle gradually increases upon start-up as the level of the voltage supply increases. Unlike prior arrangements, the start-up circuit does not require an external capacitor for forming the start-up voltage ramp. This reduces the number pins required when the controller as implemented as an integrated circuit.
[0020] According to a further aspect of the present invention, a pulse skipping circuit disables switching of the main power switch when a load powered by the power converter draws a low level of current. When the output voltage rises, as tends to occur when the load draws a low level of current, the error signal decreases. The error signal is compared to a pulse skip reference voltage. When the level of the error signal falls below the level of the pulse skip reference voltage, the main power switch is disabled until the error signal rises again. Preferably, the pulse skip reference voltage is inversely related to the supply voltage VCC. Accordingly, when the supply voltage VCCis at a higher level, the output voltage must rise to a higher level before the main power switch is disabled than when the supply voltage VCCis at a lower level. Therefore, forming the pulse skip reference voltage such that it is inversely related to the supply voltage tends to aid in spreading out in time pulsing of the main power switch under light load conditions. This tends to reduce switching noise while increasing efficiency.
[0021] According to yet another aspect of the present invention, the clock signal which is utilized to control switching of the main power switch can be selectively generated internally to the integrated circuit or externally to the integrated circuit. It is expected that when the power converter is a PWM forward converter, the clock signal is internally generated, whereas, when the power converter is a PWM post regulator, the clock signal is externally generated for synchronizing switching of the PWM post regulator with that of a pre-regulator.
Brief Description of the Drawings
[0022] FIG. 1 illustrates a schematic block diagram of a conventional pulse width modulating (PWM) forward converter.
[0023] FIGS. 2a-billustrate timing diagrams for signals of the PWM forward converter illustrated in FIG. 1
[0024] FIG. 3 illustrates a schematic block diagram of a universal integrated circuit controller for a PWM power converter in accordance with the present invention.
[0025] FIG. 4 illustrates a schematic diagram of a PWM forward converter which incorporates the integrated circuit controller illustrated in FIG. 3.
[0026] FIGS. 5a-hillustrate timing diagrams for selected signals of the controller and PWM forward converter illustrated in FIGS. 3-4.
[0027] FIG. 6 illustrates a schematic block diagram of the soft-start circuit illustrated in FIG. 3.
[0028] FIGS. 7a-billustrate a timing diagrams for selected signals of the soft-start circuit illustrated in FIGS. 3 and 6.
[0029] FIG. 8 illustrates a more detailed schematic diagram of the soft-start circuit illustrated in FIGS. 3 and 6.
[0030] FIG. 9 illustrates a schematic diagram of the PWM comparator illustrated in FIG. 3.
[0031] FIG. 10 illustrates a schematic block diagram of the pulse skip circuit illustrated in FIG. 3.
[0032] FIG. 11 illustrates a more detailed schematic diagram of the pulse skip circuit illustrated in FIGS. 3 and 10.
[0033] FIG. 12 illustrates a block schematic diagram of the current limit circuit illustrated in FIG. 3.
[0034] FIG. 13 illustrates a schematic diagram of a PWM post regulator which incorporates the integrated circuit controller illustrated in FIG. 3.
[0035] FIGS. 14a-eillustrate timing diagrams for selected signals of the post regulator illustrated in FIG. 13.
[0036] FIG. 15 illustrates a block schematic diagram of the current sense circuit illustrated in FIG. 3.
[0037] FIG. 16 illustrates a power converter circuit in accordance with the present invention including multiple post-regulators coupled to respective windings of a single transformer.
Detailed Description of a Preferred Embodiment
[0038] FIG. 3 illustrates a schematic block diagram of a universal controller 100 for a pulse width modulating (PWM) power converter in accordance with the present invention. In the preferred embodiment, the controller 100 is implemented as an integrated circuit which includes eight pins, numbered 1-8 in FIG. 3. Pin 1 receives a signal GM from circuit elements external to the controller 100 and is coupled to an inverting input of an error amplifier A1. Preferably, the amplifier A1is a transconductance (gm) amplifier. A non-inverting input of the amplifier A1is coupled to a reference voltage VREF1. An output of the amplifier A1forms an error signal VEA1and is coupled to a first non-inverting input of a three-input PWM comparator CMP3, to Pin 2 and to a first input of a pulse skip circuit 102. Pin 2 receives a signal VDCfrom circuit elements external to the controller 100 when the controller 100 is utilized in a forward converter. However, Pin 2 is coupled to compensation elements when the controller 100 is utilized in a post-regulator, as explained in more detail herein. The signals VEA1and VDCcan be present at the node coupled to the first non-inverting input of the comparator CMP3. Only one of the signals VEA1, or VDCactively controls a level of the voltage at this node at a time depending upon the particular application. An output of the pulse skip circuit 102 is coupled to a first input of a logic NOR gate U3.
[0039] Pin 3 receives a voltage signal ISENSE1or a voltage signal ISENSE2from circuit elements external to the controller 100 and is coupled to an input of a current sense circuit 104 and to an input of a current limit circuit 106. An output of the current sense circuit 104 is a signal ISENXwhich is coupled to an inverting input of the comparator CMP3. The signal ISENXapplied to the inverting input of the comparator CMP3is representative of the signal ISENSE1or the signal ISENSE2which is applied to the input of the current sense circuit 104 though the polarity of the signal ISENXis preferably positive regardless of the polarity of the signal ISENSE1or ISENSE2output of the current limit circuit 106 forms a signal ILIMand is coupled to a second input of the NOR gate U3.
[0040] Pin 4 receives a supply voltage VCCfrom circuit elements external to the controller 100 and is coupled to a second input of the pulse skip circuit 102, to a first input of a soft-start circuit 108, to an inverting input of an hysteretic comparator CMP4and to a non-inverting input of an hysteretic comparator CMP5. An inverting input of the comparator CMP5is coupled to a reference voltage VREF2. An output of the comparator CMP5forms a signal UVLO and is coupled to a second input of the soft-start circuit 108. An output of the soft-start circuit 108 forms a signal VSTART1and is coupled to a second non-inverting input of the comparator CMP3. An output of the comparator CMP3is coupled to a first input of a logic OR gate U4.
[0041] Pin 5 is coupled to receive a signal SELECT from circuit elements external to the controller 100 and is coupled to an input of a reference adjust circuit 110. The reference adjust circuit 110 adjusts internal reference voltages for use by the controller 100 according to a logic level of the SELECT signal.
[0042] Pin 6 can be coupled to receive a signal SYNC from circuit elements external to the controller 100 and is coupled to an input of an oscillator 112. An output of the oscillator 112 forms a clock signal VCLK1and is coupled to a second input of the OR gate U4, to a reset input R of a reset-dominant flip-flop U5and to a first input of a logic NOR gate U6. A clock signal generated externally to the controller 100 can be coupled to Pin 6 of the controller 100. In which case, the clock signal VCLK1is synchronous with the externally generated clock signal. Otherwise, if an externally generated clock signal is not applied to Pin 6 of the controller 100, then the clock signal VCLK1is generated by the oscillator 112 as a “free running” signal (i.e. the clock signal VCLK1is not synchronous with any externally generated clock signal).
[0043] An output of the OR gate U4is coupled to a first input of a logic NAND gate U7. An output of the NOR gate U3is coupled to a second input of the NAND gate U7. An output of the NAND gate U7is coupled to a set input S of the flip-flop U5. A Q output of the flip-flop U5is coupled to a second input of the NOR gate U6. An output of the NOR gate U6is coupled to a first input of a logic AND gate U8. An output of the comparator CMP4forms a signal OVP and is coupled to a second input of the AND gate U8. An output of the AND gate U8is coupled to Pin 7 of the controller 100 and forms a switch control signal PWM OUT which is provided to circuit elements external to the controller 100.
[0044] FIG. 4 illustrates a schematic diagram of a PWM forward converter 200 which incorporates the controller 100 illustrated in FIG. 3. A voltage source VSis coupled to a first terminal of a resistor R3and to a first terminal of a primary winding of a transformer T1. A second terminal of the primary winding of the transformer T1is coupled to a drain of a MOS transistor M1. Pin 7 of the controller is coupled to a gate of the transistor M1. A source of the transistor M1is coupled to a first terminal of a sensing resistor RSENSE1and to Pin 3 of the integrated circuit controller 100. A second terminal of the resistor RSENSE1is coupled to a first ground node. The signal ISENSE1is formed at the first terminal of the resistor RSENSE1and is representative of a level of current passing through the primary winding of the transformer T1when the transistor M1is active (turned on). When the transistor M1is inactive (turned off), current flowing in the primary winding of the transformer T1can be returned to the supply VSthrough a diode (not shown for simplicity of illustration).
[0045] A first terminal of a secondary winding of the transformer T1is coupled to an anode of a diode D1. A cathode of the diode D1is coupled to a cathode of a diode D2and to a first terminal of an inductor L1. A second terminal of the inductor L1is coupled to a first terminal of a capacitor C3, to a first output node, and to a first terminal of an optical isolator 202. A second terminal of the secondary winding of the transformer T1, an anode of the diode D2and a second terminal of the capacitor C3are coupled to a second ground node. An output voltage VOUT1is formed at the first output node. A load 204 can be coupled across the capacitor C3.
[0046] A second terminal of the optical isolator 202 forms the signal VDCand is coupled to Pin 2 of the controller 100. The gm amplifier A1with its Pin 1 input tied to ground is utilized to supply a pull-up current for the optical isolator 202. A third terminal of the optical isolator 202 is coupled to a first terminal of a resistor R4. A second terminal of the resistor R4is coupled to the first ground node. The signal VDCis an error signal which is representative of a difference between the output voltage VOUT1formed at the output node and a desired level for the output voltage VOUT1. A value of the resistor R4sets the desired level of the output voltage VOUT1. Because the optical isolator 202 forms the error signal VDC, the signal VDCis applied to the first non-inverting input of the comparator CMP3(FIG. 3) and the amplifier A1(FIG. 3) is disabled from forming the error signal VEA1. However, as mentioned above, the amplifier A1forms the pull-up current for the optical isolator 202. The optical isolator 202 optically isolates the first ground node from the second ground node. For example, the optical isolator 202 can include a TL431 optical isolator.
[0047] A first terminal of a second secondary winding of the transformer T1is coupled to an anode of a diode D3. A cathode of the diode D3is coupled to a first terminal of a capacitor C4, to a second output node, to Pin 4 of the controller 100 and to a second terminal of the resistor R3. A supply voltage VCCfor the integrated circuit controller 100 is formed at the second output node. A second terminal of the second secondary winding of the transformer T1, a second terminal of the capacitor C4, Pin 5 of the controller 100 and Pin 8 of the controller 100 are coupled to the first ground node.
[0048] FIGS. 5a-hillustrate timing diagrams for selected signals of the controller 100 and PWM forward converter 200 illustrated in FIGS. 3-4. More particularly, FIG. 5aillustrates the clock signal VCLK1; FIG. 5billustrates a signal at the Q output of the flip-flop U5; FIG. 5cillustrates a signal at the output of the NOR gate U6; FIG. 5dillustrates the switch control signal PWM OUT at Pin 7 of the controller 100; FIG. 5eillustrates a signal at the output of the OR gate U4; FIG. 5fillustrates a signal at the output of the NAND gate U7; FIG. 5gillustrates a signal at the output of the comparator CMP3; and FIG. 5hillustrates the error signal VDCand sensing signal ISENSE1.
[0049] Referring to FIGS. 3-5, upon the clock signal VCLK1transitioning to a logic high voltage, as shown at time zero in FIG. 5a,the flip-flop U5(FIG. 3) is placed in a reset condition and, thus, the Q output of the flip-flop U5is a logic low voltage, as shown in FIG. 5b.Because the flip-flop U5is reset dominant, the flip-flop U5remains in a reset condition while the signal VCLK1is a logic high voltage. In addition, the logic high voltage of the clock signal VCLK1is applied to the first input of the NOR gate U6(FIG. 3). Under these conditions, the output of the NOR gate U6is a logic low voltage, as shown in FIG. 5c.Accordingly, the signal PWM OUT is a logic low voltage, as shown in FIG. 5d,and the transistor M1(FIG. 4) is held off while the clock signal VCLK1is logic high voltage.
[0050] The logic high voltage of the clock signal VCLK1is also applied to the second input of the OR gate U4(FIG. 3). As a result, the output of the OR gate U4is a logic high voltage, as shown in FIG. 5e.Assuming the signals PSKIPand ILIMare both a logic low voltage, then the output of the OR gate U3(FIG. 3) is logic high voltage. As a result, the output of the NAND gate U7(FIG. 3) and the set input S of the flip-flop U5are a logic low voltage, as shown in FIG. 5f.
[0051] Because the transistor M1is held off while the clock signal VCLK1is a logic high voltage, the voltage signal ISENSE1is lower than the error signal VDC, as shown in FIG. 5h.As a result, the output of the comparator CMP3(FIG. 3) is logic high voltage prior to the clock signal VCLK1transitioning to a logic low voltage, as shown in FIG. 5g.
[0052] Then, when the clock signal VCLK1transitions to a logic low voltage, as shown in FIG. 5a,the reset input of the flip-flop U5transitions to a logic low voltage. Thus, the flip-flop U5is no longer held in the reset condition. In addition, the logic high voltage of the output of the comparator CMP3results in the output of the OR gate U4remaining a logic high voltage upon the logic low voltage of the clock signal VCLK1being applied to the second input of the OR gate U4, as shown in FIG. 5e.As a result, the output of the NAND gate U7and the set input S of the flip-flop U5remain a logic low voltage upon a transition in the clock signal VCLK1from high to low, as shown in FIG. 5f.
[0053] Because the set input S of the flip-flop U5is a logic low voltage, the Q output of the flip-flop U5remains a logic low voltage, as shown in FIG. 5b,and, thus, the second input of the NOR gate U6is also logic low voltage. In addition, the logic low voltage of the clock signal VCLK1is applied to the first input of the NOR gate U6. In response, the output of the NOR gate U6transitions to a logic high voltage, as shown in FIG. 5c.Accordingly, the signal PWM OUT also transitions to a logic high voltage, as shown in FIG. 5d.
[0054] As a result, the transistor M1is turned on. As current flows through the transistor M1, the signal ISENSE1begins to rise, as shown in FIG. 5h.Once the signal ISENSE1rises above the level of the error signal VDC, then the output of the comparator CMP3transitions to a logic low voltage, as shown in FIG. 5g.As a result, the output of the OR gate U4transitions to a logic low voltage, as shown in FIG. 5e.Because the output of the OR gate U4is a logic low voltage, the output of the NAND gate U7transitions from a logic low voltage to a logic high voltage, as shown in FIG. 5f.This sets the flip-flop U7, such that the Q output transitions to a logic high voltage, as shown in FIG. 5b.As a result, the output of the NOR gate U6and, thus, the signal PWM OUT become a logic low voltage, as shown in FIGS. 5c-d.This turns the transistor M1off. This process repeats for each cycle of the clock signal VCLK1, thereby regulating the output voltage VOUT1.
[0055] The above-described regulation of the output voltage VOUT1can be altered or interrupted under certain conditions. For example, in the event of a fault condition which results in an excessive level for the output voltage supply VCC(an overvoltage condition), the signal OVP transitions from a logic high voltage to a logic low voltage. In response, the AND gate U8holds the transistor M1off, thereby disabling switching of the transistor M1.
[0056] In addition, under start-up conditions, the soft-start circuit 108 and the comparator CMP3illustrated in FIG. 3 alter operation of the controller 100. FIG. 6 illustrates a schematic block diagram of the soft-start circuit 108. The supply voltage VCCis coupled to a non-inverting input of a comparator CMP6, to a first terminal of a current source I1and to a first terminal of a current source I2. An inverting input of the comparator CMP6is coupled to a reference voltage VREF4. A second terminal of the current source I1is coupled to a drain of a MOS transistor M2. A gate of the transistor M2is coupled to receive the signal UVLO from the comparator CMP5(FIG. 3). A second terminal of the current source I2is coupled to a drain of a MOS transistor M3. An output of the comparator CMP6is coupled to a gate of the transistor M3. A source of the transistor M2and a source of the transistor M3are coupled to a first terminal of a resistor R5. A second terminal of the resistor R5is coupled to the first ground node. The signal VSTART1is formed across the resistor R5.
[0057] FIGS. 7a-billustrate a timing diagrams for selected signals of the soft-start circuit 108 illustrated in FIGS. 3 and 6. More particularly, FIG. 7aillustrates a timing diagram for the supply voltage VCC, while FIG. 7billustrates a timing diagram for the signal VSTART1. Upon start-up, the supply voltage VCCis zero or nearly zero. The supply voltage VSis applied to the forward converter 200 (FIG. 4). In response, the supply voltage VCCgradually ramps up, as shown in FIG. 7a,due to the capacitor C4(FIG. 4) charging through the bleed resistor R3(FIG. 4). As VCCrises to a level sufficient to allow circuits of the controller 100 (FIG. 3) to begin operating, the output of the comparator CMP5(FIG. 3) holds the transistor M2(FIG. 6) off while the comparator CMP6(FIG. 6) holds the transistor M3(FIG. 6) off. In the preferred embodiment, VREF2(FIG. 3) is 12 volts, while VREF4(FIG. 6) is 13 volts. While VCCis below VREF2, the signal VSTART1is zero volts (any residual charge is discharged to the first ground node through the resistor R5(FIG. 6)). This is shown in FIG. 7b where the signal VSTART1is substantially at ground level prior to the time t1where VCCreaches VREF2(e.g., 12 volts).
[0058] The PWM comparator CMP3(FIG. 3) compares the smaller of the signal VDC(or VEA1) and the signal VSTART1to the signal ISENXfor controlling the duty cycle of the transistor M1(FIG. 4). FIG. 9 illustrates a schematic diagram of the PWM comparator CMP3illustrated in FIG. 3. Referring to FIGS. 3-4, upon start-up, the output voltage VOUT1is zero or nearly zero. As such, the error signal VDC(or VEA1) is relatively large, whereas, the signal VSTART1is substantially zero, as explained above. Accordingly, the output of the comparator CMP3prevents the transistor M1from turning on.
[0059] Eventually, the supply VCCreaches a level above VREF2(e.g., 12 volts). This is shown occurring at the time t1in FIG. 7a.In response, the output of the comparator CMP5(FIG. 3) transitions from a logic low voltage to a logic high voltage and the transistor M2(FIG. 6) is turned on. As a result, the current source I1(FIG. 6) generates a current which forms the voltage signal VSTART1across the resistor R5(FIG. 6). The current generated by the current source I1is representative of the level of the supply VCC. In the preferred embodiment, the current generated by the current source I1is substantially proportional to the level of the supply VCConce the supply voltage reaches the level of the reference voltage VREF2. Thus, the current I1can be given as: I1=K1*(VCC−VREF2), where K1is a constant. After VCCsurpasses the level of VREF2, then the signal VSTART1increases as VCCincreases. This is shown in FIG. 7bby the signal VSTART1gradually rising after the time t1, as does the supply voltage VCCin FIG. 7a.
[0060] After the time t1, the output of the comparator CMP3, no longer prevents the transistor M1(FIG. 4) from turning on. Rather, the signal VSTART1is compared to the signal ISENXby the comparator CMP3so as to allow the transistor M1to turn on for a portion of each cycle of the clock signal VCLK1. In response, VCCincreases further and the output voltage VOUT1(FIG. 4) starts to increase. As the level of the supply VCCcontinues to gradually increase, so does the level of the signal VSTART1. Accordingly, the duty cycle of the transistor M1gradually increases after the time t1. In response, the output voltage VOUT, ramps up while the error signal VDC(or VEA1) begins to fall.
[0061] Eventually, the error signal VDC(or VEA1) can fall to a level below that of the signal VSTART1, at which point, the soft-start circuit 108 no longer affects operation of the forward converter 200. In the preferred embodiment, however, once the supply voltage VCCrises to a level of VREF4(e.g., 13 volts), the output of the comparator CMP6(FIG. 6) transitions from a logic low voltage to a logic high voltage. As a result, the transistor M3(FIG. 6) turns on. In response, the current source I2(FIG. 6) generates a current which serves to rapidly increase the signal VSTART1to a level which is above the range of possible levels for the error signal VDC(or VEA1). This is shown in FIG. 7awhere the supply voltage VCCexceeds VREF4(e.g., 13 volts) at the time t2and, at the same time, the signal VSTART1rapidly increases, as shown in FIG. 7b.Preferably, the signal VSTART1is rapidly increased to a level of 5 volts because, in the preferred embodiment, the error signal VDCand VEA1, are constrained between zero and five volts. Because VSTART1is raised to a level higher than the error signal VDC, the duty cycle of the transistor M1is no longer affected by the soft-start circuit 108 (FIG. 3) and the forward converter 200 operates to regulate the output voltage VOUT1at the desired level, as described above in reference to FIGS. 3-5.
[0062] In an alternate embodiment, the current source I2(FIG. 6) is omitted and, instead, the drain of the transistor M3is coupled to the supply VCCor to an appropriate reference voltage. When the transistor M3is activated by the signal from the comparator CMP6(FIG. 6), the signal VSTART1is rapidly increased to the level of the supply VCCor to the level of the appropriate reference voltage. In response, the comparator CMP3compares the signal ISENSE1to the error signal VDC(or VEA1) rather than to the signal VSTART1.
[0063] During operation, the supply voltage VCCis preferably maintained at a level of approximately 14 volts, as shown in FIG. 7a.The comparator CMP6(FIG. 6) preferably exhibits a hysteretic characteristic so as to prevent the soft-start circuit 108 from affecting the duty cycle of the transistor M1in the event that the supply voltage VCCdrops. Rather, the soft-start circuit 108 is preferably activated only upon start-up. If the supply voltage VCCfalls below a predetermined low level (e.g., 8 volts), then this indicates an error condition and the controller 100 is preferably shut down until it is reset.
[0064] A feature of the soft start circuit 108 is that the current source I2generates a current which is related to the supply voltage VCC, rather than generating a constant current. This enables the signal VSTART1, formed across the resistor R5(FIG. 6), to increase gradually and reliably although an external capacitor is not required for forming the signal VSTART1. This advantageously reduces the number pins required when the controller 100 as implemented as an integrated circuit. As shown in FIGS. 3-4, such an integrated circuit can be implemented having eight pins and no capacitor, external or otherwise, is required for forming the signal VSTART1.
[0065] FIG. 8 illustrates a more detailed schematic diagram of the soft-start circuit illustrated in FIGS. 3 and 6. The signal DCOK remains a logic high voltage until internal reference voltages of the controller 100 (FIG. 3) reach their operating levels and, then, transitions to a logic low voltage.
[0066] During operation of the forward converter 200 (FIG. 4) it is possible for the load 204 which receives the output voltage VOUT1to draw a low level of current. In which case, the output voltage VOUT1tends increase due to the transistor M1being switched on and off for each cycle of the clock signal VCLK1. In the preferred embodiment, the pulse skip circuit 102 (FIG. 3) disables switching of the transistor M1under certain light load conditions. The pulse skip circuit 102 preferably disables switching of the transistor M1by changing its output signal PSKIPfrom a logic low voltage to a logic high voltage. In response, the output of the NOR gate U3(FIG. 3) changes from a logic high voltage to a logic low voltage. As a result, the output of the NOR gate U6(FIG. 3) and, thus, the signal PWM OUT, remain a logic low voltage, so long as the signal PSKIPis a logic high voltage, regardless of a level of the output of the comparator CMP3(FIG. 3).
[0067] FIG. 10 illustrates a schematic block diagram of the pulse skip circuit 102 illustrated in FIG. 3. A first terminal of a current source 13 and a first terminal of a current source I4are coupled to receive the supply voltage VCC. A second terminal of the current source I3is coupled to a non-inverting input of a comparator CMP7, to a first terminal of a resistor R6, and to a collector of bipolar transistor Q1. A second terminal of the current source I4is coupled to a collector of a bipolar transistor Q2, to a base of the transistor Q2and to a base of the transistor Q1. An emitter of the transistor Q1, an emitter of the transistor Q2and a second terminal of the resistor R6are coupled to the first ground node. The error signal VDC(or VEA1) is coupled to an inverting input of the comparator CMP7. An output of the comparator CMP7forms the signal PSKIP.
[0068] In the preferred embodiment, the current source I3generates a constant current while the current source I4generates a current which is related to the level of the supply VCC. The transistors Q1and Q2form a current mirror such that a current flowing through the transistor Q1is equal to the current generated by the current source I4. Thus, a pulse skip reference voltage signal VSKIPformed across the resistor R6is inversely related to the level of the supply VCC. In the preferred embodiment, the voltage signal VSKIPvaries substantially in reverse proportion to the level of the supply VCC. Accordingly, the voltage signal VSKIPcan be given as VSKIP=K2−(K3*VCC), where K2and K3are constants.
[0069] When the load 204 (FIG. 4) draws a sufficient level of current that the output voltage VOUT1is regulated within a predetermined range, the output PSKIPof the comparator CMP7is logic low voltage. This is because the level of the error signal VDC(or VEA1) is higher than the signal VSKIP. However, when the output voltage VOUT1rises, as tends to occur when the load 204 draws a low level of current, the error signal VDC(or VEA1) decreases. Assuming the level of the error signal VDC(or VEA1) falls below the level of the signal VSKIP, then the transistor switch M1(FIG. 4) will be held off by the signal PSKIPchanging to a logic high voltage until the error signal VDC(or VEA1) rises again to level sufficient to cause the output of the comparator CMP7to return the signal PSKIPto a logic low voltage. Note that when the transistor switch M1is disabled, then the error signal VDC(or VEA1) will tend to rise since no power is delivered to the load 204 when the transistor M1is disabled from switching.
[0070] When the level of the voltage source VSincreases, more energy is transferred by the transformer T1(FIG. 4) for each cycle of the transistor M1(FIG. 4) than when the voltage source VSis at a lower level. It is expected that when the level of the voltage source VSincreases, the supply voltage VCCalso increases. Because the pulse skip reference voltage signal VSKIPis preferably inversely related to the supply voltage VCC, when the supply voltage VCCis at a higher level, the output voltage VOUT1must rise to a higher level before the signal PSKIPis asserted in comparison to when the supply voltage VCCis at a lower level. Forming the signal VSKIPsuch that it is inversely related to the supply voltage VCCtends to aid in spreading out the pulses in the control signal PWM OUT under light load conditions. This tends to conserve supply power and produces less noise than if periodic bursts of several pulses appeared the switch control signal PWM OUT. In addition, the levels of the current sources I3, I4and the value of the resistor R6are preferably selected so as to aid in evenly spreading out in time to the extent practical the individual pulses which appear in the switch control signal PWM OUT.
[0071] FIG. 11 illustrates a more detailed schematic diagram of the pulse skip circuit illustrated in FIGS. 3 and 10.
[0072] FIG. 12 illustrates a block schematic diagram of the current limit circuit 106 illustrated in FIG. 3. The signal ISENSE1(FIG. 3) is coupled to a non-inverting input of a comparator CMP8and to an inverting input of a comparator CMP9. An inverting input of the comparator CMP8is coupled to a reference voltage VREF5. A non-inverting input of the comparator CMP9is coupled to a reference voltage VREF6. An output of the comparator CMP8is coupled to a first input of a logic OR gate U9. An output of the comparator CMP9is coupled to a second input of the OR gate U9. An output of the OR gate U9forms the signal ILIM(FIG. 3).
[0073] In the preferred embodiment, the reference voltage VREF5is positive (e.g., 1.5 volts), and the reference voltage VREF6is negative (e.g., −100 mV). Thus, when the signal ISENSE1is within the range of −100 mV to 1.5 volts, then the signal ILIMis a logic low voltage. As a result, the transistor M1(FIG. 4) is turned on and off, as explained above, to control the output voltage VOUT1. However, when the signal ISENSE1is outside the range of −100 mV to 1.5 volts, this indicates an over-current condition. In response, the signal ILIMtransitions from a logic low voltage to a logic high voltage. This opens (turns off) the transistor M1such that its duty cycle falls to zero. The transistor M1is disabled so long as the over-current condition persists.
[0074] FIG. 13 illustrates a schematic diagram of a PWM post regulator 300 which incorporates the integrated circuit controller 100 illustrated in FIG. 3. A voltage source VSis coupled to a first terminal of a resistor R7and to a first terminal of a primary winding of a transformer T2. A second terminal of the primary winding of the transformer T2is coupled to a drain of an MOS transistor M4. A source of the transistor M4is coupled to a first ground node. An output VCLK2of an oscillator 302 is coupled to Pin 6 of the controller 100 and to an input of an inverter U10. An output of the inverter U10forms a signal {overscore (V)}CLK2and is coupled to a gate of the transistor M4.
[0075] A first terminal of a first secondary winding of the transformer T2is coupled to an anode of a diode D4. A cathode of the diode D4is coupled to a drain of a MOS transistor M5. A gate of the transistor M5is coupled to Pin 7 of the controller 100. A source of the MOS transistor M5is coupled to a cathode of a diode D5and to a first terminal of an inductor L2. A second terminal of the inductor L2is coupled to a first terminal of a capacitor C5, to a first output node, and to a first terminal of a resistor RDIV1. A second terminal of the resistor RDIV1is coupled to a first terminal of a resistor RDIV2and to Pin 1 of the integrated circuit controller 100. A second terminal of the resistor RDIV2is coupled to a second ground node. An output voltage VOUT2is formed at the first output node. A second terminal of the secondary winding of the transformer T2is coupled to an anode of the diode D5, to a first terminal of a sensing resistor RSENSE2, and to a first terminal of a resistor RRAMP. A second terminal of the resistor RRAMPis coupled to a first terminal of a capacitor CRAMPand to Pin 3 of the controller 100. A second terminal of the capacitor CRAMP, a second terminal of the resistor RSENSE2and a second terminal of the capacitor C5are coupled to the second ground node. A load 304 can be coupled across the capacitor C5. A signal ISENSE2is formed at the second terminal of the resistor RRAMPand is representative of a level of current passing through the secondary winding of the transformer T2when the transistor M5is active.
[0076] Pin 2 of the controller 100 is coupled to a first terminal of a resistor RZand to a first terminal of a capacitor CP. A second terminal of the resistor RZis coupled to a first terminal of a capacitor CZ. A second terminal of the capacitor CPand a second terminal of the capacitor CZare coupled to the second ground node. The elements RZ, CPand CZare preferably included for performing compensation/filtering of the current sense ramp ISENSE2.
[0077] A first terminal of a second secondary winding of the transformer T2is coupled to an anode of a diode D6. A cathode of the diode D6is coupled to a first terminal of a capacitor C6, to a second output node, to a second terminal of the resistor R7, to Pin 4 of the controller 100 and to Pin 5 of the controller 100. A supply voltage VCCis formed at the second output node. A second terminal of the second secondary winding of the transformer T2and a second terminal of the capacitor C6are coupled to the second ground node.
[0078] As shown in FIG. 13, the output voltage VOUT2is coupled to Pin 1 of the integrated circuit controller 100 via a resistive divider formed of the resistors RDIV1and RDIV2, whereas, the optical isolator 202 illustrated in FIG. 4 is omitted from FIG. 13. Accordingly, the error signal VEA1is active, whereas, the error signal VDCis not active. The error signal VEA1, is representative of a difference between the output voltage VOUT2and a desired level for the output voltage VOUT2. The error signal VEA1, is utilized by the comparator CMP3(FIG. 3) for regulating the output voltage VOUT2, as explained herein.
[0079] FIGS. 14a-dillustrate timing diagrams for selected signals of the post regulator 300 illustrated in FIG. 13. More particularly, FIG. 14aillustrates a timing diagram for the clock signal {overscore (V)}CLK2; FIG. 14billustrates a timing diagram for the clock signal VCLK2; FIG. 14cillustrates a timing diagram for the signal PWM OUT; FIG. 14dillustrates a timing diagram for the signal ISENSE2; and FIG. 14eillustrates a timing diagram for the error signal VEA1and a timing diagram for the absolute value of the sensing signal ISENSE2, i.e. |ISENSE|.
[0080] Note that because the clock signal VCLK2is applied to Pin 6 of the controller 100, the clock signal VCLK1(FIG. 3) is synchronous with the clock signal VCLK2. As a result, the transistor M5(FIG. 13) is controlled synchronously with the transistor M4. This ensures that the first secondary winding of the transformer T2is energized when the transistor M5is turned on.
[0081] In the preferred embodiment, the clock signals VCLK2and {overscore (V)}CLK2each have a fifty-percent (50%) duty cycle and are one-hundred-eighty degrees (180°) out of phase with each other, as illustrated in FIGS. 14a-b.When the signal VCLK2is a logical high voltage, the signals {overscore (V)}CLK2and PWM OUT are each a logical low voltage, as illustrated in FIGS. 14a-c.Formation of the signal PWM OUT is described in above with reference to FIGS. 3 and 5. Because the signals {overscore (V)}CLK2and PWM OUT are each a logical low voltage, the transistors M4(FIG. 13) and M5(FIG. 13) are off. When the clock signal VCLK2transitions to a logical low voltage, the signals {overscore (V)}CLK2and PWM OUT each transition to a logical high voltage, as shown in FIGS. 14b-c.As a result, the transistors M4and M5are turned on. Because the transistors M4and M5are both on, current flows in the primary winding of the transformer T2, which induces a current to flow in the secondary windings of the transformer T2.
[0082] Current flowing in the first secondary winding of the transformer T2is drawn through the sensing resistor RSENSE2, thereby forming the voltage signal ISENSE2. Because the second terminal of the sensing resistor RSENSE2is coupled to the ground node, the signal ISENSE2, formed at the first terminal of the sensing resistor RSENSE2is negative in polarity, as shown in FIG. 14d.The current sense circuit 104 (FIG. 3) forms the signal ISENXwhich is representative of the absolute value of the signal ISENSE2As shown in FIG. 14e,the absolute value of the signal ISENSE2begins to rise upon the clock signal VCLK2transitioning from a logical high voltage to a logical low voltage. When the absolute value of the signal ISENSE2reaches a level of the error signal VEA1as shown in FIG. 14e, then the output of the comparator CMP3changes from a logic high voltage to a logic low voltage. In response, the signal PWM OUT changes from a logic high voltage to a logic low voltage, as shown in FIG. 14c.This turns the transistor M5off. This cycle repeats upon a next transition in the clock signal VCLK2.
[0083] In this manner, operation of the transistor M5is synchronized with operation of the transistor M4and a duty cycle for the transistor M5is controlled so as to regulate the output voltage VOUT2. Because the output voltage VOUT2is regulated by controlling the duty cycle of the transistor M5, which is located on the same side of the transformer T2as the load 304, the power converter illustrated in FIG. 13 is referred to as a post regulator. This is in contrast to the forward converter illustrated in FIG. 4 in which the transistor M2is located on the opposite side of the transformer T1from the load 204. An advantage of the controller 100 of the present invention is that it can be utilized for controlling switching in a forward converter or a post regulator without modification.
[0084] The above-described regulation of the output voltage VOUT2can be altered or interrupted under certain conditions. For example, in the event of an overvoltage condition, the signal OVP (FIG. 3) transitions from a logic high voltage to a logic low voltage. In response, the AND gate U8(FIG. 3) holds the transistor M5(FIG. 13) off, thereby disabling switching of the transistor M5. In addition, under start-up conditions, the soft-start circuit 108 (FIG. 3) ensures that the duty cycle for the transistor M5is gradually increased. Further, the pulse skip circuit 102 (FIG. 3) temporarily disables the transistor M5when the load 304 (FIG. 13) draws a low level of current. Also the current limit circuit 106 (FIG. 3) disables the transistor M5when the current through the secondary winding of the transformer T2becomes excessive.
[0085] As mentioned, a feature of the present invention allows the same integrated circuit controller 100 to be utilized in a PWM forward converter 200, as illustrated in FIG. 4, and in a PWM post regulator 300, as illustrated in FIG. 13, by modifying only circuitry external to the integrated circuit 100. An aspect of the invention which is in furtherance of this feature is the current sense circuit 104 (FIG. 3). As mentioned above, the current sense circuit 104 ensures that the signal ISENX, which is applied to the comparator CMP3(FIG. 3), is positive in polarity whether the signal ISENSE1(FIG. 4), which is positive in polarity, or the signal ISENSE2(FIG. 13), which is negative in polarity, is applied to the input of the current sense circuit 104.
[0086] FIG. 15 illustrates a block schematic diagram of the current sense circuit 104 illustrated in FIG. 3. The signal ISENSE1(FIG. 4) or the signal ISENSE2(FIG. 13) can be coupled to an input terminal of the current sense circuit 104. The input terminal is coupled to a non-inverting input of an amplifier U11and to a first terminal of a resistor R8.
[0087] A first terminal of a current source I5and a first terminal of a current source I6are coupled to the supply voltage VCC. A second terminal of the resistor R8is coupled to an emitter of a bipolar transistor Q3and to a drain of a MOS transistor M6. A base of the transistor Q3is coupled to a base of a bipolar transistor Q4, to a collector of the transistor Q3and to a second terminal of the current source I5. An emitter of the transistor Q4is coupled to a first terminal of a resistor R9. A second terminal of the resistor R9is coupled to the ground node. A collector of the transistor Q4is coupled to a second terminal of the current source I6and to a base of the transistor M6.
[0088] A drain of the transistor M6is coupled to a base of a bipolar transistor Q6, to a base of a bipolar transistor Q7, to a collector or the transistor Q6and to a collector of a bipolar transistor Q5. An emitter of the transistor Q6and an emitter of the transistor Q7are coupled to the supply voltage VCC. An output of the amplifier U11is coupled to a base of the transistor Q5. An emitter of the transistor Q5is coupled to an inverting input of the amplifier U11and to a first terminal of a resistor R10. A collector of the transistor Q7is coupled to a first terminal of a resistor R11. A second terminal of the resistor R10and a second terminal of the resistor R11are coupled to the ground node. The signal ISENXis formed at the first terminal of the resistor R11. In the preferred embodiment, the resistors R8, R9. R10and R11are equal in value. In addition, the current sources I5and I6preferably provide equal currents.
[0089] The signal ISENSE1is preferably a positive value which is normally within a range of zero to 1.5 volts. When a positive voltage signal, such as the signal ISENSE1, is coupled to the input terminal of the current sense circuit 104 the amplifier U11turns on the transistor Q5. In addition, the transistor M6is off due to its gate-to-source voltage being negative. A voltage formed at the first terminal of the resistor R10is substantially proportional to the signal ISENSE1. A current through the resistor R10is, therefore, also substantially proportional to the signal ISENSE1and is mirrored by the transistors Q6and Q7such that a current which flows through the transistor Q7and the resistor R11is substantially proportional to the signal ISENSE1. Because the current through the resistor R11is substantially proportional to the signal ISENSE, the voltage signal ISENXwhich is formed at the first terminal of the resistor R10is also substantially proportional to the signal ISENSE1.
[0090] When a signal of zero volts is applied to the input terminal of the current sense circuit 104, the transistor Q5is turned off by the amplifier U11. In addition, the transistor M6is substantially off due to its gate-to-source voltage being less than is required to turn on the transistor M6. Accordingly, the output signal ISENXis also zero volts. An offset voltage, e.g., 100 mV, can be inserted in series with the non-inverting input of the amplifier U11to ensure that, under such conditions, the transistor Q5is off.
[0091] The signal ISENSE2is preferably a negative value which is normally within the range of −100 mV to zero volts. When a negative voltage signal, such as the signal ISENSE2, is applied to the input terminal of the current sense circuit 104, the amplifier U11holds the transistor Q5off. In addition, the transistor M6is turned on as its gate-to-source voltage is pulled down by the signal ISENSE2. A voltage at the drain of the transistor M6is substantially equal to the signal ISENSE2. This turns on the transistors Q6and Q7. The transistors Q6and Q7form a current mirror such that each draws a current from VCCwhich is substantially proportional to the signal ISENSE2. The current through the transistor Q7forms the output signal ISENXacross the resistor R11as a positive value which is substantially proportional to the input signal ISENSE2.
[0092] Accordingly, the signal ISENXis representative of the absolute value of the signal ISENSE1or ISENSE2applied to the input of the current sense circuit 104.
[0093] According to yet another aspect of the present invention, one or more additional post regulators 300, as shown in FIG. 13, can be coupled to respective secondary windings of a single transformer. FIG. 16 illustrates a power converter circuit in accordance with the present invention including multiple post-regulators coupled to respective windings of a single transformer. As illustrated in FIG. 16, a voltage source VSis coupled to a first terminal of a primary winding of a transformer T3. A second terminal of the primary winding of the transformer T3is coupled to a drain of a MOS transistor M5. A source of the transistor M5is coupled to a first ground node. An output VCLK3of an oscillator 400 is coupled to an input of an inverter U12and to each of three controllers 100A, 100B and 100C. An output of the inverter U12forms a clock signal {overscore (V)}CLK3which is coupled to control the gate of the transistor M5. Preferably, the clock signals VCLK3and {overscore (V)}CLK3each have a fifty-percent (50%) duty cycle and are one-hundred-eighty degrees (180°) out of phase with each other.
[0094] Each controller 100A, 100B, and 100C can be identical to the controller 100 illustrated in FIG. 3. A first secondary winding of the transformer T3is coupled to a first post-regulator 402 which is controlled by the controller 100A in a manner identical to the post regulator 300 illustrated in FIG. 13 for forming an output voltage VOUTA. A second secondary winding of the transformer T3is coupled to a second post-regulator 404 which is controlled by the controller 100B in a manner identical to the post regulator 300 illustrated in FIG. 13 for forming an output voltage VOUTB. A third secondary winding of the transformer T3is coupled to a third post-regulator 406 which is controlled by the controller 100B in a manner identical to the post regulator 300 illustrated in FIG. 13 for forming an output voltage VOUTC. Each of the output voltages VOUTA, VOUTB, and VOUTCcan be regulated at a different level depending upon the requirements of the respective loads. While three post regulators 402, 404, and 406 are shown, it will be apparent that the present invention can be practiced with another number.
[0095] In an alternate embodiment, the clock signal supplied to the SYNC input of the controller 100 (or controllers 100A-c) is supplied by a prior power converter stage. For example, the prior power converter stage can be a power factor correction (PFC) converter. A suitable PFC converter is described in the related parent application of which this application is a continuation-in-part.
[0096] The present invention has been described in terms of specific embodiments incorporating details to facilitate the understanding of the principles of construction and operation of the invention. Such reference herein to specific embodiments and details thereof is not intended to limit the scope of the claims appended hereto. It will be apparent to those skilled in the art that modifications may be made in the embodiment chosen for illustration without departing from the spirit and scope of the invention. Specifically, it will be apparent to one of ordinary skill in the art that the device of the present invention could be implemented in several different ways and the apparatus disclosed above is only illustrative of the preferred embodiment of the invention and is in no way a limitation. For example, it would be within the scope of the invention to vary the values of the various components, current levels, and voltage levels disclosed herein.
Claims
Certificate of Correction present
The claims shown below may not include correction changes. Use the corrected PDF for authoritative text.
What is claimed is:
1. A power converter having a magnetic element and a switch for selectively interrupting a current through the magnetic element wherein a controller for the switch comprises:
a. current sensing means for sensing the current through the magnetic element wherein the current sensing means receives a first voltage signal representative of the current through the magnetic element and wherein the current sensing means includes means for forming a second voltage signal representative of an absolute value of the first voltage signal whereby the first voltage signal can be positive or negative;
b. voltage sensing means for sensing an output voltage of the power converter; and
c. control means coupled to the first sensing means and to the second sensing means for controlling a duty cycle of the switch based upon the second voltage signal and the output voltage.
2. The power converter according to claim 1 wherein the magnetic element is a transformer having a primary winding and a secondary winding wherein the current through the magnetic element flows through a primary winding of the transformer and an induced current in the secondary winding is rectified for forming the output voltage.
3. The power converter according to claim 1 wherein the magnetic element is a transformer having a primary winding and a secondary winding wherein the current through the magnetic element flows through a secondary winding of the transformer and is induced by a current in the primary winding.
4. The power converter according to claim 3 wherein the transformer comprises one or more additional secondary windings and wherein the power converter further comprises one or more additional switches, one coupled to each additional secondary winding and one or more additional controllers, one coupled to control each switch based upon a current through the respective secondary winding thereby forming one or more additional output voltages, one for each additional secondary winding.
5. The power converter according to claim 1 wherein the magnetic element is a transformer having a primary winding and a secondary winding wherein when the first voltage signal is positive, the current through the magnetic element flows through a primary winding of the transformer and an induced current in the secondary winding is rectified for forming the output voltage, and wherein when the first voltage signal is negative, the current through the magnetic element flows through a secondary winding of the transformer and is induced by a current through a primary winding of the transformer.
6. The power converter according to claim 1 wherein the first voltage signal is formed across a resistor coupled in series with the magnetic element.
7. The power converter according to claim I further comprising current limit means for opening the switch when the first voltage signal rises above a first limit wherein the first limit is positive and opening the switch when the first voltage signal falls below a second limit wherein the second limit is negative.
8. The power converter according to claim 6 wherein the resistor has a first terminal and a second terminal wherein the first voltage signal is formed at the first terminal and the second terminal is coupled to a ground node.
9. The power converter according to claim 8 wherein the first voltage signal is positive when the current through the magnetic element flows to the ground node and wherein the first voltage signal is negative when the current through the magnetic element flows from the ground node.
10. The power converter according to claim 9 wherein the magnetic element is a transformer having a primary winding and a secondary winding wherein when the first voltage signal is positive, the current through the magnetic element flows through a primary winding of the transformer and an induced current in the secondary winding is rectified for forming the output voltage, and wherein when the first voltage signal is negative, the current through the magnetic element flows through a secondary winding of the transformer and is induced by a current through a primary winding of the transformer.
11. The power converter according to claim 10 wherein the controller is an integrated circuit having no more than eight pins.
12. A power converter having a magnetic element and a switch for selectively interrupting a current through the magnetic element wherein the power converter is selected from a group consisting of a forward converter and a post regulator, wherein an integrated circuit controller for the switch is configurable for the forward converter and for the post regulator without modification to the integrated circuit and wherein the integrated circuit comprises:
a. a current sensor for sensing the current through the magnetic element wherein the magnetic element is a primary winding of a transformer when the power converter is a forward converter and wherein the magnetic element is a secondary winding of the transformer when the power converter is a post-regulator;
b. voltage sensor for sensing an output voltage of the power converter; and
c. a switch control circuit coupled to the current sensor and to the voltage sensor for controlling a duty cycle of the switch based upon the current through the magnetic element and the output voltage.
13. The power converter according to claim 12 wherein the current sensor receives a first voltage signal representative of the current through the magnetic element and wherein the first voltage signal is positive when the magnetic element is the primary winding and wherein the first voltage signal is negative when the magnetic element is the secondary winding.
14. The power converter according to claim 13 wherein the current sensor includes means for forming a second voltage signal representative of an absolute value of the first voltage signal.
15. The power converter according to claim 12 wherein the integrated circuit controller has no more than eight pins.
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