Methods of forming the buried strap and its quantum barrier in deep trench cell capacitors

[0002] The present invention relates to the manufacture of semiconductor integrated circuits (ICs) and more particularly to improved methods of forming the buried strap and its quantum conducting barrier (QCB) in deep trench cell capacitors that are fabricated in-situ in the same manufacturing cycle. In addition, these methods allow the formation of new quantum conducting barrier structures by the use of materials such as silicon nitride (Si₃N₄), silicon oxynitride and the like instead of silicon dioxide (SiO₂).

[0003] Buried straps (BS) in deep trenches are extensively used in the manufacture of DRAM chips, in particular for devices with groundrules equal or inferior to 0.25 μm. As known for those skilled in the art, in DRAM chips, an array transfer transistor, typically an insulated gate field effect transistor (IGFET) and a storage capacitor are associated to form an elementary memory cell. Basically, a deep trench having a buried plate surrounding its bottom portion is formed in a doped monocrystalline silicon substrate, then a thin dielectric film is conformally deposited thereon to coat the entire interior trench surface and finally the trench is filled with a doped polysilicon by LPCVD as standard. This doped monocrystalline silicon/dielectric film/doped polysilicon fill structure forms the memory cell capacitor. From the silicon surface, a recess is etched down to set the bottom edge of the buried strap. Undoped polysilicon is then deposited into this recessed area to form the buried strap (BS). The buried strap is bordered by the so-called active area (AA) of the monocrystalline substrate and is buried under the shallow trench isolation (STI) region. The surrounding surfaces of the buried strap have an important effect on its conductivity and solid phase transformation during subsequent oxidation and anneal steps (mainly active area oxidation). During these thermal steps, it occurs a recrystallization of the polysilicon of the region of the buried strap which is contiguous to the active area. This local epitaxy induces the propagation of dislocations along the so-called slip lines into the active area and in the substrate which affect cell capacitor performance. Specifically these defects are believed to cause unpredictable changes of the retention time for the capacitor. More precisely, single cell fails (SCF) occurred in some of the tested memory cells, despite the fact that the same bits were not found defective in previous tests. These defects are called Variable Retention Time (VRT) fails. The VRT problem was first identified for 0.25 μm DRAM chips where some memory cells in the array intermittently switched from a high retention state to a low retention state. Physical failure analysis (PFA) showed out that the most of analyzed VRT failed memory cells were impacted by these crystal dislocations in the active area and in the substrate that had been formed during said thermal steps in the course of the wafer processing.

[0004] To avoid or better control these VRT fails in memory cells, the use of a quantum conducting barrier layer between said contiguous silicon regions becomes an absolute requirement to maximize DRAM chip device performance. As a result, the buried strap will perfectly connect the IGFET and the capacitor of the memory cell only if after said thermal steps (oxidation and anneal), the dopants implanted in the buried strap diffuse into the active area through the quantum conducting barrier. The diffusion depth into the active area is a critical parameter. If the diffusion is too deep, a parasitic vertical transistor (VT) is formed, otherwise some junction leakages occur. Another critical parameter is the buried strap resistance itself which drives the memory cell access time. Consequently, the choice of the quantum conducting barrier material, the buried strap dopant type and concentration are very important factors for the overall chip reliability.

[0005] Starting with the FIG. 1 structure, a conventional buried strap and its quantum conducting barrier (QCB) formation process will be described in conjunction with FIGS. 2A-2F.

[0006] FIG. 1 schematically illustrates the starting structure 10 consisting of a p-type silicon substrate 11 with a conventional pad stack formed by a 5 nm thick SiO₂layer 12 and a 220 nm thick Si₃N₄pad layer 13. As apparent in FIG. 1, a deep trench referenced 14 has been formed in the substrate 11 by RIE etching as standard. Typically, deep trench 14 has a depth about 7 μm and an oblong section of about 450×220 nm at the substrate surface. Afterwards, the capacitor dielectric layer 15 is formed and the deep trench is filled with doped polysilicon material 16. After anneal the doped polysilicon fill 16 is recessed to a depth of 1.2 μm to allow the formation of a thermal SiO₂layer 17 and a TEOS SiO₂(pyrolitic) layer 18 forming the so-called collar layer 17/18 which provides a vertical isolation of the cell capacitor. The TEOS layer 18 is etched down to the remaining Si₃N₄pad layer 13. Then, a second doped polysilicon layer 19 is deposited, annealed and polished down to the remaining Si₃N₄pad layer 13. Polysilicon layer 19 is then recessed 130 nm under the substrate 11 surface. This sets the bottom edge of the buried strap. The collar layer 17/18 is removed from the upper part of the deep trench 14 exposed by a BHF HUANG A/B solution in a DNS 820 tool (Dai Nippon Screen, Yasu, Japan). This isotropic wet etch will recess the oxide materials of collar layer 17/18 slightly under the polysilicon layer 19 level as apparent in FIG. 1. At last, a angled phosphorous implant is performed in the trench sidewall that is exposed to create region 20 which is part of the active area. This step is followed by a 200:1 DHF pre clean in a CFM tool (sold by CFM, Westchester, Pa., USA) to remove 3 nm of the native SiO₂layer. The next steps, i.e. the buried strap and its QCB formation must be performed very quickly e.g. within 1 hour (Q-time) of said pre clean step otherwise a rework would be necessary. In fact, this short processing time is required to avoid native oxidation of the exposed silicon substrate 11.

[0007] Now, turning to FIG. 2A, a 1.5 nm thin oxide QCB layer 21 is formed by thermal oxidation at exposed silicon surfaces in a LPCVD vertical thermal reactor (VTR) during boat insertion under ambient atmosphere. The QCB layer 21 is made of thermal SiO₂, a material which is an electrical insulator by nature, however, when deposited in very thin film it becomes electrically conductive by a quantum mechanical effect. An adequate reactor is the baseline undoped polysilicon VTR 7000+ manufactured by SVG THERMCO, Orange, Calif., USA.

[0008] The current working conditions are:

[0009] N₂load lock: no

[0010] Q-time: 1 hour

[0011] Boat pitch: 0.14 inch

[0012] Batch size: 100 wafers centered

[0013] Insert temp.: 620° C.

[0014] Insert time: 10 min

[0015] It is important to notice that an uncontrollable oxidation rate is the main drawback of this step.

[0016] Now referring to FIG. 2B, a 300 nm thick undoped polysilicon layer 22 is deposited in the same LPCVD VTR tool. As mentioned above, this undoped polysilicon layer 22 is amorphous and will subsequently form the buried strap.

[0017] The working conditions are:

[0018] Deposition temp.: 550° C.

[0019] Deposition press.: 0.2 Torr

[0020] Deposition time: 167 min

[0021] SiH₄flow: 260 sccm

[0022] Deposition rate: 18 Å min

[0023] The SiO₂QCB layer 21 will reduce recrystallization (epitaxial regrowth) of the amorphous silicon forming the buried strap and the number of dislocations nucleating at the region 20/polysilicon layer 22 interface. The QCB layer 21 thickness is critical because it has to be thick enough to prevent VRTs and parasitic vertical transistors (VTs) but thin enough to be conductive to insure low buried strap resistance. Consequently, the extreme positions in the LPCVD boat are forbidden, the goal is to have the oxygen level (dose) in layer 21 ranging from 2.2×10¹⁵atoms/cm²(corresponding to a too thin oxide layer) to 3.0×10¹⁵atoms/cm²(corresponding to a too thick oxide layer). In these conditions the batch size in the LPCVD VTR tool mentioned above is limited to 100 wafers centered in the boat.

[0024] A planarization of the polysilicon layer 22 is performed by chemical-mechanical polishing (CMP) down to the remaining Si₃N₄pad layer 13. An adequate tool is the WESTECH 372M polisher manufactured by SPEEDFAM-IPEC, Phoenix, Ariz., USA, At this stage of the fabrication process, the structure is shown in FIG. 2C.

[0025] Now turning to FIG. 2D, the undoped polysilicon material of layer 22 is etched until a recess of 40 nm below the substrate 11 surface is obtained. This step which can be performed in an AME 5000 RIE etcher, a tool manufactured by APPLIED MATERIALS, Santa Clara, Calif., USA, is very critical. There will be no buried strap formation if the recess is too deep. On the other hand, there will be no isolation between the buried strap and the gate conductor line (the passing word line) if the recess is too shallow.

[0026] A vertical implantation of phosphorous (or arsenic) atoms is performed in the undoped amorphous polysilicon layer 22. To that end, a PI 9500 tool, manufactured by APPLIED MATERIALS, Santa Clara, Calif., USA is adequate. This implantation step affects the buried strap resistance and grain boundaries which in turn could cause recrystallization of the buried strap.

[0027] Typical working conditions are:

[0028] Phosphorus dose: 5×10¹³atoms/cm²

[0029] Energy: 10 KeV

[0030] Angle: 0°

[0031] The resulting structure is shown in FIG. 2E where the implanted region bears numeral 23.

[0032] Now referring to FIG. 2F, the active area is defined by a photolithography step. Surrounding the active area, the shallow isolation trench (STI) region is formed and filled with SiO₂and TEOS SiO₂materials to form layers 24 and 25. An anneal is performed to densify the TEOS material. These different thermal steps cause the dopants in region 23 to diffuse into region 20 which is part of the active area through the QCB layer 21 forming the “electrical” buried strap referenced 26 in FIG. 2F. The electrical buried strap 26 thus results of the merging of regions 20, 21 and 23. Electrical buried strap 26 spreads beyond the phosphorus doped region 20 formed with the previous angled implant as illustrated by the continuous line (vs the dotted line) in FIG. 2F. The QCB layer 21 is getting thinner (and sometimes may even disappear) with migration of dopants from region 23 and solid phase transformation of this region 23 into polycrystalline form.

[0033] In summary, the conventional buried strap and its QCB formation process described above in conjunction with FIGS. 2A-2F includes the six following basic steps.

[0034] 1. Forming the thermal SiO₂quantum conducting barrier layer 21.

[0035] 2. Depositing the undoped polysilicon layer 22.

[0036] 3. Polishing the polysilicon layer 22 down to the silicon substrate surface.

[0037] 4. Recessing the polysilicon layer 22 to 40 nm below the silicon substrate surface.

[0038] 5. Performing the vertical ion implantation of phosphorous dopants in polysilicon layer 22 to create region 23.

[0039] 6. Diffusing dopants of region 23 through the quantum conducting barrier layer 21 into region 20 during thermal oxide layer 24 and STI region 25 formation to create the electrical buried strap 26.

[0040] FIG. 3 is an enlarged view of structure 10 in the part which is encircled in FIG. 2F when the electrical buried strap 26 is defective. In this case, there is no electrical continuity between regions 20 and 23, the QCB layer 21 being either absent or destroyed. During the thermal steps of oxidation (to form the SiO₂layer 24) and anneal (to densify the TEOS material of the STI region 25), there is produced a local epitaxy phenomena which partially transforms the polysilicon of region 23 in monocristalline silicon as illustrated by region 23A in FIG. 3. This recrystallization creates slip lines 27 that propagate through the region 20 into the substrate bulk. Sometimes, the formation of a large polysilicon grain can occur next to the monocrystalline (single) region 20 at region 23A location which is highly resistive. Accordingly, in both cases, region 23A makes the buried strap defective.

[0041] The above described conventional buried strap and its QCB layer fabrication process solved serious reliability problems for 0.25 μm DRAM chips but still raises a severe concern for the next generations (0.2 μm and less groundrules). For these reduced scale devices, oxidizing the region 23/active area interface during the boat insertion into the LPCVD tool to form QCB layer 21 still generates a high VRT level and a high buried strap resistance because of the defects mentioned above by reference to FIG. 3. These defects occur because the thickness of the grown SiO₂of layer 21 is not well controlled and is not tunable in the manufacturing environment. A high buried strap resistance cause single cell fails (SCFs) which provide low temperature reliability fails (if the buried strap resistance is above 12 kOhms) which are added to VRT reliability fails. As the total reliability yield is the multiplication of them, it will become dramatic for these future generations of products. Moreover, before reliability test, pre fuse test showed out other fails due to low retention time and junction leakage along the deep trench and underneath the STI region 25 (referred to herein below as the sub-STI leakage). These failure mechanisms are shown in FIG. 4.

[0042] Now turning to FIG. 4, considering the profile A, the extremity of the buried strap 26 does not overlap the drain region 28 of IGFET 29, then a junction leakage occurs at top of the deep trench 14 and provides cell capacitor low retention time. This results of a limited diffusion of the buried strap 26 dopants which is supposed to be related to a QCB layer 21 too thick and/or not permeable enough to dopants. On the contrary, in the case of profile C, the buried strap dopant diffusion is too important, so that leakages along the deep trench 14 and under the STI region 25 occur. The leakage along deep trench 14 is due to a first parasitic NPN transistor created between the buried strap 26 and the buried plate bearing numeral 30 in FIG. 4. This defect is strongly dependent of the buried plate depth (nominal value 1.5 μm). On the other hand, the sub-STI region leakage is due to another parasitic NPN transistor created between two adjacent deep trenches because diffusion regions 20 of the two nearest deep trenches (DT's) are connected under the STI region 25. This defect is very sensitive to the shallow isolation trench depth (nominal value 0.26 μm). Profile C is related to a QCB layer 21 which is too thin and/or discontinued at the collar layer 17/18 top corner (labeled D in FIG. 4). Profile B shown in FIG. 4 is the right one which overcomes all the problems discussed above.

[0043] It is therefore a primary object of the present invention to provide improved methods of forming the buried strap and its quantum conducting barrier in deep trench cell capacitors wherein all the high temperature deposition steps are performed in-situ in the same CVD tool.

[0044] It is therefore a primary object of the present invention to provide improved methods of forming the buried strap and its quantum conducting barrier in deep trench cell capacitors that allows high productivity by increasing the number of wafers processed at each run.

[0045] It is therefore a primary object of the present invention to provide improved methods of forming the buried strap and its quantum conducting barrier in deep trench cell capacitors that allows manufacturing cost reduction by reducing the number of processing steps.

[0046] It is another object of the present invention to provide improved methods of forming the buried strap and its quantum conducting barrier in deep trench cell capacitors that reduces the chemical contamination from the atmosphere and undesired thermal oxidation effects as a result of a totally clusterized process.

[0047] It is another object of the present invention to provide improved methods of forming the buried strap and its quantum conducting barrier in deep trench cell capacitors that allows to place the dopants wherever desired in the buried strap with the adequate concentration.

[0048] It is another object of the present invention to provide improved methods of forming the buried strap and its quantum conducting barrier in deep trench cell capacitors which allows an accurate and total control of both the physical and electrical parameters thereof.

[0049] It is still another object of the present invention to provide multilayered quantum conducting barrier structures fabricated by these methods or other as well.

[0050] According to the present invention there are described methods of forming the buried strap and its quantum conducting barrier (QCB) in deep trench cell capacitors, wherein the QCB can be either of the single or multiple type. According to a first embodiment of the present invention there is described a method of forming a strap (BS) and its quantum conducting barrier (QCB) to make an electrical connection between two semiconductor regions having a different crystalline nature separated by a region of an insulating material comprising the steps of:

[0051] forming a thin continuous layer of undoped amorphous silicon to coat said regions;

[0052] forming a QCB layer onto the structure;

[0053] forming at least one dual layer comprised of an undoped amorphous silicon layer and a dopant monolayer onto the QCB layer to terminate the strap and its QCB; and,

[0054] heating the structure to activate the dopants in the strap to allow an electrical continuity between said semiconductor regions through the QCB by a quantum mechanical effect, wherein all these steps are performed in situ in the same CVD tool.

[0055] According to a second embodiment of the present invention there is described a method forming a strap (BS) and its quantum conducting barrier (QCB) to make an electrical connection between two semiconductor regions having a different crystalline nature separated by a region of an insulating material comprising the steps of:

[0056] forming a first QCB layer coating said polycrystalline and monocrystalline regions;

[0057] forming a thin continuous layer of undoped amorphous silicon to coat said regions;

[0058] forming a second QCB layer onto the structure;

[0059] forming at least one dual layer comprised of an undoped amorphous silicon layer and a dopant monolayer onto the QCB layer to terminate the strap and its QCB; and,

[0060] heating the structure to activate the dopants in the strap to allow an electrical continuity between said semiconductor regions through the QCB by a quantum mechanical effect, wherein all these steps are performed in situ in the same CVD tool.

[0061] For instance, they can be conducted by LPCVD with a cageless process. The material forming the QCB is silicon oxynitride, silicon nitride and the like. Nitride based materials can be deposited in thin films, so that they are better controlled than oxide based materials. The ion implantation step which created crystalline defects induced by ions collision is now eliminated. Arsenic is preferred to phosphorus as a dopant because of its slower migration through the QCB layer avoiding thereby parasitic transistors formation. Finally, the LPCVD cageless process permits to place the dopants in desired locations of the buried strap with the adequate concentration.

[0062] The novel features believed to be characteristic of this invention are set forth in the appended claims. The invention itself, however, as well as other objects and advantages thereof, may be best understood by reference to the following detailed description of an illustrated preferred embodiment to be read in conjunction with the accompanying drawings.

[0063] FIG. 1 shows the starting silicon structure at the initial stage of the buried strap fabrication process.

[0064] FIGS. 2A-2F show the structure of FIG. 1 undergoing the essential steps of a conventional buried strap fabrication process.

[0065] FIG. 3 is a cross section showing an enlarged view of a portion of the FIG. 2F structure after the buried strap has been fabricated and found defective.

[0066] FIG. 4 shows the IGFET/storage capacitor combination to point out the drawbacks that result of the conventional buried strap fabrication process.

[0067] FIGS. 5A-5D show the structure of FIG. 2 undergoing the essential steps of the improved buried strap fabrication process according to the present invention.

[0068] FIGS. 6A and 6B show the single Si—Si₃N₄QCB structure fabricated according to a first preferred embodiment of the methods of the present invention based on a LPCVD process before and after anneal to produce the electrical buried strap respectively.

[0069] FIGS. 7A and 7B show the double SiON—Si—Si₃N₄QCB structure fabricated according to another preferred embodiment of the methods of the present invention still based on a LPCVD process before and after anneal to produce the electrical buried strap respectively.

[0070] FIG. 8 shows the single Si—Si₃N₄QCB structure fabricated according to another further preferred embodiment of the methods of the present invention based on a SACVD process.

[0071] FIG. 9 shows the double SiON—Si—Si₃N₄QCB structure fabricated to another further preferred embodiment of the methods of the present invention still based on the SACVD process.

[0072] To fix defects related to the buried strap (recrystallization and high resistance) and to the QCB layer (junction and sub-DT leakages), Applicant's inventors have completely modified the conventional buried strap (BS) fabrication process described above to allow to cluster processing steps 1,2 and 5. This has been made possible by a number of process changes.

[0073] 1. A very thin continuous and homogeneous layer of undoped (intrinsic) amorphous silicon is deposited into the trench 14 (in reality, at this stage of the fabrication process, the trench is reduced to a recess still referenced 14 for sake of simplicity) to get rid of the discontinuity created by the collar layer 17/18 which separates monocrystalline silicon region 20 from the polysilicon fill 19.

[0074] 2. Then, the quantum conducting barrier (QCB) layer is formed by superficially nitridizing this amorphous silicon layer. The nature of the QCB material is thus changed. Instead of the thermally grown SiO₂material extensively used in the conventional BS fabrication process, the QCB material now is a nitride compound preferably formed by nitridization. Nitridization allows to form a thin film, the thickness of which is very well controlled unlike the SiO₂QCB layer 21 thickness which was uncontrollable because it was grown as a native oxide during a thermal step. As a result, because the new QCB layer is thinner, the resistive path therethrough is decreased.

[0075] 3. Next, the buried strap is formed in-situ by chemical vapor deposition (CVD). This step includes the deposition of at least one dual layer composed of an undoped amorphous silicon layer and a monolayer of arsenic atoms. The CVD deposition process eliminates the need of the ion implantation step which created crystalline defects induced by ions collision. On the other hand, to create such a monolayer, arsenic atoms are preferred to phosphorus atoms for doping the buried strap because they migrate slower through the quantum barrier layer. This avoids the formation of the two parasitic transistors mentioned above, and thus the sub-DT leakages. Moreover, this CVD process permits to locate the dopant in the buried strap to optimize the diffusion path in region 20.

[0076] The method of forming the buried strap according to the present invention will now be described in more details by reference to FIGS. 5A-5D, still starting with the FIG. 1 structure, now referenced 10′ to take into account the changes that will be brought up by the invention.

[0077] Now referring to FIG. 5A, a 100 A thick undoped amorphous silicon layer 31 is conformally deposited onto structure 10′ surface in a CVD reactor. This layer 31 forms a continuous and homogeneous film on all the contiguous regions and interfaces that are exposed in trench recess 14, ensuring thereby the continuity of the QCB layer that will be subsequently formed.

[0078] Now the QCB layer is formed by local nitridization of the silicon layer 31.

[0079] For instance, a Si₃N₄quantum conducting barrier layer 32 is formed by NH₃baking of the 100 A thick amorphous silicon of layer 31. The NH₃baking reaction is conducted at a temperature between 550° C. and 700° C. until the desired Si₃N₄QCB layer thickness is achieved, i.e. for a time which essentially depends on the equipment used. Typically, the thickness of nitride quantum barrier layer 32 is controlled to be in the 10-15 Å range. Note that the thickness (100 Å of amorphous silicon layer 31 is not thick enough for dislocation propagation. Preferred QCB materials are silicon oxynitride, silicon nitride and the like. These materials include stoichiometric multi-compounds which form more uniform and continuous films than single compounds on the plurality of contiguous regions 17/18, 19 and 20. Porosity and discontinuity are not permissible with regards to the desired QCB properties because they form nucleation sites for buried strap recrystallization and favor deep dopant diffusion which can create a parasitic bipolar transistor. The desired film continuity cannot be directly obtained on said continuous regions with the QCB layer 32 because it cannot be grown on the top of the collar layer 17/18 and it cannot be stoichiometric on region 20. However, if the QCB layer is grown on said contiguous regions, a second quantum barrier would become necessary to minimize these detrimental effects that are related to the collar layer 17/18.

[0080] Still in the same CVD reactor, the pyrolysis of SiH₄(Si atoms source) forms the intrinsic amorphous silicon layer 33A and the pyrolysis of AsH₃(As atoms source) forms the As monolayer 33B. It is important to remark that the arsenic atoms (which are preferred to phosphorus atoms) are deposited as a monolayer. The deposition of this dual intrinsic amorphous silicon/arsenic monolayer structure, generically referenced 33, can be repeated (33, 34, . . . ) as shown in FIG. 5A) until the desired doping that is finally expected for the buried strap is attained. Once the operation of depositing at least one dual layer is terminated, the remaining volume in the trench recess 14 is filled in excess with intrinsic amorphous silicon according to the same deposition technique to form layer 35. For sake of commodity, the pile of layers 33A, 33B, 34A, 34B, . . . which will subsequently form the electrical buried strap will be referred to herein below as the stack 36. For that deposition step, typical deposition temperatures range from 500° C. to 650° C. and pressures between 0.2 Torr and 200 Torr. Therefore, according to a significant aspect of the present invention, undoped amorphous silicon layer 31, Si₂N₄QCB layer 32 and stack 36 are formed in-situ in the same CVD reactor and during the same processing cycle (run). At this stage of the novel BS fabrication process, the structure is shown in FIG. 5A.

[0081] FIG. 5B shows resulting structure after CMP polish using Si₃N₄layer 13 as an etch stop layer.

[0082] Referring to FIG. 5C, structure 10′ is etched as described above in the prior art section, but in the present case all layers 31 to 35 forming the stack 36 are etched to recess the stack 40 nm below the silicon substrate 11 surface.

[0083] Referring to FIG. 5D, after a masking step, the STI region is etched, a TEOS layer is deposited and planarized as described above and annealed to densify the TEOS material. The remaining of stack 36 is now buried and the dopants contained therein activated. Diffusion region 20 is widened due to As atoms migration from monolayers 33B, . . . through Si₃N₄QCB layer 32, it must intersect with the IGFET diffusion region 29 to prevent junction leakage and it must have a depth less than 260 nm (see FIG. 4), because otherwise, sub DT leakages are formed along the collar layer 17/18 and under the STI region 25.

[0084] At the end of these processing steps, the electrical buried strap 37 is formed as resulting of the combination of regions 20, 31, 32 and 36.

[0085] The new electrical buried strap and its quantum conducting barrier process formation now includes four steps (instead of six in the conventional fabrication process) that are listed below.

[0086] 1. The Si₃N₄quantum conducting barrier and the buried strap formation is performed in-situ in the same CVD reactor (FIG. 5A).

[0087] 2. CMP polishing the intrinsic amorphous silicon layer 35 down the Si₃N₄pad layer 13 (FIG. 5B).

[0088] 3. Recessing the stack 36 to set its bottom 40 nm below the silicon substrate 11 surface (FIG. 5C).

[0089] 4. After processing steps not described here, oxidizing and annealing the structure 10′ to cause the arsenic atoms to diffuse through the Si₂N₄QCB layer 32 into region 20 (see FIG. 5D) to ensure an electrical continuity between contiguous regions 19 and 20 to create the electrical buried strap 37.

[0090] This in-situ global process step 1 has been made possible by adapting the baseline undoped polysilicon LPCVD VTR 7000+ reactor mentioned above to receive NH3 and AsH3 supplement gas lines and a 10 Torr baratron gauge. As the barrier is created inside the reactor, the use of the N₂load lock is now possible. Because no thermal native SiO₂growth can occur during boat insertion under N₂atmosphere, the extreme wafer positions in the boat are then allowed and the thickness of the nitridized QCB layer is now uniform wafer to wafer. Concerning the buried strap deposition, the number of dual layers (comprised of an amorphous undoped silicon layer and a monolayer of arsenic atoms) easily and accurately determines the buried strap doping level, and thus the chip performance. The arsenic monolayers permits to get a higher doping level than the one obtained by ion implantation and without generating crystalline defects, which are known to increase the buried strap internal resistance. Moreover, each arsenic monolayer acts as a barrier to buried strap recrystallization if there are located very close to region 20.

[0091] A major global benefit resulting from this in-situ process of fabricating the buried strap and its quantum conducting barrier is a huge improvement in terms of productivity. As a matter of fact, two process steps are suppressed and the batch size increases from 100 wafers to 150 wafers (as it will be shown in the practical example given below). Another advantage is to widen the manufacturing flexibility with the Q-time between BS pre clean and deposition steps increasing from 1 to 3 hours thanks to the N₂load lock. Still another advantage is the reduction of chemical contamination from the atmosphere and the elimination of any undesired reoxidation of the silicon surfaces which directly result of a totally clusterized process. Still another further advantage of this in-situ process is to allow a complete and accurate control of both the physical and electrical parameters of the buried strap and its quantum conducting barrier.

[0092] In the preferred embodiment, wafer batch processing based on A LPCVD process will be only considered. Let us give some practical examples of operating conditions when for instance the THERMCO VTR 7000 reactor mentioned above is used to fabricate a buried strap with different types of QCB structures. In this case, the boat pitch is 0.14 inch and the batch size is 150 wafers (instead of 100 in the conventional buried strap fabrication process).

[0093] Single Si—Si₃N₄QCB structure formation

[0094] 1. Formation of the undoped amorphous silicon (Si) layer 31

[0095] Q-time: 3 hours

[0096] Insert temp.: 550° C.

[0097] Insert time: 10 min

[0098] SiH₄flow: 260 cc/min

[0099] SiH₄pyrolysis temp.: 550° C.

[0100] SiH₄pressure: 0.45 Torr

[0101] SiH₄cycle 1 time: 4 min

[0102] N₂load lock: Yes

[0103] 2. Formation of the Si₂N₄QCB layer 32

[0104] Nitridization temp.: 550° C.

[0105] Nitridization pressure: 6 Torrs NH₃flow: 2000 cc/min

[0106] Stabilization (NH₃): 2 min

[0107] Nitridization time: 60 min

[0108] Gas evacuation: 10 min

[0109] 3. Formation of the buried strap stack 36

[0110] SiH₄pyrol. temp.: 550° C.

[0111] SiH₄Pressure: 0.45 Torr

[0112] AsH₃pyrol. temp.: 550° C.

[0113] AsH₃pressure: 0.5 Torr

[0114] SiH₄cycle 2 time: 13 min (formation of layer 33A)

[0115] AsH₃cycle 1 time: 10 min (″ ″ 33B)

[0116] SiH₄cycle 3 time: 25 min (″ ″ 34A)

[0117] AsH₃cycle 2 time: 10 min (″ ″ 34B)

[0118] SiH₄cycle 4 time: 153 min (″ ″ 35)

[0119] SiH₄flow: 260 cc/min

[0120] AsH₃flow (0.7% in H₂): 400 cc/min

[0121] Aver. silicon dep. rate: 15 /min

[0122] The total arsenic dose is 0.8 10¹⁵atoms/cm². The resulting structure is shown in FIG. 6A. It is important to point out that the illustrations of FIGS. 6A and 8 are not necessarily drawn to scale.

[0123] As apparent in FIG. 6A, the QCB 32 is shifted by about 8.5 nm from region 20. The characteristic of this Si₃N₄QCB layer after SIMS measurements is the nitrogen (N) level which is equal to 3.0×10¹⁵atoms/cm²with a dispersion of about 0.2 10¹⁵atoms/cm²for a batch of 150 wafers. This result strengthens the manufacturability of the in-situ global process.

[0124] 4. Formation of the electrical buried strap 37

[0125] During formation of region 24 and the anneal to densify the TEOS material of region 25, the electrical buried strap 37 is formed as illustrated in FIG. 6B.

[0126] Double SiON—Si—Si₃N₄QCB structure formation

[0127] Another type of QCB structure will be now described in conjunction with FIGS. 7A and 7B, to demonstrate that they are different ways of making an adequate electrical buried strap. A double SiON—Si—Si₃N₄QCB structure has given good results for current memory products. The first QCB is an oxynitride (SiON) layer due to the presence of native thermal SiO₂on regions 19 and 20 and the second one is a pure Si₃N₄layer because it is formed on a just deposited amorphous silicon layer. This involves very few modifications of the previous operating conditions as it will be made apparent from the following sequence.

[0128] 1. Formation of the 1st oxynitride (SiON) QCB layer 32A

[0129] Q-time: 3 hours

[0130] Insert temp.: 550° C.

[0131] Insert time: 10 min

[0132] Ramp-up time: 20 min (to 650° C. under NH₃)

[0133] Nitridization temp.: 650° C.

[0134] Nitridization time: 30 min(formation of layer 32A) Ramp-down time: 50 min (to 550° C. under NH₃)

[0135] 2. Formation of the 100 Å undoped polysilicon (Si) layer 31′

[0136] SiH₄pyrolysis temp.: 550° C.

[0137] SiH₄Pressure: 0.45 Torr

[0138] SiH₄flow: 260 cc/min SiH₄cycle 1 time: 4 min

[0139] 3. Formation of the 2nd Si₃N₄QCB barrier layer 32B

[0140] NH₃flow: 2000 cc/min

[0141] Nitridization temp.: 550° C.

[0142] Nitridization time: 30 min

[0143] Pressure: 6 Torr

[0144] 4. Formation of the buried strap stack 36

[0145] AsH₃pyrolysis temp.: 550° C.

[0146] AsH₃pressure: 0.5 Torr

[0147] SiH₄pyrol. temp.: 550° C.

[0148] SiH₄Pressure: 0.45 Torr

[0149] AsH₃cycle 1 time: 10 min (formation of layer 33B)

[0150] SiH₄cycle 2 time: 25 min (″ ″ 34A)

[0151] AsH₃cycle 2 time: 10 min (″ ″ 34B)

[0152] SiH₄cycle 3 time: 153 min(″ ″ 35)

[0153] The particularity of the structure shown in FIG. 7A is that there are two quantum conducting barrier layers. The first QCB layer 32A is formed directly onto monocrystalline region 20 at 650° C. (instead of 550° C.). The second QCB layer 32B is formed on layer 31′ at 550° C. The thin amorphous silicon layer 31′ thus separate the two QCB layers 32A and 32B by about 93 A. It is needed to conduct the second nitridization. In this example, the first As monolayer 33B is directly formed onto the 2sd QCB layer 32B and the second As monolayer is shifted from layer 32B by layer 34A thickness (could be shifted from 2sd QCB as well). The characteristic oxygen and nitrogen doses of this double SiON—Si—Si₃N₄QCB structure are:

[0154] O level (barrier 32A): less than 3×10¹⁵atoms/cm²typically equal to 1.2×10¹⁵atoms/cm².

[0155] N level (barrier 32A): between 1 and 3×10¹⁵atoms/cm²typically equal to 1.6×10¹⁵atoms/cm².

[0156] N level (barrier 32B): between 0.5 and 3×10¹⁵atoms/cm²typically equal to 0.8×10¹⁵atoms/cm².

[0157] 5. Formation of the electrical buried strap 37

[0158] After regions 24 and 25 formation, the electrical buried strap is fabricated. The As dose is 0.8 at/cm². As apparent in FIG. 7B, in the electrical buried strap 37, the frontiers with regions 19 and 20 are discontinued by N atoms segregation, so that QCB layer 32A is no longer efficient. The continuity is therefore ensured by the second QCB layer 32B. Advantageously, these two thin layers have the ability to prevent or slow diffusion of chemical species from one side of the layer to the other and to prevent or reduce transmission of forces associated with recrystallization from one side of the layer to the other. This type of structure could be a must for future memory product generations which will be more sensitive to recrystallization effects. However, it has a drawback which is the recovery time, i.e. the time lost to reduce the reactor temperature from 650 to 550° C. which is about 50 min and the contamination caused by this temperature change.

[0159] When a single wafer processing tool is used, most of the inconveniences recited above are eliminated. A SACVD Centura tool manufactured by APPLIED MATERIALS, Santa Clara, Calif., USA is adequate in all respects provided that some modifications are made to set the chamber with SiH₄, NH₃and AsH₃supply lines. Note that in this case, the notion of “stack 36” is not well adapted (because copyrolysis is used instead of sequential depositions), so that we will rather favor the term “layer 36” instead.

[0160] Single Si—Si₃N₄QCB structure

[0161] 1. Formation of the undoped amorphous silicon (Si) layer 31

[0162] Insert temp.: room temperature

[0163] Q-time: 3 hours

[0164] N₂load lock: Yes

[0165] Susceptor temp.: 600° C.

[0166] SiH₄flow: 500 cc/min

[0167] SiH₄pressure: 160 Torr

[0168] Deposition time: 10 s

[0169] 2. Formation of the QCB layer 32

[0170] Nitridization temp.: 650° C.

[0171] Nitridization pressure: 500 Torr

[0172] NH₃flow: 31/min Nitridization time: 15 s

[0173] Gas evacuation: 1 min

[0174] 3. Formation of the electrical buried strap layer 36′

[0175] SiH₄& AsH₃copyrol. temp.: 600° C.

[0176] SiH₄& AsH₃copyrol. press.: 160 Torr

[0177] SiH₄flow: 500 cc/min AsH₃flow (0.02% in H₂): 200 cc/min

[0178] Deposition time: 300 s

[0179] Deposition rate: 600 Å/min

[0180] The resulting structure is shown in FIG. 8.

[0181] After regions 24 and 25 formation, the electrical buried strap is the same as buried strap 37 depicted in FIG. 6A.

[0182] The main particularity of the SACVD Centura process is the copyrolysis of AsH₃and SiH₄instead of depositing a succession of dual amorphous silicon layer/As monolayer to form stack 36 (if several dual layers are deposited). This could be a disadvantage because the dopants are spread in the buried strap layer 36′ preventing them from having the barrier influence performed by the As monolayer to reduce strap recrystallization (see FIGS. 6A and 7A). The characteristic of this Si—Si₃N₄QCB structure after SIMS measurements is a N level of about 3×10¹⁵atoms/cm².

[0183] Double SiON—Si—Si₃N₄QCB structure

[0184] A similar multilayered structure as the one described above in conjunction with FIGS. 7A and 7B can be obtained with the Centura tool. Oxynitride and Si₃N₄are still the materials used to form the first and second QCB layers separated by a thin layer of undoped amorphous silicon. Now referring to FIG. 9, the double SiON—Si—Si₃N₄QCB structure is formed according to the following processing step sequence.

[0185] 1. Formation of the 1st oxynitride (SiON) layer 32A

[0186] Insert temp.: room temperature

[0187] Q-time: 3 hours

[0188] N₂load lock: Yes

[0189] Nitridization temp.: 650° C.

[0190] Nitridization pressure: 500 Torr

[0191] NH₃flow:

[0192] 31/min Nitridization time: 15 s

[0193] Gas evacuation: 1 mn

[0194] 2. Formation of the 100 undoped amorphous polysilicon (Si) layer 31′

[0195] Susceptor temp.: 600° C.

[0196] SiH₄Pressure: 160 Torr

[0197] SiH₄flow: 500 cc/min Deposition time: 10 s

[0198] 3. Formation of the 2nd Si₃N₄QCB layer 32B

[0199] Nitridization temp.: 600° C.

[0200] Nitridization pressure: 500 Torr

[0201] NH₃flow: 3/1 min

[0202] Nitridization time: 15 s

[0203] Gas evacuation: 1 min

[0204] 4. Formation of the electrical buried strap layer 36′

[0205] SiH₄& AsH₃copyrol. temp.: 600° C.

[0206] SiH₄& AsH₃copyrol. press.: 160 Torr

[0207] SiH₄flow: 500 cc/min AsH₃flow (0.02% in H₂): 200 cc/min

[0208] Deposition time :300 s

[0209] Deposition rate: 600 Å/min

[0210] As apparent in FIG. 9, the dopants are uniformly spread in buried strap layer 36′. SIMS measurements show no difference with results of the structure obtained by LPCVD described by reference to FIG. 7A. The drawbacks mentioned above with regards to the LPCVD process relating to the time necessary to change the temperature do not exist any longer, the ramp-up, ramp-down and deposition times are now very short. Obviously, such MQCB structures are well adapted to single wafer processing which is the future of the semiconductor industry. The reliability of reduced scale devices in deep trench cell capacitors is significantly increased by the use of quantum conducting barrier structures. QCB layers are thin enough to ensure a continuous conductive path between contiguous regions by a quantum mechanical effect and also act as a recrystallisation and diffusion barrier. The type of QCB structures of either type (single, double, . . . ) can vary to meet various device specifications and satisfy chip performance requirements. Their formation is driven by the different processing tools used and the working conditions thereof. Nitride based materials such as silicon oxynitride, silicon nitride and the like are adequate to prevent recrystallisation while maintaining the desired conduction characteristics. However, other materials could be envisioned, for instance, silicides formed still by in-situ CVD using chlorine or fluorine compounds. Conventional single thermal SiO₂—Si QCB structures are no more suitable for 0.2 μm DRAM chip because lack of electrical continuity and poor process robustness. The serial resistance of contiguous materials can be maintained very low only if the buried strap and its quantum conducting barrier are formed with an in-situ CVD deposition technique which does not create defects in said materials and allows to have very high dopant concentration and the desired electrical continuity. A high concentration level cannot been reached by ion implantation without creating crystalline defects. This global in-situ process offers the total control of what the IC manufacturer needs: reliability, low cost and customer satisfaction.

[0211] In essence, the purpose of this invention is thus the in-situ formation of the buried strap and its quantum conducting barrier wherein the buried strap is formed by in-situ doped polysilicon deposition. Only in-situ polysilicon doping permits to keep high IGFET and storage capacitor device performance at high level. Deep trench cell capacitors are extensively employed in EDO (extended data out), SDRAM (synchronous dynamic random access memory) and EDRAM (embedded DRAM) memory chips.

[0212] While the invention has been particularly described with respect to preferred embodiments thereof it should be understood by one skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.