Digital-analog current converter

[0002] The present invention relates to a current digital-analog converter. It can be applied especially to digital-analog sigma-delta type converters.

[0003] The present development of technologies is tending to shift the boundary between digital technologies and analog technologies in order to reduce the analog part to the maximum extent. This trend is designed especially to simplify the hardware architecture of systems by performing most of the functions in digital techniques while at the same time reducing manufacturing costs. A major consequence of this development is the huge increase in the constraints carried over to the analog-digital or digital-analog conversion part, since ultimately the converter is at the end or almost at the end of the processing chain. The converters must therefore comply with increasingly demanding performance requirements.

[0004] With regard to digital-analog converters, there are several types. Among these different types, the sigma-delta type converters are of considerable interest since they work with only one conversion bit.

[0005] In sigma-delta type converters, the binary signal encoded on N bits and sampled at a given frequency Fs is converted by digital means into an over-sampled one-bit signal, namely a signal sampled at a far higher frequency F's=MxFs. This signal is then converted into an analog signal by means of a one-bit digital-analog converter and a lowpass filter placed at output of the converter.

[0006] There are many known ways of making this type of digital-analog converter. It is possible to make a voltage converter, i.e. a converter where either a positive voltage at a potential +Vref or a negative voltage at a potential −Vref is sent at output, depending on the state of the binary signal. This structure however is limited in particular to a distortion level of about 60 dB and is sensitive to the instabilities, generally known as “Jitter”, in the reference clock. This jitter in particular prompts a parasite noise at the output of the converter.

[0007] Current converters are also made. In this case, either a positive current with a value +Iref or a negative current with a value −Iref is sent, depending on the state of the binary signal. These converters give very high distortion performance characteristics. However, they remain sensitive to the jitter of the clock.

[0008] There are also known ways of making switched-capacitor converters that are insensitive to the jitter of the clocks but they require very fast amplifiers to obtain efficient distortion performance levels.

[0009] An aim of the invention is to enable the making of a converter that ensures a high level of distortion and is insensitive to the jitter of the reference clock.

[0010] To this end, an object of the invention is a digital-analog current converter receiving, at input, a succession of bits of a binary signal and delivering, at output, sampled by a clock signal, a positive or negative current depending on the state of the input bit, wherein the converter comprises at least one circuit to control the build-up time of the output current of the converter, the build-up time being controlled by the charging of a capacitor by a constant current up to a reference voltage.

[0011] In a second embodiment, the circuit to control the build-up time of the output current comprises at least two reference voltages, the capacitor being charged and then discharged between these two voltages, the build-up time of the output current then being the sum of the time taken to charge the capacitor and the time taken to discharge the capacitor. An advantage of this embodiment is that it can be used to obtain high electrical efficiency.

[0012] In a third embodiment, the charging and discharging current of the capacitor is sent directly into the output load of the converter by means of selector switches and current mirrors. Two capacitors are used and are they are charged and discharged. While one of the capacitors gets charged, the other gets discharged. One advantage of this embodiment is that it can be used to overcome the current noise of the converter.

[0013] Other features and advantages of the invention shall appear from the following description made with reference to the appended drawings, of which:

[0014] FIG. 1 is a block diagram of the digital-analog sigma-delta type converter;

[0015] FIG. 2 is a block diagram of a digital-analog current converter;

[0016] FIG. 3 is a first possible embodiment of a control circuit of the charging duration of the output filter in a converter according to the invention;

[0017] FIG. 4 illustrates signals in play as a function of time and as a function of the clock signal in the above-mentioned circuit;

[0018] FIG. 5 is a second possible embodiment of a circuit to control the duration of charging the output filter in a converter according to the invention;

[0019] FIG. 6 illustrates signals in play as a function of the time t and as a function of the clock signal in the above-mentioned circuit;

[0020] FIG. 7 is another possible embodiment of a converter according to the invention;

[0021] FIG. 8 illustrates signals in play as a function of the time t and as a function of the clock signal in the above-mentioned circuit, bringing into play especially the shape of the current for charging the output filter.

[0022] FIG. 1 is a block diagram illustrating a sigma-delta type digital-analog conversion chain. This chain converts a digital signal V_Nencoded on N bits into an analog signal V_A. The signal V_Nis sampled at input of a sigma-delta converter 1 at a frequency Fs. This converter, whose mode of operation is well known, delivers a signal encoded on one bit that is over-sampled, i.e. the successive bits come out of the sigma-delta converter at a rate F's far greater than the input sampling frequency Fs, F's=MxFs. The output signal of the sigma-delta converter is then converted into an analog signal by means of a digital-analog converter 2 and then by a lowpass filter 3.

[0023] The working of a conversion chain of this kind can be described briefly. The parallel binary signal V_Nencoded on N bits is therefore converted by the sigma-delta converter 1 into a series signal conveyed on one bit. When the value of the input bit of the converter 2 is equal for example to 1, the converter delivers a voltage +Vref if it is a voltage type converter or a current +Iref if it is a current type converter. When the value of the bit is equal for example to 0, the converter delivers a voltage −Vref or −I_ref. This lowpass filter 3 placed at output of the digital-analog converter obtains a mean, in time, of the signals thus given by the converter. This mean is the result of the digital-analog conversion, namely the above-mentioned signal V_A.

[0024] FIG. 2 is a block diagram of a current digital-analog converter. At input, this converter receives a binary signal encoded on one bit. This signal is referenced y(k). This signal is given for example at output of a sigma-delta converter or any other conversion means for the conversion of an N bit parallel signal into a series signal. For example, the signal y(k) is successively the N bits y(0), . . . , y(k), . . . , y(N−1) of the parallel signal V_Nencoded on N parallel bits and to be converted into an analog value.

[0025] The converter illustrated by FIG. 2 has a first current source SC1 giving a current I_ref. This source is connected at input to a first supply terminal, for example a positive supply terminal. It is connected at output to a first switch T1 made out of a bipolar or MOS type transistor. The output of this first switch is connected to the input of a second switch T2 which too is based on a bipolar or MOS type transistor. The other terminal of the second switch is connected to a second current source SC2 furthermore connected to a second supply terminal at a potential below that of the first source SC1, for example the ground potential. The junction point of the two switches is connected to a lowpass filter, constituted for example by a resistor R_band a capacitor C_bthat are parallel-connected. The output S of the conversion chain is the junction point of the resistor and the capacitor, the other junction point of these elements being for example the ground potential. The first switch is controlled by the signal y(k) mentioned here above. It is not directly controlled by this signal but in combination with a clock signal H, the two signals being combined by a circuit 21 that performs a logic “and” operation between the two signals. The second switch is controlled by the conjugate signal y_b(k) of the previous one, again in combination with the clock signal H, by means of a logic circuit 22 performing a logic “and” operation between the two signals. The output of the logic circuits 21, 22, possibly amplified, then control the bases or gates of switch transistor T1, T2 depending on whether they are bipolar or MOS type transistors.

[0026] The converter then works as follows. If the bit y(k) is equal to 1, a current or a voltage occurs at the base or gate of the transistor T1 which is controlled so as to open when the clock signal H is set up. The current I_refgiven by the first current source SC1 goes into a lowpass filter R_bC_bthrough the transistor T1. At the same time, the bit y_b(k) is at 0. The transistor T2, since it has no control current or voltage, remains off in the closed state. When the bit y(k) is equal to 0, the operation is reversed. The transistor T1 is off in the closed state and the transistor T2 is controlled in the open state. In this case, the current I_refof the second current source goes into the lowpass filter through the transistor T2 when the clock signal H is set up. Seen from the filter, the current I_refis then reversed. It therefore has a value −I_refinstead of +I_refin the previous case.

[0027] A current converter of this kind, like a voltage converter, undergoes jitter from the clock H. To obtain both high distortion performance and clock insensitivity to jitter, the invention uses a digital-analog current converter to obtain a high distortion performance level and comprises means of time control during which the current is sent to the lowpass filter independently of the width of the clock signal H to overcome the jitter of this clock. This time is controlled by the charging or discharging of a capacitor with a constant current up to a reference voltage. The time is then equal to the time taken to discharge the capacitor. A limiting device known as a clamp blocks the voltage of the capacitor at the reference voltage.

[0028] FIG. 3 shows a first possible embodiment of a circuit for controlling the time of current injection into the output filter, namely in fact a circuit to control the current build-up time at output of the converter −I_refor +I_ref. This circuit has a capacitor C₀and a circuit for charging or discharging this capacitor. It therefore has a switch Q1 controlled by the clock signal H in such a way that Q1 is on when the clock signal is at 1 and off when the clock signal is at 0. An interface circuit controls the switch in current if it is a bipolar transistor or controls it in voltage if it is a MOS transistor by means of a clock signal H. The switch Q1 is connected between a positive supply terminal and a terminal of a current source SC1′ that gives a constant current I₀, the other terminal of this source being connected to another supply terminal, for example the ground potential. A capacitor C₀, known as a clamp capacitor, is wired between, firstly, the junction point of the switch Q1 and the current source SC1′ and, secondly, the ground potential. When this switch Q1 is on, namely when it is in the presence of the clock signal H, the current I₀goes into the switch Q1. When this switch Q1 is off, the current I₀charges the capacitor C₀. The voltage Vc at the terminals of this capacitor then decreases from a zero value as shown in FIG. 4.

[0029] FIG. 4 illustrates the different signals in play as a function of the time t and as a function of the clock signal H. This signal is a binary signal illustrated by a curve 41. The second curve 52 represents the voltage Vc at the terminals of the capacitor C₀. On the leading edge 59 of the clock signal, the capacitor starts getting charged at constant current −I₀, from the voltage 0. It thus gets charged until its voltage reaches a value −V₀known as the clamp voltage.

[0030] Indeed, a circuit limits the voltage Vc to a minimum value −V₀which is the reference voltage. This circuit has an operational amplifier 32 whose positive input is connected to a potential with a value −V₀and whose negative input is connected to the emitter of a PNP transistor Q4, this emitter being connected to the junction point of the current source, the capacitor C₀and the switch Q1. The base of the transistor Q4 is controlled by the output of the operational amplifier 32 and its collector is connected to the positive supply terminal. When the voltage Vc reaches the value known as the clamp value of −V₀, the output of the operational amplifier delivers a positive voltage that controls the transistor Q4 in the on state, this transistor being previously off. The current I₀is then deflected by Q4, the capacitor then remaining charged at the voltage value −V₀, which is illustrated by a second curve 52 in FIG. 4. When the switch Q1 becomes on, the voltage Vc again becomes equal to the voltage at the terminals of the current source SC1′, namely substantially zero.

[0031] A third curve 53 illustrates the charging current I₀of the capacitor as a function of the time t. The build-up time of this current is perfectly controlled by the charging duration of the capacitor C₀illustrated by the progress of the voltage between 0 and −Vc. This duration is independent of the jitter of the clock H and may thus be used to control the switches T1, T2 of the converter, like that of FIG. 2 for example. For this purpose, it is planned to have a shaping circuit that creates a logic signal whose duration is equal to the charging time of the capacitor C₀. This signal then controls the switches T1, T2 in combination with the signals y(k) and y_b(k) to replace the clock signal H itself. Other means may be planned to obtain the width of output current of the converter I_refequal to the discharge time of the capacitor C₀.

[0032] The exemplary embodiment of a circuit to control the build-up time of the output current of the converter works on the basis of the discharge time of the capacitor C₀. It is of course possible to obtain a device of this kind through the charging of the capacitor C₀. In either case, the sign of the current I₀in the capacitor changes.

[0033] The time T_0nduring which the transistors T1, T2 are controlled, which is also the discharge time of the capacitor C₀, is given by the following relationship: $\begin{array}{cc}{T}_{\mathrm{on}}=\frac{C_0{V}_0}{I_0}& \left(1\right)\end{array}$

[0034] The charge injected into the output filter R_bC_bduring a clock period T is: $\begin{array}{cc}Q=\frac{I_{\mathrm{ref}}{V}_{\mathrm{ref}}{C}_0}{I_0}& \left(2\right)\end{array}$

[0035] The efficiency is relatively low because the charging of the output filter is done only during the period Tc for charging the capacitor C₀which may be low as compared with the period T. Tc for example may be in the range of T/4.

[0036] FIG. 5 illustrates a second possible embodiment of a circuit to control the injection time of the current, which improves the efficiency. In this embodiment, two reference voltage values are used and the capacitor is charged and discharged between these two voltages also known as clamp voltages. The time during which the converter sends the current I_refat output, into the load, is then the sum of the time taken to charge the capacitor and the time taken to discharge the capacitor. The current I_refof the converter can furthermore be divided by two as compared with the above cases with the same packet of charges sent at output.

[0037] The circuit comprises a charging and discharging circuit of the capacitor C₀with two reference voltages. It therefore has, in series, a first current source SC1′ connected to a supply terminal, a first switch Q1, a second switch Q2 and a second current source SC2′ connected to a second supply terminal, for example the ground potential. The switches are for example bipolar transistors or MOS type transistors. The two current sources deliver a current I₀. The first switch Q1 is controlled by the clock signal H and the second switch Q2 is controlled by the conjugate of the clock signal H_b. A capacitor C₀is connected between the junction point of the two switches Q1, Q2. The signal EN present at this capacitor C₀replaces the signal H combined with the bits y(k), y_b(k) at input of the converter as illustrated by FIG. 2.

[0038] When the clock signal H is at 1, namely when it is present, the capacitor C₀gets charged at constant current I₀. Indeed, in this case, the transistor Q1 is on and the transistor Q2 is off. The voltage Vc at the terminals of the capacitor C₀therefore increases linearly. When the clock signal H is at 0, the signal H_bis at 1 and the capacitor gets discharged at constant current I₀through the second switch Q2. The voltage Vc at the terminals of the capacitor therefore decreases linearly. Two circuits limit this voltage Vc, one to a maximum value V₀and the other to a minimum value −V₀. The V₀limiting circuit is constituted for example by an operational amplifier 31 and a PNP bipolar transistor Q3. The positive input of the operational amplifier 31 receives the voltage V₀and its negative input is connected to the emitter of the transistor Q3 which is furthermore connected to the junction point of the two switches Q1, Q2. The output of the operational amplifier controls the base of the transistor Q3 whose source is connected to the second supply terminal, for example the ground potential. When the voltage Vc at the terminals of the capacitor C₀, which is also the voltage present at the negative input of the operational amplifier, reaches the value V₀, the output of the amplifier gives a base current to the transistor Q3 which then shunts the current I₀that continues to be given by the first source SC1′ through the switch Q1 during the remaining time when the clock H is in the 1 state. The −V₀limiting circuit is for example formed by an operational amplifier 32 and an NPN bipolar transistor Q4. The positive input of the operational amplifier 32 receives the voltage −V₀and its negative input is connected to the emitter of the transistor Q4 which is furthermore connected to the junction point of the two switches Q1, Q2. The output of the operational amplifier controls the base of the transistor Q4 whose collector is connected to the first supply terminal which is the positive supply terminal. When the voltage Vc at the terminals of the capacitor C₀, which is also the voltage present at the negative input of the operational amplifier, reaches the value −V₀, the output of the amplifier gives a base current to the transistor Q4 which then shunts the current I₀that continues to be given by the second source SC2′ through the switch Q2 during the remainder of the time when the clock H is in the 0 state.

[0039] FIG. 6 illustrates the different signals in play as a function of the time t and as a function of the clock signal H. The latter signal is a binary signal illustrated by a curve 41. A second curve 42 represents the voltage Vc at the terminals of the capacitor C₀. On the leading edge 49 of the clock signal, the capacitor begins to get charged at a constant current I₀, from the voltage −V₀. It gets charged until its voltages reaches the value V₀. The voltage Vc remains clipped at V₀for the rest of the time when the clock signal is in the 1 state. During the time Tc for the charging of the capacitor, the charging current of this capacitor is I₀. This current is zero for the rest of the clock signal H.

[0040] On the trailing edge 48 of the clock signal H or on the leading edge of its conjugate signal H_b, the capacitor starts getting discharged at constant current I₀from the voltage V₀. It gets discharged until its voltage reaches the value −V₀. The voltage Vc remains at −V₀for the rest of the time when the clock signal is in the 0 state. During the time Tc for charging the capacitor, the charging current of this capacitor is −I₀. This current is zero once the value −V₀is reached. A curve 43 illustrates the shape of the current I₀.

[0041] A binary signal EN can be created by known means from the voltage Vc at the terminals of the capacitor C₀. The width of this signal is equal to the width of the build-up time of the voltage Vc. In other words, at each build-up of the voltage Vc, the signal EN is equal to 1 and outside it is equal to 0. It is the signal EN that is combined with the bits y(k) and y_b(k) at input of the converter as illustrated for example by FIG. 2, instead of the clock signal H. As the case may be, the signal EN may also be equal to 1 during the drop in the voltage Vc.

[0042] The duration T_onfor charging the capacitor C₀is given by the following relationship: $\begin{array}{cc}{T}_{\mathrm{on}}=\frac{2C_0{V}_0}{I_0}& \left(3\right)\end{array}$

[0043] This time is also the time when the switches T1, T2 of the converter are controlled. It is independent of the jitter of the clock H.

[0044] The charge Q injected during a clock period T is: $\begin{array}{cc}Q=\frac{2I_{\mathrm{ref}}{V}_{\mathrm{ref}}{C}_0}{I_0}& \left(4\right)\end{array}$

[0045] The efficiency is therefore improved as compared with a circuit of the type shown in FIG. 3.

[0046] With regard to the noise of the converter which is a function of the variation in charge dQ injected into the output filter R_b, C_bof the conversion chain, it is substantially zero. For the standard converter, the charge Q injected is given by the following relationship:

[0047] Q=(I_ref+dI_ref)×(T+dT)  (5)

[0048] where T represents the time taken to charge the capacitor C_bof the filter at output of the converter.

[0049] The variation in charge dQ is therefore given by the following relationship:

[0050] dQ=dI_ref×T+I_ref×dT  (6)

[0051] In one converter according to the invention, T is perfectly controlled and equal to T_on, therefore dT=0. The remaining noise is only due to the current noise dI_ref.

[0052] FIG. 7 shows another possible embodiment of a converter according to the invention. In this embodiment, the charging and discharging current of the clamp capacitor C₀is sent directly into the output load, namely into the output filter R_bC_b, by means of switches and current mirrors. Then, two control circuits of the type shown in FIG. 5, cabled in differential mode, are used. This is known as the differential double clamp method. These two circuits are used with two clamp capacitors that are charged and discharged.

[0053] While one of the capacitors gets charged, the other gets discharged. One advantage of this embodiment is that it can be used to overcome the current noise dI_refof the converter.

[0054] The current charging time control circuit therefore has a pair of differential circuits. More specifically, it has two parallel arms each with a capacitor and a circuit for charging and discharging this capacitor at constant current of the type shown in FIG. 5 but controlled in phase opposition. The current sources SC1′, SC2′ are for example common to the two circuits.

[0055] Thus, since the first circuit is identical to that of FIG. 5, the second circuit comprises, in series with the first current circuit SC1′, a first switch Q1′. A second switch Q2′ is series-connected with the second current source SC2′. The switches are for example bipolar transistors or MOS type transistors. The first switch Q1′ is controlled by the conjugate clock signal H_bwhile the switch Q1 is controlled by the clock signal H. Similarly, the second switch Q2′ is controlled by the clock signal H while the switch Q2 is controlled by the clock signal H_b. In this sense, the two circuits of the differential pair are controlled in phase opposition by means of the clock signal H. A capacitor C′₀is connected between the junction point of the two switches Q1′, Q2′. This capacitor C′₀is for example equal in value to the capacitor C₀of the first circuit.

[0056] Two circuits limit the voltage Vc at the terminals of the capacitor C′₀, one to a maximum value V₀and the other to a minimum value −V₀. The V₀limiting circuit is constituted for example by an operational amplifier 31′ and a PNP bipolar transistor Q3′. The positive input of the operational amplifier 31′ receives the voltage V₀and its negative input is connected to the emitter of the transistor Q3′ which is furthermore connected to the junction point of the two switches Q1′, Q2′. The output of the operational amplifier controls the base of the transistor Q3′ whose source is connected to the second supply terminal, for example the ground potential. When the voltage Vc at the terminals of the capacitor C′₀, which is also the voltage present at the negative input of the operational amplifier, reaches the value V₀, the output of the amplifier gives a base current to the transistor Q3′ which then shunts the current I₀that continues to be given by the first source SC1′ through the switch Q1′ during the remaining time when the clock H is in the 1 state. The −V₀limiting circuit is for example formed by an operational amplifier 32′ and an NPN bipolar transistor Q4′. The positive input of the operational amplifier 32′ receives the voltage −V₀and its negative input is connected to the emitter of the transistor Q4′ which is furthermore connected to the junction point of the two switches Q1′, Q2′. The output of the operational amplifier controls the base of the transistor Q4′ whose collector is connected to the first supply terminal which is the positive supply terminal. When the voltage V′c at the terminals of the capacitor C′₀, which is also the voltage present at the negative input of the operational amplifier, reaches the value −V₀, the output of the amplifier gives a base current to the transistor Q4′ which then shunts the current I₀that continues to be given by the second source SC2′ through the switch Q2′ during the remainder of the time when the clock H is in the 0 state.

[0057] The two clamp capacitors C₀, C′₀are each connected to a virtual ground potential. In other words, the terminal of the capacitor C₀or C′₀not connected to the junction point of the switches Q1, Q2 or Q1; Q2′ is connected to a potential that is automatically linked to the value of 0 volts. The function of this automatically controlled potential will be explained further below in the description.

[0058] Since the two circuits of the differential pair are controlled in phase opposition as indicated here above, when the capacitor C₀of the first circuit gets charged, the capacitor C′₀of the second circuit gets discharged. FIG. 8 illustrates this situation. Like the FIGS. 4 and 6, this figure illustrates different signals in play as a function of the time t and as a function of the clock signal H. A first curve 41 again illustrates the shape of the clock signal H as a function of the time t. A second curve 82 illustrates the shape of the voltage Vc at the terminals of the capacitor C₀and a third curve illustrates the shape of the voltage V′c at the terminals of the capacitor C′₀. Whereas the capacitor C₀gets charged from the leading edge 49 of the clock signal, the capacitor C′₀gets discharged. The situation is reversed starting with the trailing edge 48 of the clock signal H.

[0059] A fourth curve 84 illustrates the current Ic in the capacitor C₀and a fifth curve 85 illustrates the current l′c in the capacitor C′₀. The two currents are in phase opposition. When the capacitor C₀gets charged, its current Ic is equal to I₀and the current l′c which goes into the capacitor C′₀which gets discharged is then −I₀, and vice versa. The current Ic corresponds to the current Ic of FIG. 6, namely the charging current of the capacitor C₀of FIG. 5.

[0060] The output filter R_bC_bis still supplied with the current I_ref, the output S of the filter being the output of the conversion chain, in practice the output of the digital-analog converter. In the exemplary embodiment shown in FIG. 7, the output current I_refis the current for charging and discharging the capacitors C₀, C′₀. The time taken for the charging of the filter by the current I_refor −I_refis therefore perfectly defined by the control of the charging duration of the capacitors C₀, C′₀. The charging and discharging current of the capacitors is for example sent to the output filter by means of switches and current mirrors, in passing through the potential point automatically linked to a virtual ground.

[0061] The circuit used to bring the potential to 0 has for example an operational amplifier 71, 71′ whose positive terminal is connected to a potential V_Gequal to 0 volts and whose negative terminal, which is the automatically controlled potential, is connected to the terminal of the capacitor C₀, C′₀.

[0062] On the first control circuit side, an NPN bipolar transistor Q5 connects the terminal of the capacitor C₀to a first pair of switches T1, T2. The collector of the transistor Q5 is thus connected to a junction point of the two switches, the other terminal of the switch T1 being connected to a first current mirror and the other terminal of the switch T2 being connected to a positive supply terminal. The emitter of the transistor Q5 is connected to the capacitor C₀. The base of the transistor Q5 is controlled by the output of the operational amplifier 71.

[0063] Similarly, a PNP transistor Q6 connects the terminal of the capacitor C₀to a second pair of switches T3, T4. The collector of the transistor Q6 is thus connected to the junction point of the two switches, the other terminal of the switch T3 is connected to the ground potential and the other terminal of the switch T2 is connected to the second current mirror. The emitter of the transistor Q6 is connected to the capacitor C₀. The base of the transistor Q6, like that of the transistor Q5, is controlled by the output of the operational amplifier 71.

[0064] The two pairs of switches are controlled by the binary signal y(k) and its conjugate y_b(k). The switch T1 is controlled in the on state when the signal y(k) is at 1, the switch T2 is controlled in the on state when the signal y_b(k) is at 1, the switch T3 is controlled in the on state when the signal y(k) is at 1, and the switch T4 is controlled in the on state when the signal y_b(k) is at 1.

[0065] On the second control circuit side, an NPN bipolar transistor Q5′ connects the terminal of the capacitor C₀to a first pair of switches T1′, T2′. The collector of the transistor Q5′ is thus connected to a junction point of the two switches, the other terminal of the switch T1′ being connected to a first current mirror and the other terminal of the switch T2′ being connected to a positive supply terminal. The emitter of the transistor Q5′ is connected to the capacitor C₀. The base of the transistor Q5′ is controlled by the output of the operational amplifier 71′.

[0066] Similarly, a PNP transistor Q6′ connects the terminal of the capacitor C₀to a second pair of switches T3′, T4′. The collector of the transistor Q6′ is thus connected to the junction point of the two switches, the other terminal of the switch T3′ is connected to the ground potential and the other terminal of the switch T2′ is connected to the second current mirror. The emitter of the transistor Q6′ is connected to the capacitor C₀. The base of the transistor Q6, like that of the transistor Q5′, is controlled by the output of the operational amplifier 71′.

[0067] The first current mirror has for example two PMOS transistors whose gate is connected to the switches T1, T1′ and whose source is connected to the positive supply terminal. The drain of one of the two transistors Q7 is connected to the switches T1, T1′. The second current mirror has for example two NMOS transistors whose gate is connected to the switches T3, T3′ and whose source is connected to the ground potential. The drain of one of the two transistors Q9 is connected to the switches T3, T3′. The drain of the other transistor Q10 is connected to the drain of the transistor Q8 of the first current mirror. The junction point of these two transistors Q8, Q10 is connected to the input of the output filter R_b, C_b. This output filter is therefore charged by the output of the drains of the transistors Q8, Q10, namely by the output of the current mirror.

[0068] The two pairs of switches are controlled by the binary signal y(k) and its conjugate y_b(k) and in the same way.

[0069] When the capacitor C₀gets charged at the current I₀, this current goes into the transistor Q6. The transistor Q5 is then turned off by the voltage Vbe of this transistor. Similarly, the transistor Q5′ is on and the transistor Q6′ is off because the capacitor C′₀gets discharged. Two cases can then arise depending on whether the signal y(k) is in the 1 state or in the 0 state.

[0070] If this signal y(k) is at 1, the current Ic going through the transistor Q6 is shunted by the switch T3 to the ground potential and the current l′c going through the transistor Q5′ is shunted by the transistor T1′ from the transistors Q7, Q8 of the first current mirror. The two transistors Q7, Q8 controlled with the same gate source voltage then conduct the same current. To this end, the virtual ground potential V_Genables the passage of the charging current Ic into the current mirror. Since the current Ic is imposed on the transistor Q7, the transistor Q8 also conducts this current. The current given by this transistor Q8 is the current I_refgiven to the output filter. It is positive and for example has a value I₀.

[0071] If the current y(k) is at 0, the current Ic going through the transistor Q6 is shunted by the transistor T4 to the second current mirror while the current l′ c that flows into the transistor Q5′ is shunted from the positive supply. The two transistors Q9, Q10 of the current mirror controlled by the same gate-source voltage conduct the same current with a value I₀. The output filter is then discharged by this current which flows into the drain of the transistor Q10. In this case, the charging current of the input filter I_refis negative, for example with a value of −I₀.

[0072] When the capacitor C₀gets discharged at the current I₀, this current flows into the transistor Q5. The transistor Q6 is then turned off by the voltage Vbe of this transistor Q5. Similarly, the transistor Q6′ is on and the transistor Q5′ is off because the capacitor C′₀gets charged. The same two cases as above can therefore occur.

[0073] If the signal y(k) is at 1, the current I′c flowing through the transistor Q6′ is shunted by the switch T3′ to the ground potential and the current Ic flowing through the transistor Q5 is shunted by the transistor T1 from the transistors Q7, Q8 of the first current mirror. The two transistors Q7, Q8 controlled with the same gate-source voltage then conduct the same current. Since the current Ic is imposed on the transistor Q7, the transistor Q8 also conducts this current. The current given by the transistor Q8 is the current I_refgiven to the output filter. It is positive and for example has a value I₀.

[0074] If the signal y(k) is at 0, the current Ic flowing through the transistor Q6′ is shunted by the transistor T4′ to the second current mirror while the current Ic that flows in the transistor Q5 is shunted from the positive supply. The two transistors Q9, Q10 of the current mirror controlled by the same gate-source voltage conduct the same current with a value 10. The output filter is then discharged by this current which flows into the drain of the transistor Q10. In this case, the current for the charging of the input filter I_refis negative, for example with a value of −I₀.

[0075] Thus, when the bit y(k) is at 1, the current I_refcharges the input filter, whether the capacitors C₀, C′₀get charged or discharged. Similarly, when the bit y(k) is at 0, the current in the output filter is −I_ref. The charging duration of the current I_refor −I_refin the filter is perfectly controlled by the charging or discharging duration of the capacitors C₀, C′₀.

[0076] The last two curves 86, 87 in FIG. 8 illustrate this result. A curve 86 gives an example of a sequence of values y(k) and a curve 87 gives the current Is at output of the output filter of the converter as a function of the bits y(k). The time taken to control the charging and discharging of the capacitors C₀, C′₀are such that there is for example at least one charging of the capacitor C₀and one discharging of the capacitor C′₀between the arrival of two successive bits y(k) at input of the converter. When a bit y(k) is at 1, there are then two successive positive current pulses 90, 91 at the output filter. Of these two pulses, the first corresponds to the current I′c for charging the capacitor C′₀and the second to the current Ic for charging the capacitor C₀. When the bit y(k) is in the 0 state, there are two successive negative current pulses 92, 93 at the output filter. Of these two pulses, the first corresponds to the current Ic for charging the capacitor C₀and the second to the current I′c for charging the capacitor C′₀.

[0077] The exemplary digital-analog converter illustrated in FIG. 7 has the advantage especially of having high efficiency as shown in FIG. 5 for the same reasons. It furthermore makes it possible to overcome the noise of the current sources dI_ref. This current noise induces a corresponding electric charging noise dQ which is given by the following relationship: $\begin{array}{cc}\mathrm{dQ}={\mathrm{dI}}_{\mathrm{ref}}{T}_{\mathrm{on}}=\frac{2{\mathrm{dI}}_{\mathrm{ref}}{C}_0{V}_0}{I_0}& \left(7\right)\end{array}$

[0078] according to the relationship (3) for the duration T_onof two pulses. For the duration of one current pulse I_ref, the noise is given by: $\begin{array}{cc}\mathrm{dQ}=\frac{{\mathrm{dI}}_{\mathrm{ref}}{C}_0{V}_0}{I_0}& \left(8\right)\end{array}$

[0079] Furthermore, the electrical charge Q sent to the output filter during a pulse is perfectly controlled by what is called the clamp voltage V₀and by what is called the clamp capacitance C₀. As is well known, it is equal to C₀V₀. It follows therefore that dQ is zero. In fact, given that dI_refexists and that its value is not zero, the time T_onor T_on/2 during which the current is sent gets adjusted as a function of the noise of the current I₀since this time T_onis precisely a function of I₀as recalled above in the relationship (3).

[0080] In fact: $\begin{array}{cc}\frac{d{V}_0}{dt}=\frac{\left(I_0+{\mathrm{Ib}}_0\right)}{C_0}& \left(9\right)\end{array}$

[0081] where Ib₀is the current noise superimposed on I₀. T_ongets adjusted so that: $\begin{array}{cc}{V}_0={\int }_0^{T_{\mathrm{on}}}\frac{\left(I_0+{\mathrm{Ib}}_0\right)}{C_0}dt& \left(10\right)\end{array}$

[0082] through the clamp circuit.

[0083] Given that $\begin{array}{cc}Q=2{\int }_0\left(I_0+{\mathrm{Ib}}_0\right)dt& \left(11\right)\end{array}$

[0084] It follows that

[0085] Q=2C₀V₀and therefore that dQ=0.

[0086] The switches may be bipolar transistors or MOS type transistors. Similarly, the other transistors used in the control circuit for the build-up time of the current may be bipolar or MOS type transistors. These transistors are NPN, PNP, NMOS, PMOS depending on the polarities in play according to the knowledge of those skilled in the art.