Super self-aligned bipolar transistor and method for fabricating thereof

[0002] 1. Field of the Invention

[0003] The present invention relates to a super self-aligned heterojunction bipolar transistor and method for manufacturing thereof using a Si/SiGe heterojunction base layer.

[0004] 2. Description of Prior Art

[0005] In general, even if the prior art element has an improved operating speed in proportion to miniaturization of a homojunction bipolar transistor, since, to accomplish this, impurity concentration between emitter and base are increased, enhancement of characteristics thereof based on a structure of such element is a difficult task. A heterojunction bipolar transistor to cope with the above disadvantage has been proposed.

[0006] Such a heterojunction bipolar transistor has a characteristic that energy bandgap of an emitter is larger than that of a base. For this reason, utilization of the heterojunction bipolar transistor showed an improvement in the performance of the element and various design effects in comparison to the homojunction bipolar transistor. In addition, in the manufacturing process associated with the homojunction bipolar transistor previously described, a method of decreasing the energy bandgap by adding germanium to a base layer composed of silicon has been developed.

[0007] As a conventional homojunction silicon bipolar transistor, the prior art heterojunction bipolar transistors utilize a polysilicon thin film as both a base electrode and an impurity diffusion source for the emitter. Thus, using Ge instead of Si on the base layer, a difference between an energy bandgap of the emitter and that of the base is incurred to increase emitter implantation efficiency, then the base is grown to a high doping concentration ultra-thin film, thereby enhancing a current gain and a switching speed of element.

[0008] Recently, in order to optimize and miniaturize the structure of the element, various methods have been used to minimize several parasitic components such as a base resistance at an active region of the element and parasitic capacity between a collector and a base.

[0009] Examples of such various methods include a trench isolation, a local oxidation of silicon (“LOCOS”), a selective epitaxial growth(“SEG”) of a SiGe thin film, and a selective epitaxial growth of a Si emitter and so on.

[0010] Using the above methods, a super self-aligned Si/SiGe heterojunction bipolar transistor is being developed, which is self-aligned between base and emitter to reduce a base parasitic resistance, or self-aligned both between base and emitter, and between collector and base.

[0011] The LOCOS has a disadvantage in that since a bird's beak is horizontally formed as much as the thickness of silicon thermal oxidation film which is vertically formed, there is a limit in geometrically reducing the transistor.

[0012] There are shown in FIG. 1 an exemplary super self-aligned Si/SiGe heterojunction bipolar transistor which is directed to using the SEG method without using the LOCOS method.

[0013] Referring now to FIG. 1, an n⁺ buried silicon collector layer (1-2), which has a high doping concentration, is first formed on a p-type silicon substrate (1-1), and an n− silicon collector layer (1-3), which has a low doping concentration, is then grown on the buried collector layer (1-2).

[0014] Subsequently, a collector junction portion (1-4) is formed by implanting an n-type impurity ion thereon, and then a trench to isolate between elements is formed by a dry etching method, and, in turn, filling therein with Boron Phosphorous Silica Glass(“BPSG”) insulating thin film (1-5) made of boron and phosphorous. The BPSG insulating thin film (1-5) is then flattened under a high pressure.

[0015] In an ensuing step, an insulating film (1-6), a P⁺ polysilicon film (1-7), an insulating film (1-8) and a side-wall insulating film (1-9) are formed by depositing and etching methods as shown in FIG. 1, and an n-type collector region (1-10) for enhancing characteristics of elements in a high current region is then formed by selective ion implantation to only an active region of the element.

[0016] In a subsequent step, a SiGe base layer (1-11) is selectively grown on only an exposed portion in the collector region (1-10) and the polysilicon film (1-7), through the use of gas source molecular beam technique, and then a polysilicon film (1-12) is selectively grown on the remaining space, thereby accomplishing a junction between the polysilicon film (1-7) for a base electrode and the SiGe base layer (1-11).

[0017] Accordingly, self-alignment between the collector and the base can be performed, since a parasitic capacity region formed between the collector and the base is not defined as a photoresist and is limited only to a portion of a polysilicon thin film (1-12).

[0018] Since, however, the parasitic capacity region defined by the polysilicon thin film (1-12) is determined from a horizontal wet etching for the insulating film (1-6), resulting in the degradation of efficiency of process in terms of uniformity and reproduction aspects, thus entailing the fatal degradation of the performance of element.

[0019] In addition, the prior art method has a disadvantage that since the low speed selective epitaxial growth method is applied two times during the growth of the SiGe base layer (1-11) and the polysilicon thin film (1-12), and two thin films for example, the SiGe base (1-11) and the polysilicon (1-12), are used during the growth process thereof, resulting in a complicated manufacturing process, and further even if the polysilicon thin film (1-12) is slightly grown on the base layer (1-11), it is possible to cause the fatal degradation of element performance, thereby making it difficult to control the process thereof. Thus, with the prior art method it is difficult to accomplish an effective manufacturing process and a simplified processing step.

[0020] Furthermore, as shown in FIG. 1, the prior art method has a shortcoming in that a trench structure for isolating between elements should be deeply formed so as to prevent the collector junction portion (1-4) from contacting between elements via the n⁻ collector thin film (1-3) on the n⁺ buried Si collector layer (1-2) formed at the entire surface of a substrate, resulting in a larger space requirement to be filled with the insulating thin film (1-5), thus entailing a bulkier element.

[0021] Turning now to FIG. 2, there is presented a cross-sectional view of a Si/SiGe heterojunction bipolar element manufactured by another method previously described, after the growth of a base thin film. In the prior art exemplary shown in FIG. 2, both of the base and the collector thin films are grown through the use of the SEG method in contrast with the trench structure previously described, to thereby accomplish a simplified and an integrated manufacturing process.

[0022] As shown in FIG. 2, an n⁺-type collector (2-2) is first formed on a p-type substrate (2-1), and then an insulating thin film (2-3) and a polysilicon thin film (2-4) for a base electrode are sequentially deposited thereon. Thereafter, a base electrode region is defined by a photoresist mask and etching of the polysilicon thin film (2-4).

[0023] After the above step, an insulating thin film (2-5) is deposited thereon, and then the photoresist mask, the insulating thin film (2-5), the polysilicon thin film (2-4) and the insulating thin film (2-3) are defined as an active region by etching process.

[0024] Subsequently, an n-type silicon layer (2-6) for a collector, a SiGe layer (2-7) for a base, and a silicon layer (2-8) for an emitter are sequentially grown through the application of impurity thereon.

[0025] During the growth of the layers, (2-6), (2-7), and (2-8), as shown in FIG. 2, a polycrystalline or an amorphous silicon thin films, (2-6-1), (2-7-1) and (2-8-1), are formed at each side thereof, respectively. Thereafter, a silicide thin film (2-9) for a collector metal junction is formed, and a metal electrode (2-10) is then deposited to thereby obtain an element.

[0026] However, the above element suffers from a drawback that since if a current path passes via a sequence of the amorphous silicon thin films, (2-8-1), (2-7-1) and (2-6-1), it can be prone to a short between the collector and the emitter. Likewise, current paths passing through a sequence of the amorphous silicon thin films, (2-8-1), (2-7-1), (2-6-1) and the n-type Si thin film (2-6), or a series of the thin film (2-6), the thin films, (2-7-1) and (2-6-1) may occur, in practice thereby causing an emitter-base and a base-collector short.

[0027] In addition, when the collector, the base and the emitter layer (2-6, 2-7 and 2-8)) is selectively growing, since the thin films (2-6-1, 2-7-1 and 2-8-1) are laterally formed respectively, the active region defined by a single-crystalline silicon layer is not clearly defined.

[0028] It is, therefore, a primary object of the present invention to provide a super self-aligned bipolar transistor and a method for manufacturing thereof which is capable of miniaturizing the size of an element, and simplifying the fabrication process without designing a trench for isolating between elements, thereby enhancing the performance thereof.

[0029] In accordance with the present invention, there is provided a super self-aligned heterojunction bipolar transistor, which comprise a semiconductor substrate having a buried collector; a first insulating film, a second insulating film and a conducting layer for a base electrode sequentially formed on the substrate, the first insulating film being formed at both sides of the second insulating film and the conducting layer; a collector surrounded by the first and the second insulating films and the conducting layer, and formed on the buried collector in an active region of the transistor defined by patterning the conducting layer and the first and the second insulating films; a multi-layer intrinsic base formed on the collector, and a multi-layer extrinsic base formed on the conducting layer and the first insulating film of the sidewall; an emitter formed on the intrinsic base; a first spacer formed at both sides of the emitter, and a second spacer formed on the first spacer and formed at both sidewalls of the emitter; a metallic base electrode formed on the extrinsic base and a metalic emitter electrode formed on the emitter; a passivation insulating layer formed on an entire surface of the above semi-finished structure; and metallic interconnections formed on the base electrode, the emitter electrode, and the buried collector, passing through the passivation insulating layer, and/or the first and the second insulating film, respectively.

[0030] In accordance with the present invention, there is provided a method for manufacturing a super self-aligned heterojunction bipolar transistor, which comprises the steps of:

[0031] (a) growing a collector film on an entire surface of a semiconductor substrate having a buried collector; (b) sequentially forming a plurality of masking layers on the collector film, and patterning the masking layers and the collector film using a photoresist pattern for defining an active region as a mask; (c) forming a first insulating film to coat the exposed substrate and at both sidewalls of the collector; (d) forming a second insulating film on the first insulating film; (e) forming a conducting layer for base electrode on the second insulating film such that its height is equal to the collector; (f) depositing a multi-layer base to form simultaneously an intrinsic base on said collector and an extrinsic base on said conducting layer; (g) forming a third insulating film, and opening an emitter region by etching the third insulating film; (h) depositing an emitter on the exposed intrinsic base and on a portion of the third insulating film; (i) forming a spacer at both sidewalls of the emitter and on the third insulating film; (j) forming a metallic silicide on the emitter and on the extrinsic base; and (k) depositing a passivation insulator, opening contact windows to contact the emitter silicide, the base silicide and the buried collector, and performing a metal wiring process.

[0032] Preferably, the semiconductor substrate is composed of a single silicon substrate, a heterojunction substrate being made of Si/SiGe/Ge, or a heterojunction substrate being made of Si/diamond/ Si.

[0033] Preferably, the plurality of masking layers are composed of a pad oxide, a first masking layer and a second masking layer, in which the etching rates of the masking layers are different from each other. Also, the first masking layer is a silicon nitride and the second masking layer is a polysilicon.

[0034] Preferably, the first insulating film, used as a spacer of the collector, is a thermal oxide formed by thermal oxidation of the exposed substrate.

[0035] In addition, the step of (d) may further comprise: (d1) overcoating the second insulating film; (d2) chemical-mechanically polishing the overcoated second insulating film using the second masking layer as a polishing stopper; and (d3) etching the overcoated portion of the second insulating film.

[0036] More preferably, the step of (e) further comprises: (e1) overcoating the conducting layer; (e2) first chemical-mechanically polishing the overcoated conducting layer using the second masking layer as a stopper; (e3) second etching the conducting layer using the first masking layer as an etching stopper; and (e4) third etching the conducting layer using the pad oxide as an etching stopper.

[0037] Preferably, the conducting layer for the base electrode is a P⁺-type polysilicon, a poly-SiGe, or a poly-Ge which is doped by either an in-situ doping or a dopant implantation. Also, the multi-layer base is comprised of a Si/undoped SiGe/doped SiGe/Si heterojunction structure, to thereby prevent the degradation of the performance of the element due to the occurrence of a parasitic electric potential.

[0038] Before depositing the passivation insulating film of the (k) step, the method may further comprise the step of removing the remaining collector films to expose the surface of the substrate, to thereby decrease a transmission loss of transistor.

[0039] Also, before depositing the passivation insulating film of the (k) step, the method may further comprise the step of forming a collector sinker by implanting dopants into a portion of remaining collector films in order to directly connect with the collector wire, thereby decreasing the step-coverage of the metal wire.

[0040] The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments, when taken in conjunction with the accompanying drawings, in which:

[0041] FIG. 1 shows a cross-sectional view of a super self-aligned npn Si/SiGe heterojunction bipolar transistor which utilizes the selective base epitaxial growth method previously described;

[0042] FIG. 2 offers a cross-sectional view of a heterojunction bipolar transistor which is self-aligned between collector and base by using another method previously described;

[0043] FIG. 3 explains a cross-sectional view of a super self-aligned bipolar transistor manufactured in accordance with a preferred embodiment of the present invention;

[0044] FIGS. 4(A) to 4(P) exhibit schematic cross-sectional views setting forth the manufacturing steps for the super self-aligned bipolar transistor in accordance with one preferred embodiment of the present invention;

[0045] FIGS. 5(A) to 5(P) exhibit schematic cross-sectional views setting forth the manufacturing steps for the super self-aligned bipolar transistor in accordance with other preferred embodiments of the present invention; and

[0046] FIGS. 6(A) to 6(P) exhibit schematic cross-sectional views setting forth the manufacturing steps for the super self-aligned bipolar transistor in accordance with other preferred embodiments of the present invention.

[0047] FIG. 3 provides a cross-sectional view of a super self-aligned bipolar transistor in accordance with a preferred embodiment of the present invention.

[0048] Referring to FIG. 3, a buried collector 2 is first formed on a semiconductor substrate 1, and then a first insulating film 9, a second insulating film 10 and a conducting thin film 11 for a base electrode are sequentially formed thereon. At this time, a portion of the first insulating film 9 is formed at both sides of the second insulating film 10 and the conducting layer 11.

[0049] Meanwhile, the semiconductor substrate 1 is preferably composed of single silicon substrate, a heterojunction substrate being made of Si/SiGe/Ge, or a heterojunction substrate being made of Si/diamond/Si or Ge. Also, the above conducting thin film 11 is generally made of a polysilicon of high concentration, a poly-SiGe, or a poly-Ge which is doped by either an in-situ doping or a dopant implantation.

[0050] Then, a collector layer 4 such as a single-crystalline silicon or a germanium is formed on the buried collector 2 in an active region of the transistor defined by patterning the conducting layer 11 and the first and the second insulating films, 10 and 9, respectively. Also, the collector layer 4 is surrounded by the first and the second insulating films 9, 10 and the conducting layer 11. A multi-layer intrinsic base 12 is formed on the collector layer 4, and a multi-layer extrinsic base 12-1 is formed on the conducting layer 11 and the first insulating film 9 of the sidewall. Preferably, the multi-layer intrinsic and extrinsic base 12 and 12-1 are formed by a double layer consisting of Si/SiGe, or more preferably, comprised of a Si/undoped SiGe/doped SiGe/Si heterojunction structure.

[0051] An emitter layer 14 is formed on the intrinsic base 12. A third insulating film 13 is formed at both sides of the emitter layer 14, and a spacer 16 is formed on the third insulating film 13 and at both sidewalls of the emitter 14, for isolating the emitter layer 14 from the conducting layer 11. On the extrinsic base 12-1, a metallic base electrode 17 is formed, and a metalic emitter electrode 17 is formed on the emitter layer 14.

[0052] On the above resulting structure, a passivation insulating layer 18 is deposited, and then metallic interconnections 19 are formed on the metallic base/emitter electrodes 17 and the buried collector 2 passing through the passivation insulating layer 18 and/or the first and second insulating layers 9 and 10.

[0053] In comparison with the conventional arts (see, FIGS. 1 and 2), details of the advantages of the present invention will be described in detail below with reference to FIG. 3.

[0054] First, in the conventional art, a trench structure should be deeply formed to isolate the elements so as to prevent the collector junction portion (1-4) from contacting with elements through the n⁻ Si collector layer (1-3), in the n⁺ buried Si collector layer (1-2) deposited on the entire surface of the substrate, as shown in FIG. 1. As a result, a plane area for filling with the BPSG insulating thin film (1-5) is increased to thereby entail a bulkier element.

[0055] On the other hand, since each of the collector thin films 4 is isolated from the others by the aid of the insulating thin film 9 and 10, as shown in FIG. 3, in the present invention it is unnecessary to use the sophisticated trench isolation process. Likewise, since each of the self-alignments of base-collector and emitter-base are performed so that all of the emitter, the base and the collector has the same area relative to each other, it is possible to switch upward/downward operating modes, thereby making it possible to reduce a parasitic capacity between the base and the collector, and to self-align between the emitter and the base. Thus, removing the need for a process to isolate the elements results in a smaller element and a further simplified process step.

[0056] Second, in FIGS. 2 and 3, a useless region in FIG. 1 (which is indicated by length L) is eliminated to miniaturize a size of the element, resulting in a possibility of high integration and a reduction of parasitic capacity caused between an n⁺ buried collector and a p-type substrate, thereby making it possible to enhance an operating speed of the element.

[0057] On the other hand, in comparison with the element shown in FIG. 2, merits of the element shown in FIG. 3 will be discussed below.

[0058] First, in the case of the element presented in FIG. 2, since a current path passes via a sequence of the amorphous silicon thin films, (2-8-1), (2-7-1) and (2-6-1), it can be prone to a collector -emitter short effect not related to a leakage of current. Similarly, since a current path passes through a sequence of the amorphous silicon thin films, (2-8-1), (2-7-1), (2-6-1) and the n-type silicon thin film (2-6), or a series of the n-type silicon thin films, (2-6), (2-7-1) and (2-6-1), an emitter-base and a basecollector short effects may occur. In consequence, in practice the element associated with the structure shown in FIG. 2 is difficult to accomplish.

[0059] Furthermore, when the n-type silicon thin film (2-6), i.e., collector thin film, is selectively grown, since the thin film (2-6-1) is grown from sides of the collector thin film (2-6), the thicker the thickness of the collector thin film (2-6) is, the greater the growth of the thin film (2-6-1) in the sides thereof. As a result, a sequence of simple-crystal thin films, (2-8), (2-7), (2-6) and (2-2), to be defined as an active region in the element may not be clearly determined. In addition to the growth of both of the SiGe thin film (2-7) and the silicon thin film (2-8), since the thin films, (2-7-1) and (2-8-1), are also grown, a width of the active region in the element depends on a thickness of a sequence of the thin films, (2-6), (2-7) and (2-8).

[0060] In contrast to the element disclosed previously, the present invention prevents a poly-crystalline thin film from growing between the polysilicon conducting film 11 and the collector layer 4, thereby making it possible to clearly define the active region in the element as defined by a mask. Also, isolation between an emitter layer 14 and the conductiong layers is derived by using a mask defining an emitter region and spacers 13 and 16. Thus, the present invention is less prone to a flow of leakage current or an emitter-base-collector short effect.

[0061] Second, when a single p-type SiGe thin film is used as a base as shown in FIG. 2, a p-type impurity within the base thin film, during the growth of the emitter layer (2-8), may be diffused to the collector and the emitter adjacent to the base, respectively. Thus, discordance between a junction face of a sequence of the emitter thin film (2-8), the SiGe base thin film (2-7) and the n-type silicon collector thin film (2-6), i.e., a sequence of emitter-base-collector, and a junction face by the npn impurity is incurred. As a result, a parasitic electric potential is created at the junction faces between the emitter-the base and between the collector-the base, hence, the parasitic electric potential prevents an electron from transferring from the emitter to the collector, thereby causing degraded performance factors of the element such as a current amplification factor and a cutoff frequency and so on.

[0062] Conversely, in the present invention, in order to overcome the degradation of performance factors arising from generation of such parasitic electric potential, the base layer 12 and 12-1 have a multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si.

[0063] Third, in the prior art element, since a thickness of the collector thin film in a high speed element is thinly designed, a thickness of the base electrode film (2-4) in FIG. 2 is thin so that a parasitic resistance resulting from the base electrode film (2-4) is further increased. The present invention, by contrast, provides a silide layers 17 to minimize the parasitic resistance as shown in FIG. 3.

[0064] Fourth, in order to achieve a high speed element when a thickness of the collector thin film (2-6) is decreased, the thickness of the insulating thin film (2-3) is also decreased, thus entailing a reduction of breakdown voltages between the thin film (2-4) and the thin film (2-6-1) and between the thin film (2-4) and the collector thin film (2-6). In accordance with the present invention, even though a thickness of the collector layer 4 is decreased depending on the insulating films 9 and 10, the breakdown voltage between the conduction layer 11 and the collector layer 4 is not decreased.

[0065] Fifth, in the structure shown in FIG. 2, since a selective epitaxial growth process to grow the SiGe thin film (2-7) is used, it is difficult to manufacture and has cumbersome processes, thereby degrading overall productivity. In addition, the prior art structure causes an increase of parasitic resistance owing to a junction between the base electrode (2-4) and the base thin film (2-7) being performed at the sides thereof.

[0066] In accordance with the present invention, the selective epitaxial growth for the intrinsic and extrinsic base 12 and 12-1 is not required since all surfaces underlying the base are made of silicon, thereby preventing a loading effect causing the degradation of transistor and preventing an increase in the parasitic resistance in the base regions.

[0067] Hereinafter, the manufacturing method of a super self-aligned bipolar transistor in accordance with the present invention will be described in detail.

[0068] FIGS. 4(A) to 4(P) show schematic cross-sectional views setting forth the manufacturing steps for super self-aligned bipolar transistors according to a first embodiment of this invention.

[0069] Referring to FIG. 4 (A), there are shown a p-type semiconductor substrate 1 having a buried collector 2. The semiconductor substrate 1 is preferably composed of a single silicon substrate as shown in FIG. 4 (A). Also, the substrate can be composed of a heterojunction substrate being made of Si/SiGe/Ge, or being made of Si/diamond thin film/Si. The above buried collector 2 is generally formed by photolithography, ion implantation and annealing process.

[0070] Next, on the entire surface of the substrate 1, a collector thin film 3 is grown. Then, a collector region 4 is formed by selectively implanting n-type dopants into the portion of the collector thin film 3. Sequentially, a plurality of masking layers are formed on the resultant structure. At this time, the plurality of masking layers are composed of a pad oxide layer 5, a first making layer 6 and a second masking layer 7, in which an etching rate of each masking layer is different from that of the other masking layers to use an etching stopper. That is, the first masking layer 6 uses a silicon nitride and the second masking layer 7 is a polysilicon film.

[0071] Turning now to FIG. 4(B), the masking layers 5, 6 and 7 and the collector films 3 and 4 are sequentially etched by using a photoresist pattern 8 for defining an active region of transistors as a mask, and then the photoresist mask 8 is removed.

[0072] Referring to FIG. 4(C), a first insulating film 9 such as a thermal oxide is formed on the resultant structure so as to coat the exposed substrate and both sidewalls of the collector film 3 and 4. The first insulating film 9 used as a spacer of the collector is grown by thermal oxidation process of the exposed substrate 1 and collector thin film 3 and 4.

[0073] FIGS. 4(D) to 4(F) illustrate steps of forming a second insulating film 10 on the first insulating film 9. The formation steps of the second insulating film 10 comprise overcoating the second insulating film 10; chemically-mechanically polishing the overcoated second insulating film 10 using the polysilicon masking layer 7 as a polishing stopper, as shown in FIG. 4(D), and etching the overcoated portion of the second insulating film 10, as shown in FIGS. 4(E) and 4(F).

[0074] Thereafter, the formation steps of a conducting layer 11 for a base electrode will be described below with reference to FIGS. 4(G) to 4(J).

[0075] First, a conducting layer 11 is overcoated such that its height is higher than that of the polysilicon masking layer 7, and then the overcoated portion of the conducting film 11 is firstly removed by chemically-mechanically polishing using the second masking layer 7 as a stopper, that is, the overcoated portion of the conducting film is polished such that the surface of the conducting film is planarized with that of the second masking layer 7, as shown in FIG. 4(G).

[0076] Thereafter, the conducting film 11 is further etched using the first masking layer 6 as an etching stopper, wherein the conducting film 11 and the polysilicon masking layer 7 are also etched the same as the etched thickness of the conducting film 11, as shown in FIG. 4(H).

[0077] Finally, the conducting film 11 is further etched using the pad oxide 5 as an etching stopper, to thereby form a conducting layer 11 for base electrode on the second insulating film 10 such that its height is equal to the collector film 4, as shown in FIG. 4 (I). Then, the pad oxide 5 and the first masking layer 6 are removed, as shown in FIG. 4 (J). At this time, the conducting layer 11 for the base electrode is a P⁺-type polysilicon, a poly-SiGe, or a poly-Ge which is doped by either an in-situ doping or a dopant implantation.

[0078] Referring now to FIG. 4(K), multi-layer base materials are deposited on the resultant structure. A single-crystalline intrinsic base 12 is formed on the surface of the single-crystalline collector films 3 and 4, and a poly-crystalline extrinsic base 12-1 is formed on the polysilicon conducting layer 11, simultaneously. In order to prevent the degradation of the performance of the element due to the occurrence of a parasitic electric potential, the multi-layer base is comprised of Si/undoped SiGe/doped SiGe/Si heterojunction structure from the bottom to the top.

[0079] Referring to FIG. 4(L), a third insulating film 13 is deposited on the base regions 12 and 12-1, and then the intrinsic base 12 is opened by etching the third insulating film 13 using a photoresist pattern defining an emitter region as a mask. Thereafter, an emitter layer 14 is formed by depositing on the surface of the exposed intrinsic base 12 and a portion of the third insulating film 13. The single crystalline emitter layer 14 is then doped by either an in-situ doping or an ion implantation followed by the heat treatment.

[0080] Referring now to FIG. 4(M), a spacer 16 is formed at both sidewalls of the emitter layer 14 and on the third insulating film 13.

[0081] Referring to FIG. 4(N), a metal or a metallic silicide layer 17, such as a titanium silicide is selectively formed on the emitter layer 14 and the base electrode 12-1 in order to decrease the parasitic resistance of base and emitter.

[0082] Referring to FIG. 4(0), a non-active region of the transistor, such as a portion of metallic silicide 17, the extrinsic base 12-1, the conducting layer 11 and the collector films 3 are sequentialy etched using a photoresist mask defining an active region as a mask. Thereafter, a passivation insulating film 18 is deposited on the entire surface of the resultant structure.

[0083] Referring to FIG. 4(P), metallic interconnections 19 are formed through contact windows exposing the emitter silicide 19, the base silicide 17 and the buried collector 2.

[0084] FIGS. 5(A) to 5(P) exhibit schematic cross-sectional views setting forth manufacturing steps for a super self-aligned bipolar transistor according to the second embodiment of the present invention.

[0085] All processes of this embodiment are the same as the above-described first embodiment except for the steps shown in FIGS. 5(O) and 5(P). Therefore, descriptions of the same processes will be omitted.

[0086] This embodiment is to prevent transmission losses due to the remaining collector thin films 3 in the first embodiment. The transmission losses occur in the remaining collector films 3 since dopants are unintentionally added into the single-crystalline collector films 3.

[0087] In order to prevent the transmission loss, this embodiment further comprises the step of removing the remaining collector films 3 to expose the surface of the substrate 1, as shown in FIG. 5(O). As a result, the passivation insulating film 18 is directly connected to the substrate 1, as shown in FIG. 5(P), thereby decreasing the transmission loss of the transistor.

[0088] FIGS. 6(A) to 6(P) exhibit schematic cross-sectional views setting forth manufacturing steps for a super self-aligned bipolar transistor according to the third embodiment of the present invention.

[0089] Likewise, all processes of this embodiment are the same as the above-described first embodiment except for the steps shown in FIGS. 6(O) and 6(P). Therefore, descriptions of the same processes will be omitted.

[0090] The third embodiment of this invention is to improve the step-coverage of the metallic interconnections. Referring to FIG. 6(O), before depositing the passivation insulating film 20, this embodiment further comprises the step of forming a collector sinker 19 by implanting dopants into a portion of remaining collector films 3 using a photoresist pattern 18 as an ion-implanting mask. As a result, the collector interconnection 21 is directly connected with the collector sinker 19, thereby decreasing the step-coverage of the metal wire.

[0091] As mentioned above, the present invention has advantages in that an operating speed of the bipolar transistor can be increased using a Si/SiGe heterojunction thin film structure, a parasitic capacity and a parasitic resistance of elements are reduced, and an element is miniaturized, to thereby achieve high speed, high integration and low power consumption.

[0092] Furthermore, the invention provides a super self-aligned heterojunction bipolar transistor and method thereof which is capable of miniaturizing an element, simplifying the process steps thereof without using a trench isolation process and a sophisticated selective epitaxial growing (SEG) process.

[0093] While the present invention has been described with respect to certain preferred embodiments only, other modifications and variations may be made without departing from the scope of the present invention as set forth in the following claims.