Apparatus for interconnecting logic boards

[0002] This is a continuation application of U.S. Ser. No. 09/128,779, filed Aug. 4, 1998. U.S. Pat. No. 6,163,464.

[0003] The present invention relates to apparatus for interconnecting logic boards, which is preferably applicable to equipment for transmitting signals at high speed between a plurality of logic boards through the intermediary of interconnecting boards.

[0004] Apparatuses for transmitting signals between a plurality of logic boards through a backplane and interconnecting boards have been adopted in computers and switchboards. For example, computers, such as a workstation for transmitting signals between logic boards through bus wires provided on a backplane to which a plurality of logic boards, including a processor, memories, I/O devices are connected, are disclosed in pp. 330-337 of Digest of Technical Papers (issued in February, 1993) of CONPCON 93. In the connection method along the bus, the number of signals which are input or output through a logic board ranges from several bytes to ten odd bytes (8 bytes for example). The transfer frequency is in a range of 30 to no more than 80 MHz. This is due to high load because of a plurality of logic boards being connected to the bus wires and also due to the difficulty in increasing the transfer frequency owing to the disorder of waveform caused by reflections from each logic board.

[0005] With the increase in the operation frequency of the processors and also with the progress in multiprocessing, the throughput of data transfer becomes insufficient so long as the bus connection method is used. To solve this problem, it is required to adopt the switch connection method. To give an example, the switch connection method is to provide interconnecting boards, form a switch by LSI (semiconductor integrated circuit device) on each interconnecting board, and transmit signals between the logic boards through the intermediary of switches. In this switch connection method, it is possible to make a one-to-one connection between the logic LSI's on the logic boards and the switch LSI's on the interconnecting boards, thereby improving the transfer frequency to higher than 100 MHz. Apparatus for transmitting signals between a plurality of logic boards through interconnecting boards is disclosed U.S. Pat. No.5,122,691. The above-mentioned known example is shown in FIG. 7, in which reference numerals 5a, 5bdenote logic boards, 76bdenotes a logic LSI mounted on a logic board 5b, and a similar LSI is mounted also in a logic board 5a. Numeral 76bdenotes a connector for connecting the logic board 5bto the interconnecting boards 72gto 72j. Numeral 74gdenotes an interconnecting LSI, mounted on an interconnecting board, which forms a switch for example. One each of the same LSI is mounted on the interconnecting boards 72hto 72j. In this prior-art example, logic boards 5 are directly connected to the interconnecting boards 72 without intervention of a backplane, and the logic boards 5 and the interconnecting boards 72 exchange signals through pins of the connector 76 at the intersections of the logic boards 5 and the interconnecting boards 72. Accordingly, there are a limited number of pins connecting the logic boards to a single interconnecting board 72 (3 pins in an embodiment of U.S. Pat. No. 5,122,691, of which 2 pins are for signals). Therefore, in order to transfer data of 8 bytes (64 bits) per logic board, more than 30 interconnecting boards are required, which results in the first problem of difficulty in mounting and assembling those boards and hence a high production cost.

[0006] When the switch connection method is adopted to improve throughput, there arise the following problems. As the transfer frequency improves, it becomes impossible to transfer data in one cycle, so that it will become necessary to adopt a method of transferring data in two or more cycles. In this case, it becomes necessary to equalize propagation delays in the transfer of data between the logic boards and the interconnecting boards, and it becomes necessary to at least equalize wire lengths between the logic boards and the interconnecting boards. However, in the switch connection method, because there is a large number of wires used (the number of logic boards×the number of input and output signals per logic board), the second problem is that a large number of man-hours for design are required to equalize the length of all wires. Though JP-A-62-204359 discloses the necessity to equalize the wire lengths in the transfer method as mentioned above, it does not disclose a wiring method.

[0007] It is an object of the present invention to solve the first and the second problems and provide a logic board interconnection apparatus which realizes low cost and high reliability and high-speed signal transmission.

[0008] The first problem can be solved effectively by connecting the logic boards and the interconnecting boards to a backplane, transmitting signals through the connector pins other than at the intersections of the logic boards and the interconnecting boards, thereby increasing the number of signals that the interconnecting boards couple to the backplane and decreasing the number of the interconnecting boards used. The second problem can be solved effectively by connecting all logic boards to the backplane with the logic boards in vertical position, that is, at right angles with the interconnecting boards and mutually spaced apart by a specified distance and so on. More specifically, by dividing connectors connecting the interconnecting boards and the backplane into regions of the number of the logic boards, allotting the divided regions to the logic boards in a designated order, dividing the connectors for connecting the logic boards and the backplane into regions of the number of the interconnecting boards, allotting the divided regions to the interconnecting boards in a designated order, and connecting the regions of the connectors for the interconnecting boards and the regions of the connectors for the logic boards on one-to-one correspondence by wires on the backplane, so that all wire lengths connecting the logic boards and the interconnecting boards can be equalized easily.

[0009] According to the present invention, in connection between the logic boards and the interconnecting boards, equilong wiring for data several bytes long can be done easily, which will contribute to lower cost, higher reliability and high-speed signal transmission.

[0010] FIG. 1 is a diagram showing a first embodiment of the present invention;

[0011] FIG. 2 is a diagram showing details of a backplane in FIG. 1;

[0012] FIG. 3 is a diagram showing wiring of the backplane in FIG. 2;

[0013] FIG. 4 is a diagram showing details of a logic board in FIG. 1;

[0014] FIG. 5 is a diagram showing details or a interconnecting board in FIG. 1;

[0015] FIG. 6A is a diagram for explaining the relation between a propagation delay and a transfer period when propagation times are substantially equal;

[0016] FIG. 6B is a diagram for explaining the relation between a propagation delay and a transfer period when propagation times are not equal;

[0017] FIG. 7 is a diagram showing an example of the prior-art apparatus;

[0018] FIG. 8 is a diagram showing a second embodiment of the present invention; and

[0019] FIG. 9 is a diagram showing a third embodiment of the present invention.

[0020] FIG. 1 shows a first embodiment of the present invention, in which the man-hours for design of equilong wiring on the backplane are minimal. In FIG. 1, reference numeral 1 denotes a backplane, and 2gto 2idenote interconnecting boards. Numeral 4gdenotes an interconnecting LSI to be mounted on the interconnecting board 2g. FIG. 1 shows the interconnecting LSI as a single LSI, but this interconnecting LSI may be formed of two or more LSI's. The same interconnecting LSI's as the one 4gare mounted on the interconnecting boards 2h, 2i. The interconnecting LSI's are formed of transistors or the like for bus, ring, and switch connections. Numerals 3gto 3idenote connectors for connecting the interconnecting boards 2gto 2iwith the backplane 1, and connectors 23gto 23iof the backplane 1 in FIG. 2 are connected with connectors 53 of the interconnecting boards 2 as shown in FIG. 5. Numerals 5a, 5b, 5eand 5fdenote the logic boards, such as a processor, a memory, an I/O device, etc. Numeral 7bdenotes a logic LSI mounted on the logic board 5b. Similarly, one logic LSI each is also mounted on the logic boards 5a, 5eand 5f. As with the interconnecting LSI 4g, the logic LSI 7bmay be formed of two or more LSI's. A connector 6bconnects the logic board 5bwith the backplane 1. The logic board 5ais also connected to the backplane 1 by a similar connector. The logic boards 5e, 5fare connected by connectors 6e, 6fto the reverse side of the backplane. Though the connector 6cis not connected to a logic board in FIG. 1, a logic board is connectable to the connector 6c. Thus, the connectors 6b, 6c, 6e, 6fare connected by connectors 46 (FIG. 4) of the logic boards 5 to the connectors 26ato 26fof the backplane 1. In the present embodiment, the interconnecting boards 2gto 2iin horizontal positions are connected to the backplane 1, the logic boards 5a, 5b, 5e, 5fin vertical positions are connected from both sides to the backplane 1, and all the logic boards 5a, 5b, 5e, 5fare arranged at equal distances from the interconnecting boards 2gto 2i. In this case, the logic boards 5a, 5b, 5e, 5fare connected to both sides of the backplane 1, but may be connected only to one side of the backplane 1. Another structure can be formed such that the interconnecting LSI's are directly soldered to the backplane without providing the interconnecting boards. However, this structure lacks reliability, because the backplane may be warped when the logic boards are mounted or removed, with the result of the solder being damaged. In the present embodiment, such a problem does not arise since the interconnecting boards are connected to the backplane by means of the connectors. If solderless press-fit connectors are used, the backplane is free from the problem of solder and its reliability is improved.

[0021] FIG. 2 shows details of the backplane 1. In FIG. 2, numeral 1 denotes the backplane, 23gto 23idenote connectors for the interconnecting boards, 26ato 26fdenote connectors for connecting the logic boards, and 28 denotes wires interconnecting the connectors 23gto 23iand the connector 26a. The connectors 26ato 26fare divided into three regions 26gto 26i, the same number as the number of the interconnecting boards. The connectors 23gto 23iare divided into six regions 23ato 23f, the same number as the number of logic boards. The connector pins of the regions 26gto 26iare distribute signals to the connector pins of the connectors 23gto 23i. The connector pins of the regions 23ato 23fdistribute signals to the connector pins of the connectors 26ato 26f. The connections between the regions will be described by referring to the connections between the connector 26aand the connectors 23gto 23i. The region 26gof the connector 26ais connected to the region 23aof the connector 23g, and the region 26hof the connector 26ais connected to the region 23aof the connector 23h, and the region 26iof the connector 26ais connected to the region 23aof the connector 23i, respectively, by using wires of almost the same length 28. If the number of signals to be input to or output from a logic board is 8 bytes (64 bits), the number of wires 28 between the regions is 21 to 22 each. Description will be made in detail of wires strung between the region 26gof the connector 26aand the region 23aof the connector 23gby referring to FIG. 3. FIG. 3 is a diagram showing an example of wiring on the backplane, in which there are four rows of pins each of the connectors 23gto 23i, and 26a, and six wires are connected between the regions. The white dots are signal pins, the black dots are power pins, and the power pins are directly connected to the power layer of the backplane. Numerals 281 to 286 denote the wires 28 in FIG. 2. The wires of X directions and Y directions are placed in different wiring layers. Supposing that the space between the connectors 23gto 23ifor connecting the interconnecting boards is 4 mm, the space between the connector 23iand the connector 26ais 50 mm, the inter-pin distance of connectors is 2 mm, and two wires can be strung in equal distances between the pins, the wire length is 76.7 mm for wire 281, 75.3 mm for wires 282 and 284, and 78.0 mm for wires 283, 285, 286. Therefore, the difference between the maximum and minimum wire lengths is 2.7 mm, and if the propagation delay of the wires is 7 ns/m, the difference in propagation delay is not more than 20 ps. If wiring is optimized, the propagation delay can be shortened. Also for wiring between the region 26hof the connector 26aand the connector 23hand between the region 26iof the connector 26aand the connector 23i, if the relative position of the pins to be wired is the same as with the pins of the region 26gand the connector 23gand the wires are routed on wiring layers other than that for the wires 281 to 286, equilong wiring can be done merely by displacing the wires 281 to 286 in the vertical direction. Further, for wiring between the connectors 26bto 26fand the connectors 23gto 23iin FIG. 2, the same wiring as between the connector 26aand the connectors 23gto 23ican be applied. Specifically, if the same relative position as between the connector 26aand the connectors 23gto 23iis used for the pins to be wired, equilong wiring can be set up between the connectors only by displacing the wiring in the horizontal direction. After all, wiring of 281 to 286 can be utilized for all inter-connection wiring with the result of man-hours for design being reduced. When the connectors 26ato 26fare located in the regions 23ato 23f, the horizontal wiring length becomes minimum, so that the propagation delay from the logic boards to the interconnecting boards can be decreased. At this time, the wires on the backplane 1 extend for the most part in the vertical direction, the horizontal wires being only at the lead-out portions from the connector pins. As the result, the number of horizontal wiring layers can be reduced. By connecting the interconnecting boards and the logic boards to the backplane and dividing the connectors into proper regions as in the present embodiment, the distances between the pins can be made substantially equal, and equilong wiring can be realized easily in wiring between all logic boards and interconnecting boards.

[0022] FIG. 4 shows details of the logic board. In FIG. 4, numeral 5 denotes a logic board, 46 denotes a connector, connected to the backplane, which is divided into three regions 46gto 46ilike in the connectors 26ato 26fin FIG. 2. The connector 46 is connected to any of the connectors 26ato 26fin FIG. 2. Numeral 48 denotes wires connecting the regions 46gto 46iof the connector 46 with the logic LSI 7 by equilong wiring. In FIG. 4, the wires are connected to one side of LSI 7. The I/O pins of LSI 7, to which the wires 48 are connected, are divided into three regions so as to correspond to the regions 46gto 46ito facilitate installation of wires 48. If the number of signals to be input to or output from a logic board is 8 bytes (64 bits), like in the wires 28 in FIG. 2, the number of signals 48 between the regions 46g to 46i and LSI 7 is 21 to 22 each.

[0023] FIG. 5 shows details of the interconnecting board. In FIG. 5, numeral 2 denotes an interconnecting board, and 53 denotes a connector, which is connected to the backplane and divided into six regions 53ato 53flike those connectors 23gto 23iin FIG. 2. The connector 53 is connected to any of the connectors 23gto 23iin FIG. 2. Numeral 58 denotes wires connecting the regions 53ato 53fof the connector 53 with the interconnecting LSI 4 by wires of the same length. The input/output pins of LSI 4 are divided into six regions so as to correspond to the regions 53ato 53fto facilitate installation of wires 58. If the number of signals to be input to or output from one logic board is 8 bytes (64 bits), like in the wires 28 in FIG. 2, the number of signals between the regions 53ato 53fand LSI 4 is 21 to 22 each.

[0024] Taking data transfer from the logic boards to the interconnecting boards as an example, description will be made of data transfer under two different conditions, that is, when the propagation delays are substantially equal by referring to FIG. 6A and when the propagation delays are not equal by referring to FIG. 6B. Transmit data is data several bytes long output by the logic LSI on the logic board, and variations hardly occur in propagation delay among individual pieces of transmit data. Receive data is data input into the switch LSI on the interconnecting board, and variations occur in propagation delay among different pieces of receive data owing to variations in wiring length on the logic boards, the backplane or the interconnecting boards. The switch LSI needs to receive data during a period between the arrival of all bits of the first data and the arrival of the first portion of the second data in FIGS. 6A and 6B. When propagation delays are not equal among different pieces of data, there is a large data uncertain region due to differences in propagation delay compared with a data uncertain region when propagation delays are substantially equal. In order for the switch LSI to receive correct data, it is necessary to set a greater data transfer period tcyc. Therefore, to transmit signals at high speed, it is required to equalize the propagation delay for all data. By achieving equilong wiring as in the present embodiment, the propagation delay of data between the logic boards and the interconnecting boards can be made almost equal, so that high-speed signal transmission can be carried out.

[0025] To reduce the number of interconnecting boards, it is necessary to connect the logic boards 5a, 5b, 5e, 5fand the interconnecting boards 2gto 2ito the backplane 1, and transmit signals through the wires on the backplane as shown in FIG. 1. Further, by performing equilong wiring on the logic boards, the interconnecting boards and the backplane, it becomes possible to realize cost reduction, high reliability and high-speed transmission of signals. In the present embodiment, unlike in second and third embodiments that will be described later, all logic boards are arranged equidistantly from the interconnecting boards, it is only necessary to perform equilong wiring for the logic boards, the interconnecting boards, and the backplane. Wiring of the backplane is systematic work, and therefore man-hours for design of equilong wiring are reduced to a minimum.

[0026] FIG. 8 is a diagram showing a second embodiment of the present invention. Even when the number of wiring layers of the backplane is small, equilong wiring is possible. In FIG. 8, numeral 1 denotes a backplane, 2gto 2idenote interconnecting boards, 4gdenotes an interconnecting LSI mounted on an interconnecting board 2g, and one each of this LSI is also mounted on the interconnecting boards 2hand 2i. Numerals 3gto 3idenote connectors for connecting the interconnecting boards 2gto 2ito the backplane 1. Numerals 5a, 5b, 5e, 5fdenotes logic boards, 7bdenotes a logic LSI mounted on the logic board 5b, and a similar LSI is also mounted on each of the logic boards 5a, 5e, 5f. Numeral 6bdenotes a connector connecting the logic board 5bto the backplane 1, and the logic board 5bis also connected by a connector to the backplane 1. Numeral 6bdenotes a connector connecting the logic board 5bto the backplane 1, and the logic board 5ais likewise connected by a connector to the backplane 1. The logic boards 5e, 5fare connected to the reverse side of the backplane 1 by connectors 6e, 6f. Though logic boards are not connected to the connectors 6c, 6d, logic boards can be connected to those connectors like the other connectors. In FIG. 1, all the logic boards 5a, 5b, 5e, 5fare arranged equidistantly from the interconnecting boards 2gto 2i, whereas in FIG. 8 the logic boards 5e, 5fare connected to the side of the backplane opposite the side where the interconnecting boards 2gto 2iare provided, and the connectors are at right angles with the connectors 3gto 3i. Wiring between the logic boards 5e, 5fand the interconnecting boards 2gto 2iis carried out as follows. If the number of signals input from and output to a logic board is 8 bytes (64 bits), the number of signals from the logic boards 5e, 5fto the interconnecting boards 2gto 2iis 21 to 22 each. If the number of signals directly connected by the pins at intersections of the connectors is four, the remaining 17 to 18 signals are connected by using the connector pins other than at the intersections, and also using the wires on the backplane. The wires on the backplane at this time represent wiring length differences because the wiring length on the backplane is zero where direct pin connection is done at the intersections of the connectors. Therefore, when wiring the interconnecting boards 2gto 2ior the logic boards 5e, 5f, by setting a longer length of wire for direct pin connections at the intersections of the connectors and also by setting a shorter length of wire for wiring through the backplane, the wiring length differences are lessened, so that equilong wiring is performed between the interconnecting boards and the logic boards. Wiring between the logic boards 5a, 5band the interconnecting boards 2gto 2iis carried out in the same way as wiring between the logic boards and the interconnecting boards in the first embodiment. By the wiring described above, the wiring lengths between the logic boards 5e, 5fand the interconnecting boards 2gto 2ican be equalized, and the wiring lengths between the logic boards 5a, 5band the interconnecting boards 2gto 2ican be equalized. However, there is a difference in wiring length between the two groups. In order to obtain a uniform propagation delay between all logic boards and the interconnecting boards, the wiring length differences that occur between the logic boards are reduced in wiring of the interconnecting boards 2gto 2ior the logic boards 5a, 5b, 5e, 5f. In FIG. 8, the logic boards5a, 5bare connected on the same side as the interconnecting boards 2gto 2i, but the logic boards 5a, 5bmay be connected on the reverse side like the logic boards 5e, 5f. In the present embodiment, some of the wires connecting the logic boards and the interconnecting boards are directly connected through the connectors, with the result that the number of wires on the backplane can be reduced, and equilong wiring can be performed between the logic boards and the interconnecting boards even when there are not many wiring layers on the backplane.

[0027] FIG. 9 shows a third embodiment of the present invention. This embodiment is effective in a case where there are many signals to be exchanged between the logic boards and the interconnecting boards and there are many interconnecting boards. The same numerals as in FIG.8 show the same parts. In FIG. 9, all logic boards are connected to the side of the backplane opposite the side where the interconnecting boards are mounted. Interconnecting boards 2jto 2lare connected to the side of the backplane opposite the side where there are the logic boards 5a, 5b. Connectors 3jto 3lconnect the interconnecting boards 2jto 2lto the backplane 1. An interconnecting LSI 4jis mounted on the interconnecting board 2j. Wiring between the logic boards 5e, 5fand the interconnecting boards 2gto 2iand wiring between the logic boards 5a, 5band the interconnecting boards 2jto 2lare the same as wiring between the logic boards 5e, 5fand the interconnecting boards 2gto 2iin the second embodiment. Wiring between the logic boards 5e, 5fand the interconnecting board 2jto 2iand wiring between the logic boards 5a, 5band the interconnecting boards 2gto 2iare the same as wiring between the logic boards 5a, 5band the interconnecting boards 2bto 2iin the second embodiment. In the third embodiment, like in the second embodiment, some of the wires between the logic boards and the interconnecting boards are directly connected through the connectors. Therefore, the number of wires on the backplane can be reduced, and equilong wiring can be done between the logic boards and the interconnecting boards even when there are not many wiring layers on the backplane.