Serial data transceiver architecture and test method for measuring the amount of jitter within a serial data stream

[0002] 1. Field of the Invention

[0003] This invention relates to digital data communication circuits, and more particularly to the testing of serial data communication circuits.

[0004] 2. Description of the Relevant Art

[0005] Electronic devices typically communicate via electrical signals (e.g., voltage and/or current) driven upon electrical conductors (e.g., metal wires). Simultaneous transmission of multiple signals is accommodated by several wires routed in parallel (i.e., buses). Most computer systems have a modular architecture centered around a bus which serves as a shared communication link between system components. The two major advantages of shared buses over direct communication links between system components are versatility and low cost. By defining a standard interconnection scheme for a given bus, new devices may be easily connected to the bus. The cost of the bus is low because it is shared among the number of components connected to the bus.

[0006] Due to technological advances, the signal processing capabilities of more modern electronic devices (e.g., microprocessors) are outstripping the signal transfer capabilities of conventional parallel buses. To their detriment, parallel buses have physical limitations which place an upper limit on the rate at which information can be transferred over the bus. For example, the electrical characteristics and loading of each wire of a bus may vary, causing signals transmitted simultaneously upon the bus to be received at different times. Bus timing must take into consideration worst case delays, resulting in reduced data transfer rates of systems employing parallel buses.

[0007] A serial data path, on the other hand, is a direct communication link between a single transmitter and a single receiver. Such a serial data path typically includes a dedicated transmission medium connected between the transmitter and receiver. The transmission medium may be, for example, a differentially-driven pair of wires or a fiber-optic cable. In cases where the transmission medium is a pair of wires, the communication link (i.e., channel) has a defined electrical loading and is typically optimized for minimum signal delay. As a result, the rate at which electrical signals can be transferred over such a serial data path exceeds the data transfer rate of a common shared parallel bus.

[0008] A typical serial data transceiver includes a transmitter and a receiver. The transmitter receives parallel data at an input port, converts the parallel data to a serial data stream in response to a transmit clock signal, and provides the serial data stream at an output port. The serial data stream includes data “windows” between data transition periods. The receiver receives a serial data stream at an input port, converts the serial data stream to parallel data, and provides the parallel data at an output port.

[0009] Serial data streams are typically self-clocking. That is to say the transmit clock signal used to transmit the data contains timing information necessary to extract the data from the serial data stream. Both the data and the timing information (i.e., the transmit clock signal) are discernible within the serial data stream. A given receiver typically recovers the transmit clock signal from the serial data stream and uses the transmit clock signal to recover the data. The receiver typically uses the recovered transmit clock signal to sample the serial data stream in the center of the data windows of the serial data stream (i.e., midway between the data transitions).

[0010] A variety of noise sources can cause the amount of time between data transitions of a serial data stream to fluctuate or “jitter”. A practical receiver must be able to accurately extract the data from the serial data stream despite the presence of a certain amount of jitter in the input serial data stream. For this reason, receivers typically include phase-locked loop (“PLL”) circuitry to recover transmit clock signals from serial data streams. The use of PLL circuitry provides some immunity to jitter in the serial data stream.

[0011] FIG. 1 is a block diagram of a typical PLL clock signal recovery/data sampling circuit 10 used within a serial data receiver. PLL clock signal recovery/data sampling circuit 10 includes a phase comparator 12, a loop filter 14, a voltage-controlled oscillator (“VCO”) 16, a divide-by-n circuit 17, and an edge-triggered latch 18. Phase comparator 12 receives a frequency-divided Q₁′ signal produced by divide-by-n circuit 17 (i.e., a frequency-divided clock signal) and a serial data stream. Phase comparator 12 produces an a.c. error signal having a short term average value substantially proportional to the phase difference between the frequency-divided Q₁′ signal and the serial data stream. Loop filter 14 may be, for example, a low pass filter. Loop filter 14 receives the a.c. error signal and produces a low pass filtered error signal substantially proportional to the short term average value of the a.c. error signal. VCO 16 then produces the Q₁′ output signal and a complementary Q₁output signal. The frequencies of the Q₁′ and Q₁output signals are dependent upon the error signal and the number n, where n is an integer greater than or equal to 1 as described below. When n=1, the Q₁output signal of VCO 16 is the transmit clock signal recovered from the serial data stream. Divide-by-n circuit 17 receives the Q₁′ output signal and divides the frequency of the Q₁′ output signal by a number n, where n is an integer greater than or equal to 1, producing the frequency-divided Q₁′ signal. Edge-triggered latch 18 recovers the serial data from the serial data stream using the Q₁output signal. Edge-triggered latch 18 samples the serial data stream (at a data or “D” input) upon the rising edge of the Q₁output signal (at a clock signal or “C” input), producing sampled serial data at a Q₂output.

[0012] FIG. 2 is a timing diagram showing the temporal relationships between the serial data, Q₁′ and Q₁output signals, and the sampled serial data, for n=1. The serial data stream includes data “windows” separated by data transition periods. Parallel lines 20 represent jitter existing within the serial data stream. VCO 16 produces output signal Q₁′ having rising edges synchronized to data transitions within the serial data stream. Output signal Q₁is the complement of signal Q₁′, and has rising edges nominally midway between the data transitions of the serial data stream. Edge-triggered latch 18 produces the sampled serial data in response to the rising edges of signal Q₁, thus edge-triggered latch 18 samples the serial data edges nominally midway between the data transitions. As sampling the serial data near one of the data transitions on either side of a data window may result in an error, this data sampling method minimizes the chance of an error occurring during data sampling.

[0013] Serial data transceivers offering, digital signal transmission rates exceeding 1 gigabit per second are now commercially available. The testing of such transceivers at their normal operating speeds, however, presents many technical challenges. Serial data transceiver test methods must verify that a given transmitter produces a serial data stream having less than or equal to a specified maximum amount of jitter. It would thus be beneficial to include testing elements within a serial data transceiver to facilitate measurement of an amount of jitter present within a serial data stream produced by a high-speed transmitter having an extremely short data window. Measuring jitter is important, especially in high speed applications, since knowledge gained from jitter testing can be used to direct a more appropriate sampling position within relatively short data windows.

[0014] The problems outlined above are in large part solved by a serial data transceiver architecture and test method for measuring the amount of jitter within a serial data stream. The serial data transceiver includes a transmitter and a receiver formed upon a monolithic semiconductor substrate. The transmitter receives parallel input data at a transmit data input port, converts the parallel input data to a serial data stream having data windows separated by data transition periods, and produces the serial data stream at a transmitter output port. The receiver receives a serial data stream at a receiver input port, converts the serial data stream to parallel output data, and provides the parallel output data at a receive data output port. The receiver includes a deserializer which receives the serial data stream, recovers the transmit clock signal used to transmit the serial data from the serial data stream, generates a timing signal based upon the recovered transmit clock signal, samples the serial data stream using the timing signal in order to recover the data from the serial data stream, aligns the deserialized data into parallel units, and provides the resulting parallel data at the receive data output port. The deserializer samples the serial data stream within each data window dependent upon the duty cycle of the timing signal. The deserializer varies the duty cycle of the timing signal according to a received control signal in order to facilitate measurement of the amount of jitter within the serial data stream.

[0015] The deserializer includes a PLL circuit having a phase comparator, a loop filter, a VCO, and a divide-by-n circuit. The phase comparator receives the serial data stream and a frequency-divided clock signal, and produces an a.c. error signal having a short term average value substantially proportional to the phase difference between the serial data stream and the frequency-divided clock signal. The loop filter receives the a.c. error signal and produces a low pass filtered error signal substantially proportional to the short term average value of the a.c. error signal. The VCO receives the filtered error signal and the control signal and produces the clock signal and the timing signal. The frequency of the clock signal is dependent upon the filtered error signal and the number n, and the duty cycle of the timing signal is dependent upon the value of the control signal. The divide-by-n circuit receives the clock signal and divides the frequency of the clock signal by a number n to produce the frequency-divided clock signal, where n is an integer greater than or equal to 1.

[0016] In one embodiment, the VCO includes a ramp generator coupled to a Schmitt trigger circuit. The ramp generator produces an output voltage which alternately increases and decreases linearly with time. The Schmitt trigger circuit produces the clock signal and the timing signal in response to the ramp generator output voltage. The ramp generator may include a current source coupled to a capacitor. In this case, the output of the current source alternates between two constant levels, and the capacitor integrates the output of the current source with time to produce the ramp generator output voltage. The current source adjusts the values of the two constant levels in response to the filtered error signal produced by the loop filter in order to maintain the period of the clock signal substantially equal to the time interval between the data transitions of the serial data stream. The current source also adjusts the values of the two constant levels in response to the control signal in order to alter the duty cycle of the timing signal.

[0017] In an alternate embodiment, the VCO includes an odd number of pairs of non-inverting and inverting logic blocks arranged in a recirculating loop. The number of pairs is also equal to half the number of bits per parallel data unit. One of the pairs of logic blocks is configured to produce the clock signal and the timing signal. Each logic block exhibits a time delay between reception of an input signal and production of an output signal. The time delay is variable and dependent upon a delay control signal. A control unit coupled to each logic block produces the delay control signal for each logic block. The control unit produces the delay control signals in response to the filtered error signal from the loop filter such that the period of the recovered transmit clock signal is substantially equal to the time interval between the data transitions of the serial data stream. The control unit also produces the delay control signals in response to the control signal in order to alter the duty cycle of the timing signal.

[0018] A system for testing the serial data transceiver in accordance with the present invention includes the serial data transceiver and a test unit. The test unit includes a parallel data generator coupled to the transmit data input port and a parallel data comparator coupled to the parallel data generator and to the receive data output port. The transmitter output port of the transceiver is coupled to the receiver input port. The parallel data generator generates parallel input test data and provides the parallel input test data to the transmit data input port. The parallel data comparator receives parallel output test data produced by the receiver and the parallel input test data produced by parallel data generator, and compares the parallel output test data to the parallel input test data. The test unit produces the control signal such that the duty cycle of the timing signal is varied. A match between the parallel output test data and the parallel input test data (i.e., a one-to-one correspondence between the logic levels of the bit positions of the parallel output test data and the parallel input test data) verifies proper operation of the transceiver and the absence of jitter at a given sampling point within the data window. Any discrepancy between the parallel output test data to the parallel input test data is indicative of jitter within the serial data stream at the sampling time determined by the control signal.

[0019] A method for testing the serial data transceiver according to the present invention includes providing the serial data transceiver and coupling the transmitter output port to the receiver input port. The following sequence of steps is repeated until a difference between parallel input test data and parallel output test data is observed:

[0020] 1) The control signal is varied such that the sampling time occurs earlier within each data window;

[0021] 2) Parallel input test data is provided to the transmit data input port;

[0022] 3) Parallel output test data is received from the receive data output port; and

[0023] 4) The parallel output test data is compared to the parallel input test data.

[0024] When a difference between the parallel input test data and the parallel output test data is observed, a “leading edge” of the data window has been located, and the value of the control signal is recorded as a first control signal value. The following sequence of steps is then repeated until a difference between the parallel input test data and the parallel output test data is again observed:

[0025] 1) The control signal is varied such that the sampling time occurs later within each data window;

[0026] 2) Parallel input test data is provided to the transmit data input port;

[0027] 3) Parallel output test data is received from the receive data output port; and

[0028] 4) The parallel output test data is compared to the parallel input test data.

[0029] When a difference between the parallel input test data and the parallel output test data is again observed, a “trailing edge” of the data window has been located, and the value of the control signal is recorded as a second control signal value. The first control signal value is subtracted from the second control signal value in order to determine the width of each data window. The data window width is subtracted from the bit time of the serial data stream in order to determine the amount of jitter present within the serial data stream.

[0030] Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:

[0031] FIG. 1 is a block diagram of a typical PLL clock signal recovery/data sampling circuit used within a serial data receiver, wherein the PLL clock signal recovery/data sampling circuit includes a phase comparator, a loop filter, a VCO, a divide-by-n circuit, and an edge-triggered latch;

[0032] FIG. 2 is a timing diagram showing the temporal relationships between signals within the PLL clock signal recovery/data sampling circuit of FIG. 1 for n=1, wherein the serial data stream includes data “windows” separated by data transition periods, and wherein the serial data stream is sampled within the data windows and nominally midway between the data transitions;

[0033] FIG. 3 is a block diagram of one embodiment of a serial data transceiver of the present invention, wherein the serial data transceiver includes a transmitter and a receiver; and wherein the receiver includes a deserializer which receives a serial data stream, recovers a transmit clock signal used to transmit the serial data from the serial data stream, generates a timing signal based upon the recovered transmit clock signal, samples the serial data stream within a data window dependent upon the duty cycle of a received control signal, aligns the deserialized data into parallel units, and provides the resulting parallel data at the receive data output port;

[0034] FIG. 4 is a block diagram of one embodiment of the deserializer of FIG. 3 including a PLL circuit having a phase comparator, a loop filter, a VCO, and a divide-by-n circuit, wherein the VCO produces a clock signal and the timing signal, and wherein the serial data stream is sampled within each data window dependent upon the duty cycle of the timing signal, and wherein the VCO varies the duty cycle of the timing signal according to a received control signal in order to facilitate measurement of the amount of jitter within the serial data stream;

[0035] FIG. 5 is a block diagram of one embodiment of the VCO of FIG. 4, wherein the VCO includes a ramp generator coupled to a Schmitt trigger circuit, and wherein the ramp generator produces a voltage ramp which alternately increases and decreases linearly with time, and wherein the Schmitt trigger circuit receives the voltage ramp and produces the clock signal and the timing signal dependent upon the voltage ramp;

[0036] FIG. 6 is a timing diagram which illustrates the signal waveforms within the VCO embodiment of FIG. 5 for n=1;

[0037] FIG. 7 is a block diagram of a serial data transceiver testing system including a test unit coupled to a transceiver under test, wherein the test unit is used to measure the amount of jitter within a serial data stream produced by the transmitter;

[0038] FIG. 8 is a timing diagram which illustrates the operation of the serial data transceiver testing system of FIG. 7; and

[0039] FIG. 9 is a block diagram of an alternate embodiment of the VCO of FIG. 4, wherein the VCO includes an odd number of pairs of non-inverting and inverting logic blocks arranged in a recirculating loop and a control unit, wherein the control unit issues delay control signals which alter the delays of the logic blocks in order to produce the clock signal and to vary the duty cycle of the timing signal.

[0040] While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

[0041] FIG. 3 is a block diagram of one embodiment of a serial data transceiver 30 of the present invention. Transceiver 30 includes a transmitter 32 and a receiver 34 formed upon a single monolithic semiconductor substrate. Transceiver 30 also includes a transmit data input port, a pair of polarized transmitter output terminals, a pair of polarized receiver input terminals, a receive data output port, a reference clock terminal, and a control terminal. Transmitter 32 receives parallel data from the transmit data input port, converts the parallel data to a serial data stream (i.e., serializes the parallel data), and differentially drives the pair of polarized transmitter output terminals with complementary voltage values representing the logic values of the serial data stream. Receiver 34 receives differentially-driven voltage values representing logic values of a serial data stream from the pair of polarized receiver input terminals, converts the serial data stream to parallel data (i.e., deserializes the serial data stream), and provides the parallel data at the receive data output port.

[0042] Transmitter 32 includes a serializer 36 and an output buffer 38. Serializer 36 receives parallel data at the transmit data input port in response to a reference clock signal received at the reference clock terminal. The parallel data is supplied in n-bit data units, where n is an integer greater than 1. Common data units include 8-bit “bytes”, 16-bit “words”, and 32-bit “double words”. A clock generator within serializer 36 uses the reference clock signal to produce a transmit clock signal which has a frequency times the frequency of the reference clock signal. Serializer 36 serializes the parallel data in response to the transmit clock signal producing a serial data stream, and provides output buffer 38 with the logic values of the serial data stream. The serial data stream includes data windows separated by data transition periods. As the data transitions occur at intervals equal to the period of the transmit clock signal, the transmit clock signal is inherently present within the serial data stream. Output buffer 38 differentially drives the pair of polarized transmitter output terminals with complementary voltage values representing the logic values of the serial data stream.

[0043] Receiver 34 includes an input buffer 40 and a deserializer 42. Input buffer 40 receives a differentially-driven serial data stream from between the pair of polarized receiver input terminals and provides the corresponding logic values of the serial data stream to deserializer 42. Deserializer 42 recovers the transmit clock signal used to transmit the serial data from the serial data stream, generates a timing signal based upon the recovered transmit clock signal, samples the serial data stream using the timing signal in order to recover the data from the serial data stream, aligns the deserialized data into parallel units, and provides the resulting parallel data to the receive data output port.

[0044] The data sampling time within each data window is dependent upon the duty cycle of the timing signal. In order to facilitate measurement of the amount of jitter present within a serial data stream produced by transmitter 32, deserializer 42 also receives a control signal at the control terminal. Deserializer 42 varies the duty cycle of the timing signal in response to the control signal in order to change the sampling time within the data windows. As will be described in more detail below, the ability to change the sampling time within the data windows via the control signal facilitates measurement of the amount of jitter present within the serial data stream.

[0045] FIG. 4 is a block diagram of one embodiment of deserializer 42. In the embodiment of FIG. 4, deserializer 42 includes a PLL circuit having a phase comparator 44, a loop filter 46, a VCO 48, and a divide-by-n circuit 49. Deserializer 42 also includes an edge-triggered latch 50. Phase comparator 44 receives a serial data stream from input buffer 40 and a frequency-divided Q₁′ signal produced by divide-by-n circuit 49 . Phase comparator 44 produces an a.c. error signal having a short term average value substantially proportional to the phase difference between the frequency-divided Q₁′ signal and the serial data stream. Loop filter 46 receives the a.c. error signal and produces a low pass filtered error signal substantially proportional to the short term average value of the a.c. error signal. Loop filter 46 may be, for example, a low pass filter. VCO 48 produces the Q₁′ output signal and a complementary Q₁output signal in response to the filtered error signal. The Q₁′ output signal is n times the transmit clock signal recovered from the serial data stream, where n is an integer greater than or equal to 1 as described below. The complementary Q₁output signal is a timing signal used to sample the serial data stream. The frequencies of the Q₁′ and Q₁output signals are thus dependent upon the filtered error signal and the number n. Divide-by-n circuit 49 receives the Q₁′ output signal and divides the frequency of the Q₁′ output signal by a number n, where n is an integer greater than or equal to 1, producing the frequency-divided Q₁′ signal. Edge-triggered latch 50 recovers the serial data from the serial data stream using the Q₁output signal. Edge-triggered latch 50 samples the serial data stream (at a data or “D” input) upon the rising edge of the Q₁output signal (at a clock signal or “C” input), producing sampled serial data at a Q₂output.

[0046] VCO 48 also receives the control signal via the control terminal. As will be described in more detail below, VCO 48 varies the duty cycle of the Q₁output signal (i.e., the serial data stream sampling time within the data windows) dependent upon the value of the control signal in order to facilitate measurement of the amount of jitter present within the serial data stream.

[0047] FIG. 5 is a block diagram of one embodiment of VCO 48. In the embodiment of FIG. 5, VCO 48 includes a ramp generator 52 coupled to a Schmitt trigger circuit 54. Ramp generator produces a voltage ramp at an output terminal. The voltage ramp alternately increases and decreases linearly with time. Schmitt trigger circuit 54 receives the voltage ramp and produces output signals Q₁and Q₁′, which vary between two discrete voltage levels, dependent upon the value of the voltage ramp. As with all Schmitt trigger circuits, a graph of the output voltage at the Q₁or Q₁′ terminal versus the input voltage reveals different switching points (i.e., threshold values) for positive-going and negative-going inputs.

[0048] In the embodiment of FIG. 5, ramp generator 52 includes a current source 56 coupled to a capacitor 58. Current source 56 produces an output current “I” at an output terminal dependent upon the value of the filtered error signal produced by loop filter 40, the current values of output signals Q₁and Q₁′, and the control signal from the control terminal. Capacitor 58 is coupled between the output terminal of current source 56 and a ground potential. Capacitor 58 integrates the current produced by current source 56 with time, producing the voltage ramp at the output terminal. If the output current “I” produced by current source 56 is a constant, the value of the voltage ramp at time “t” is given by:

[0049] V(t)=(I/C)·t

[0050] where:

[0051] V(t)=value of voltage ramp at time “t”, and

[0052] C=capacitance of capacitor 58

[0053] FIG. 6 is a timing diagram which will be used to describe the operation of the embodiment of VCO 48 shown in FIG. 5 for n=1. Current “I” produced by current source 56 alternates between two constant values +I₁and −I₂. When output signal Q₁′ is a logic high, current source 56 produces current “I” with a value of +I₁. When output signal Q₁is a logic high, current source 56 produces current “I” with a value of −I₂. Capacitor “C” integrates current “I” with time to form linear voltage ramp “V”. Voltage ramp “V” is positive-going when output signal Q₁′ is a logic high, and negative-going when output signal Q₁is a logic high. Schmitt trigger circuit 54 receives voltage ramp “V” and produces output signals Q₁and Q₁′ in response to the value of voltage ramp “V”. When voltage ramp “V” is positive-going, and attains a first threshold value of V₁, Schmitt trigger circuit 54 switches output signal Q₁′ from a logic high to a logic low, and switches complementary output signal Q₁from a logic low to a logic high. When voltage ramp “V” is negative-going, and attains a second threshold value of V₂, Schmitt trigger circuit 54 switches output signal Q₁′ from a logic low to a logic high, and switches complementary output signal Q₁from a logic low to a logic high.

[0054] The periods and duty cycles of the Q₁and Q₁′ waveforms are determined by the relationship between values I₁and I₂. For example, if output signal Q₁′ is a logic high for a time period t₁while voltage ramp “V” is positive going, then a logic low for a time period t₂while voltage ramp “V” is negative going,

[0055] P=period of the Q₁′ waveform=t₁+t₂=C·(V1−V2)·(1/I₁+1/I₂)

[0056] D=duty cycle of the Q₁′ waveform=t₁/(t₁+t₂)=1/(1+I₁/I₂)

[0057] Current source 56 adjusts the values of I₁and I₂:(i) in response to the filtered error signal produced by loop filter 40 in order to maintain the periods of the Q₁and Q₁′ waveforms equal to the time interval between data transitions within the serial data stream, and (ii) in response to the control signal in order to alter the duty cycles of the Q₁and Q₁′ waveforms. The duty cycle of the Q₁waveform determines the data sampling time within each data window between data transitions within the serial data stream. As will be described in more detail below, the duty cycle of the Q₁waveform is altered via the control signal in order to measure the “width” of the data window between data transitions. The width of the data window between data transitions is then used to determine the amount of jitter within the serial data stream.

[0058] FIG. 7 is a block diagram of a serial data transceiver testing system 59 including a test unit 60 coupled to transceiver 30 (i.e., the transceiver under test). Test unit 60 is used to measure the amount of jitter within a serial data stream produced by transmitter 32 of transceiver 30. Test unit 60 includes a parallel data generator 62 and a parallel data comparator 64. During testing, test unit 60 generates the reference clock and control signals and provides the reference clock and control signals to transceiver 30. Parallel data generator 62 generates parallel input test data and provides the parallel input test data to the transmit data input port of transceiver 30. Transmitter 32 serializes the parallel input test data and differentially drives the pair of polarized transmitter output terminals with complementary voltage values representing the logic values of the resultant serial data stream. The polarized transmitter output terminals are coupled to the corresponding receiver input terminals. Receiver 34 of transceiver 30 receives the complementary voltage signals produced by transmitter 32, recovers the transmit clock signal from the corresponding serial data stream, samples the serial data stream in response to the control signal, aligns the resulting deserialized data into parallel units, and provides the resulting parallel test output data at the receive data output port.

[0059] As a first step during testing, test unit 60 may simply verify proper operation of transceiver 30. In order to accomplish this, test unit 60 may produce the control signal such that receiver 34 samples the serial data stream substantially midway between data transitions within the serial data stream. Parallel data generator 62 generates parallel input test data and provides the parallel input test data to the transmit data input port of transceiver 30. Parallel data comparator 64 receives the parallel output test data produced by transceiver 30 and the parallel input test data produced by parallel data generator 62. Parallel data comparator 64 compares the parallel output test data to the parallel input test data. A match between the parallel output test data and the parallel input test data (i.e., a one-to-one correspondence between the logic levels of the bit positions of the parallel output test data and the parallel input test data) verifies proper operation of transceiver 30.

[0060] FIG. 8 is a timing diagram which will be used to describe the operation of serial data transceiver testing system 59. The value of the control signal produced by test unit 60 causes receiver 34 of transceiver 30 to sample the serial data stream at time t_Sbetween a first data transition 66 and a second data transition 68. Following operational verification of transceiver 30, test unit 60 varies (i.e., increases or decreases) the value of the control signal such that receiver 34 samples the serial data stream closer and closer to first data transition 66 (i.e., earlier within each data window). The value of the control signal is preferably proportional to the sampling time t_Swithin the data window or “eye” between first data transition 66 and second data transition 68. Parallel data comparator 64 receives the parallel output test data produced by receiver 34 of transceiver 30 and the parallel input test data produced by parallel data generator 62. Parallel data comparator 64 compares the parallel output test data to the parallel input test data. A match between the parallel output test data and the parallel input test data reveals the absence of jitter at sampling time t_Swithin the data eye. In the absence of jitter, test unit 60 continues to vary (i. e., increase or decrease) the value of the control signal such that receiver 34 samples the serial data stream closer to first data transition 66. When the parallel output test data no longer matches the parallel input test data, jitter has been encountered in the serial data stream and a “leading edge” of the data eye has been located. Test unit 60 records the corresponding value of sampling time t_S1for future use.

[0061] Once test unit 60 has determined the value of t_S1, test unit 60 varies (i.e., decreases or increases) the value of the control signal such that receiver 34 samples the serial data stream closer and closer to second data transition 68 (i.e., later within each data window). Parallel data comparator 64 continues to compare the parallel output test data produced by receiver 34 of transceiver 30 to the parallel input test data, and a match between the parallel output test data and the parallel input test data signifies the absence of jitter at sampling time t_Swithin the data eye. In the absence of jitter, test unit 60 continues to vary (i.e., decrease or increase) the value of the control signal such that receiver 34 samples the serial data stream closer to second data transition 68. When the parallel output test data no longer matches the parallel input test data, jitter has again been encountered in the serial data stream and a “trailing edge” of the data eye has been located. Test unit 60 records the corresponding value of sampling time t_S2for future use.

[0062] Once test unit 60 has determined the values of t_S1and t_S2, test unit 60 determines the width of the data eye, preferably by simply subtracting the recorded value of t_S1from the recorded value of t_S2. Test unit 60 then determines the amount of jitter in the serial data stream produced by transmitter 32 of transceiver 30 (i.e., transmitter jitter) by subtracting the data eye width from the period of the transmit clock signal (i.e., the “bit time” of the serial data stream). As described above, the transmit clock signal has a frequency n times the frequency of the reference clock signal provided by test unit 60, where n is the number of bits per data unit. Thus the bit time of the serial data stream is 1/n times the period of the reference clock signal.

[0063] FIG. 9 is a block diagram of an alternate embodiment of VCO 48. In the embodiment of FIG. 9, VCO 48 includes m pairs of non-inverting and inverting logic units (i.e., logic “blocks”) connected in series to form a recirculating loop, where m is an odd number and twice the number of bits per data unit. Such a configuration resembles a ring oscillator. In FIG. 9, VCO 48 includes three block pairs 70a-c.Each block pair includes a non-inverting block 72 and an inverting block 74. Each logic block is coupled to a control unit 76, and has a variable time delay responsive to a delay control signal issued by control unit 76. Control unit 76 issues the delay control signals to the logic blocks in response to the filtered error signal from loop filter 40, the control signal from the control terminal, and the Q₁and Q₁′ output signals. For example, assume non-inverting blocks 72a-chave a variable delay of d₁and inverting blocks 74a-chave a variable delay of d₂. Control unit 76 adjusts the nominal values of d₁and d₂in response to the filtered error signal produced by loop filter 40 in order to maintain the periods of the Q₁and Q₁′ waveforms equal to the time interval between data transitions within the serial data stream. Control unit 76 also varies d₁and d₂between minimum and maximum values in response to the control signal in order to alter the duty cycles of the Q₁and Q₁′ waveforms. Control unit 76 alters the duty cycle of the Q₁waveform in response to the control signal in order to facilitate measurement of the data eye width and transmitter jitter as described above. For example, in response to the control signal, control unit 76 may reduce the duty cycle of the Q₁waveform by increasing the values of d₁and d₂when output signal Q₁′ is a logic high and reducing the values of d₁and d₂when output signal Q₁is a logic high.

[0064] It will be appreciated by those skilled in the art having the benefit of this disclosure that this invention is believed to be a serial data transceiver architecture and test method for measuring the amount of jitter within a serial data stream. Furthermore, it is also to be understood that the form of the invention shown and described is to be taken as exemplary, presently preferred embodiments. Various modifications and changes may be made without departing from the spirit and scope of the invention as set forth in the claims. It is intended that the following claims be interpreted to embrace all such modifications and changes.