Method and apparatus for controlling power level during BIST

[0002] The present invention generally relates to digital circuits and, more specifically, to a mechanism for modifying the power consumption and noise conditions of a digital circuit (or system) under test. It is more specifically applicable to circuits implementing built-in self-test (BIST).

[0003] The behavior of a circuit under test is often modified to increase the level of activity of all its components to facilitate testing of the circuit. However, the reconfigured circuit might consume an average amount of power that is significantly higher from that measured during normal operation for the same clock frequency. This is especially true when the circuit is tested at high-speed to detect defects that might cause delay faults, for example. Excessive power consumption due to the increased circuit activity (or toggle rate) can damage the circuit itself or the test equipment and it can also invalidate the results of the test.

[0004] The additional stress caused by a controlled amount of additional power consumption can, however, be used to evaluate the reliability of the circuit. It allows the temperature of the circuit to be increased without requiring additional equipment (e.g. hot chuck, furnace). The elevated temperature is known to reduce the performance of a circuit. This kind of test is used to screen circuits that must be able to function at high temperature.

[0005] Jaber et al U.S. Pat. No. 5,614,838 discloses a reduced power apparatus and method for testing high speed components. The method is only applicable to a specific type of circuit known as Level-Sensitive Scan Design (LSSD), where separate clock sources are needed to control the circuit in normal and test modes of operation. Even though the patentee claims that the method is applicable to other types circuits, it is neither obvious nor practical to use the method for circuits other than LSSD circuits. In general, only one clock is available for controlling normal and test modes of operation (e.g. multiplexed scan). Therefore, it is not possible to gate the clock during the shift operations. Also, the method does not allow adjustment of the level of power consumption, which might invalidate the performance test results.

[0006] The present invention is used in combination with BIST methods for controlling the amount of power consumption of a digital circuit or system under test. Since the power level can, in many cases, be made proportional to the test clock or frequency for a given set of environmental conditions such as supply voltage and temperature, the present invention proposes a flexible programmable clock control mechanism allows the average power consumption to be set by suppressing clock pulses during the phases of the test that do not require the maximum level of activity. In other phases of the circuit where the performance of the circuit is being evaluated, no clock pulses are suppressed so that the conditions are close as possible, if not identical, to the normal mode of operation. The programmability is necessary in order to test the circuit under various sets of conditions that occur at different times in the life cycle of the circuit under test (e.g. wafer probe, package test, board manufacturing, system burn-in, field maintenance) using only available system clocks.

[0007] The present method is compatible with Phase-Locked Loop (PLLs) used to synchronize the circuit with other circuits of the system and as a clock multiplier. The method can also be used with several known BIST methods such as those disclosed in U.S. Pat. Nos. 5,329,533 (Lin), 4,503,537 (McAnney), 5,349,587 (Nadeau-Dostie et al), 4,969,148 (Nadeau-Dostie et al) and co-pending application Ser. No. 08/752,499 (Nadeau-Dostie et al), incorporated herein by reference. For each of these methods, there is an interval of time in which the clock should not be suppressed in order to evaluate the performance of the circuit under test is or can be generated.

[0008] One aspect of the present invention is generally defined as an improvement in a method of testing a digital circuit or system, having a plurality of scannable memory elements, in accordance with conventional BIST methods in which, at a reference clock, a test stimulus is shifted into the memory elements, the response of the elements is captured and the captured data is shifted out of the elements and analyzed, the improvement comprising controlling the average power consumption of the circuit during the test by suppressing clock pulses from the reference clock during phases of the test that do not require the maximum level of activity or in which the performance of the circuit is not to be evaluated; and, suppressing no clock pulses from the reference clock in phases of the test in which the performance of the circuit is to be evaluated, so that the conditions are substantially as those of normal mode of operation of the circuit.

[0009] Another aspect of the present invention is generally defined as a clock controller for use during testing of a digital circuit or system, comprising means responsive to a reference clock applied to the controller for generating a test clock signal for use by the digital circuit; the means including means responsive to a first value of a test phase signal for periodically suppressing clock cycles from the reference clock so as to operate the circuit a lower power level than a maximal power level and responsive to a second value of the test phase signal for not suppressing clock cycles from the reference clock so as to operate the circuit at the frequency of the reference clock.

[0010] These and other features of the invention will become more apparent from the following description in which reference is made to the appended drawings in which:

[0011] FIG. 1 diagrammatically illustrates a portion of a digital circuit including core logic, a test controller and a clock controller according to a preferred embodiment of the present invention;

[0012] FIG. 2 diagrammatically illustrates a clock controller according to a preferred embodiment of the invention;

[0013] FIG. 3 is a state diagram for a clock controller according to a preferred embodiment of the invention;

[0014] FIG. 4 is a timing illustrating the operation of the clock controller according to a preferred embodiment of the invention; and

[0015] FIG. 5 is a flow chart illustrating the various steps in the operation of the clock controller according to a preferred embodiment of the invention.

[0016] FIG. 1 diagrammatically illustrates a portion of a digital circuit 10 having a circuit core logic 12, a test controller 14, a clock controller 16, an optional Phase-Lock Loop (PLL) 18 and a multiplexer 20. Core logic 12 implements the system functions during the normal mode of operation of the circuit and includes scannable memory elements, not shown but well known in the art, into which a test stimulus may be shifted, the response of the memory elements captured, shifted-out and analyzed in accordance with conventional BIST methods. The core logic is connected to a clock distribution tree 22 to optimize the performance of the circuit. The clock distribution tree, in turn, is provided with a clock signal, CKC, generated by clock controller 16, as explained later.

[0017] Test controller 14 is provided to enable performance testing of the circuit. It is also connected to the clock distribution tree 22. When several clocks are used during normal operation, the test controller can derive additional clocks from the branch of the clock distribution tree having the highest frequency.

[0018] Clock controller 16 provides the clock signal that is used by the core logic and the test controller. Clock controller 16 receives a clock input CKI from either a reference clock 24 or from the optional Phase-Lock Loop 18 and outputs clock signal, CKC, as previously mentioned. Clock controller 16 also receives a DutyCycle input signal and a TestPhase input signal. A multiplexer 20 is controlled by a Test Mode signal, TM, and is operable to select between the output of the PLL and the output of the clock controller and apply the selected signal to the PLL.

[0019] The PLL 18 is an optional component of the circuit. However, PLLs are common in high-performance circuits. A PLL has been included to show that the feedback path 23 used to synchronize the core logic with the reference clock must be modified during test mode. Since the method of adjusting the power level involves the suppression of clock pulses, the PLL would not lock onto a stable frequency during the test mode, invalidating the performance test results. The different feedback path would cause the core logic to no longer be in phase with the reference clock. However, this is not important during test mode.

[0020] It will be understood by those skilled in the art that the reference clock and the signal fed back from the end of the clock distribution tree should be synchronized. This may be achieved by providing an additional multiplexer or other such means. However, inasmuch as this feature does not form part of the invention, it has not been illustrated and is not described further.

[0021] The TestPhase signal is either low (0) and high (1). A low TestPhase input indicates that the power level is to be adjusted to the fraction of the power level specified by the DutyCycle input signal. A high TestPhase signal indicates that the circuit is to be operated at the frequency of the reference clock signal applied to the clock controller and generally indicates that a burst of clock pulses is required to measure the performance of the circuit. The number of clock cycles is usually relatively small, in the order of 2 to 8 clock cycles, so that the average power consumption of the circuit is not affected. However, the transients and noise conditions which arise during the performance test measurement are comparable to those which would occur during normal operation of the circuit.

[0022] The DutyCycle signal is representative of the desired power level to be applied to the circuit during non-performance critical phases or portions of a test. The DutyCycle signal is encoded as a binary number that represents a desired fraction of the maximal power level. The maximal power is expressed as 2^kso that the smallest fraction of the maximal power level is expressed as 2^−k, where k is an integer. Thus, k bits are used to encode the power level in 2^−kincrements. The number of bits, k, is chosen to accommodate requirements in terms of resolution and dynamic range of the power level.

[0023] By way of example, if is desired to perform one phase of a test at ¼ of the maximal power, DutyCycle would be set to 01, and k would be set to 2 so that the maximal power would be 4 (2²). The DutyCycle code may be loaded into a register (not shown) designed into the circuit, it may be input to the circuit prior to a test or it may be generated internally of the circuit by the test controller during a test.

[0024] FIG. 2 shows a more detailed view of clock controller 16. Clock controller 16 is comprised of a simple finite-state machine, called a duty cycle generator 26, an AND gate 28, a transparent latch 30 and an OR gate 32. Duty cycle generator 26 provides an output signal, CKOFF, and is comprised of a counter and a comparator. The counter and comparator are illustrated in the block diagram of FIG. 5 described below. The counter has the same number of bits, k, as the DutyCycle input. In the example mentioned earlier in which it was desired to perform a test of one phase at ¼ of maximal power, the counter would be two-bit counter. The counter is initialized to 0 before a test begins and whenever TestPhase goes high. The various sequence of steps in the operation of the clock controller may be best understood by referring to FIG. 5 described hereinbelow.

[0025] The first step 40, determines whether TestPhase is high or low. In general, when TestPhase is low, the power level is to be adjusted to the fraction specified by DutyCycle and the counter continuously cycles through counting from 0 to 2^k−1. Thus, if k is 2, as in the above example, the counter counts from 0 to 3 continuously until this cycle is broken by TestPhase going high.

[0026] The first step 42 which is executed after TestPhase goes low is to determine whether the count is less than or equal to the DutyCycle. If it is, the clock is enabled by setting CKOFF equal to 0 at step 44, which outputs a clock pulse. When the count exceeds the value of DutyCycle, the clock is disabled by setting CKOFF equal to 1 as indicated at step 46, which suppresses a clock pulse. In either case, the counter then increments at step 50 and its new value is compared at step 52 with its maximum value, MaxCount, which in the example is 3. When the value is less than or equal to MaxCount, the process returns to step 42 and the cycle repeats. When the count exceeds MaxCount, the count is re-initialized to 0 at step 54 and then returns to step 40 where the clock controller determines whether the value of TestPhase has changed.

[0027] Thus, when DutyCycle is 01, one output pulse would be generated for every four pulses of the reference clock and the other three would be suppressed. If DutyCycle was assigned the binary value of 11 (2), two consecutive output pulses would be generated and they would be followed by the suppression of two consecutive pulses.

[0028] When TestPhase goes high, the counter is re-initialized to 0 at step 56 and remains at that value for as long as TestPhase is high. In addition, CKOFF is set to 0 at step 58, which enables the clock and results in an output pulse for each pulse of the reference clock. Thus, as long as TestPhase remains high, the clock controller will output a clock signal at the same frequency as the reference clock. The behavior of the duty cycle generator is also precisely summarized in the state diagram of FIG. 3.

[0029] The timing diagram in FIG. 4 further illustrates the example in which two bits are used to encode the power level and the desired power level is ¼ of the maximum power level (DutyCycle=01). As can be seen, while TestPhase is low, the counter (Count) counts from 0 to 3 continuously, enabling the clock for one cycle out of every four cycles of the reference clock until TestPhase becomes 1. The latter forces the counter to return to 0 and results in a burst of consecutive clock cycles. TestPhase also enables the clock by forcing the output of the AND gate to 0. TestPhase remains high for as long as consecutive clock cycles are required by the test controller. Once TestPhase goes back to low, the counter resumes its cycle. In general non-performance critical phases of an internal test are performed at the lower power, lower frequency mode (TestPhase low). These phases would include, for example, Scan-In and Scan-Out operations, and the like. Performance critical operations, such a Capture operations, are performed at the frequency of the reference or test clock applied to the clock controller.

[0030] Thus, the present invention provides an improved method of testing digital circuits by controlling the average power consumption of the circuit during the test using a single reference clock. This is achieved by suppressing clock pulses from the test or reference clock during phases of the test that do not require the maximum level of activity or in which evaluation of the performance of the circuit is not to be evaluated; and, by not suppressing clock pulses from the reference clock in phases of the test in which the performance of the circuit is to be evaluated so that the conditions are substantially as those of normal mode of operation of the circuit.

[0031] It will be seen that the above described method and circuit allows performance testing to be performed concurrently with normal testing of the circuit using only one reference clock input during testing.

[0032] There are two important timing considerations to take into account in the implementation of this invention. First, the TestPhase signal should always be generated using the falling edge of the clock CKC, as shown by the vertical dashed line in FIG. 4, to maximize the time within which the TestPhase signal can propagate from the test controller to the clock controller (i.e. one full period of the reference clock).

[0033] Second, the use of a transparent latch prevents potential glitches from occurring at the clock output CKC. On the rising edge of the clock, CKI, the clock output CKC is set to 1 irrespective of the current state of transparent latch 30. Then, the latch is made transparent to allow new values of TestPhase and CKOFF to propagate through the latch. Due to potentially long propagation delays from the test controller to the clock controller, the value at the D input and Q output of the transparent latch might not be stable, but these possible glitches are masked by the fact that CKI is 1 at the input of the OR gate. Therefore, the output clock CKC remains at 1. However, the D input of the transparent latch must be stable on the falling edge of the clock CKI which will latch its value. This value will determine whether a low-going clock pulse will be produced at clock output CKC.

[0034] It should be understood that the features of the clock controller can be integrated with other features requiring control of the clock. Specifically, it is easy to add a mechanism that will stop the clock independently of the state of the counter for diagnostic purposes. It might also be necessary to be able to choose from a multiplicity of input clocks to be applied to CKI input of the clock controller, again for diagnostic purposes. All of these variations are within the scope of this invention.