Static series voltage regulator

[0002] This is a continuation-in-part of copending application(s). Ser. No. 08/372,485 filed on Jan. 13, 1995 now abandoned.

[0003] The present invention relates generally to electrical distribution switchgear, and, more particularly, to a voltage regulator for buffering loads from momentary voltage dips on utility grids.

[0004] In the past, electric power consumers ignored service interruptions of less than three seconds. With the increasing use of digital computer equipment electric power consumers are becoming less tolerant of short term voltage dips and sags. These disturbances cause flashing clock displays, resets to VCRs and personal computers, and lost production on automated assembly lines and businesses that rely on computer networks. Voltage sags and voltage dips are two closely related problems. Voltage sag is a partial reduction in the magnitude of voltage and voltage dip describes a situation wherein the magnitude of the voltage phasor drops significantly, often to zero. Voltage sags often persist for extended periods and are usually related to system loading conditions, while voltage dips generally occur for brief durations and are caused by faults on the power system. In either case, it is desirable to support the voltage to prevent service interruption and inconvenience.

[0005] One source of complaints regarding power quality are single phase disturbances on the transmission and distribution network. Most utility distribution system disturbances are single phase events. These disturbances may have relatively long durations because ground faults can require several seconds to clear on some distribution feeders. Balanced three phase disturbances are generally less common. Major three phase voltage dips are primarily due to closing into grounded equipment, but generally last only a few cycles. Less severe voltage sags occur during transient conditions following energization of large loads or during recovery from a major network disturbance. The latter events can last for a second or more. Uninterruptible power supply is a good technical solution it is expensive especially when a large load area is to be served. Accordingly it will be appreciated that it would be highly desirable to have a relatively inexpensive voltage regulator that boosts voltage during voltage dips and sags and supports the load during severe unbalanced voltage disturbances.

[0006] The present invention is directed to overcoming one or more of the problems set forth above. Briefly summarized, according to one aspect of the invention, a static series voltage regulator for an electrical distribution system comprises a voltage source inverter having a dc input and an ac output; a source bridge, fed from a power source, supplying the dc input of the inverter; a series transformer connected between the power source and a load coupling the inverter output to appear between the power source and the load; and control means for controlling operation of the inverter so that during normal operation the inverter acts as a short on the series transformer. During a power supply fault that causes a dip in the source voltage, the inverter output is injected in series with the source voltage to provide a boost action to maintain load voltage at a desired magnitude and balance.

[0007] A relatively simple 3-phase voltage source inverter is used instead of separate inverters for each phase. A second inverter and series transformer may be connected in series and coordinated to synchronize their sampling and computation cycles so that the effective pulse width modulation (PWM) carrier frequency is doubled for more efficient boost action.

[0008] According to another aspect of the invention, a method for regulating voltage applied to a load from a power distribution transformer by providing a boost action from a static series voltage regulator includes measuring a voltage V_Tat an output of the power transformer: measuring a load current I_LMEASdrawn by the load; constructing what load voltage V_LXwould be, using V_Tand I_LMEAS, in absence of a boost action (V_LXcompensating for impedance drop of the static series voltage regulator itself); processing the load voltage V_LXthrough a minimum dip detector and obtaining a signal V_LXMthat rapidly responds to a voltage dip while remembering a dip happened for a predetermined period of time; and beginning a boost action when V_LXMfalls below a preselected threshold voltage and bringing the load voltage V_LXto a desired level V_LORDLER.

[0009] The static series voltage regulator senses the incoming voltage from the utility and load current. From these is constructed what the load voltage would be in the absence of boost action. This information is processed through a minimum detector to obtain a signal V_LXMwhich rapidly responds to a voltage dip but remembers a dip happened for a few cycles. When V_LXMfalls below some threshold, then boosting begins to bring load voltage to a desired level. Boosting is halted after V_LXMexceeds the threshold, or when the load voltage exceeds a high voltage threshold.

[0010] These and other aspects, objects, features and advantages of the present invention will be more clearly understood and appreciated from a review of the following detailed description of the preferred embodiments and appended claims, and by reference to the accompanying drawings.

[0011] FIG. 1 is a block diagram of a preferred embodiment of an electric power distribution system incorporating a static series voltage regulator (SSVR) according to the present invention and illustrating a feeder fault scenario defining SSVR performance requirements.

[0012] FIGS. 2-3 graphically illustrate the performance scenario during a fault without the SSVR.

[0013] FIGS. 4-5 graphically illustrate the performance scenario with the SSVR.

[0014] FIG. 6 shows the performance of the SSVR in terms of lowest load voltage as a function of voltage on the faulted phase.

[0015] FIG. 7 is a single-line diagram of the static series voltage regulator of FIG. 1.

[0016] FIG. 8 is diagram of a thyristor controlled bridge.

[0017] FIG. 9 is a diagram of a voltage source bridge.

[0018] FIG. 10 is a diagram of a hybrid bridge.

[0019] FIG. 11 is a block diagram of the control portion of the SSVR.

[0020] FIG. 12 illustrates the abc and dq reference frames for the abc-dq transformation.

[0021] FIG. 13 is a block diagram of the voltage boost function of the control portion of the SSVR.

[0022] FIGS. 14-15 graphically illustrate the response of the voltage boost function variables to a single phase fault on the supply system.

[0023] FIG. 16 is a block diagram illustrating SSVR control processing delays and a phase lead block to compensate for the delays.

[0024] FIG. 17 is a block diagram of the flux offset control.

[0025] FIGS. 18-19 graphically illustrate flux offset control performance.

[0026] FIGS. 20-21 illustrate the different operating points for FIG. 7, in which the source bridge is connected to the power supply side of the SSVR.

[0027] FIGS. 22-23 illustrate the different operating points for a single-line diagram of FIG. 1, wherein the source bridge is connected to the load side of the SSVR.

[0028] The followings are a list of the reference numbers as used in the drawings and the corresponding element names of those numbers:

[0029] Referring to FIG. 1, a static series voltage regulator (SSVR) 10 is installed in an electric power distribution system 12 to protect a load 14 on a feeder branch 16 from voltage dips. The SSVR is installed between the load 14 and the Y-side of a Δ-Y distribution transformer 18. A circuit breaker 20 connects the feeder 16 to the Δ-side of the transformer 18 and to the substation transformer 22 via a grounded transformer bus 24. Other branch feeder 26, 28, 30, 32 are shown with a time overcurrent relay 34 for overcurrent protection. The typical performance criterion which determines SSVR design involves a single phase fault on a feeder, such as feeder 32, which when cleared in normal relay time will leave the load with full 3-phase power from an unfaulted source.

[0030] The minimum load voltage for this event is established by the Computer Business Equipment Manufacturers Association (CBEMA). The minimum load voltage is related to fault voltage level using CBEMA data and curves and relay characteristics and is given in the following Table 1 for typical settings of time overcurrent protection and for faults of varying impedance.

[0031] Table 1 is based upon General Electric Company relay type GE IAC 77, 6 amp tap=960 amps, 30-cycle trip @ tap 5 (4760 amps). The governing case is a solid fault, cleared in 0.2 seconds, where the CBEMA guideline establishes a minimum load voltage of 79%. For longer faults, the CBEMA requirement rises to 87%, but the source voltage is considerably higher.

[0032] FIGS. 2-3 illustrate the performance scenario during a fault without the SSVR. During the feeder fault, the load voltage drops on two phases to approximately 57% (FIG. 2), and below 48% (not shown) on one line-to-line voltage. To create a meaningful measure to compare performance criterion, the load voltages are rectified and filtered. This is shown in FIG. 3 where the bottom two traces represent the unfiltered average of the three individual rectified phase voltages (one trace is for line-to-neutral voltages, the other for the line-to-line voltages). The top trace represents the average of the two lower signals, with a 1 ms low pass filter applied. It is this total averaged and filtered trace that is to be compared to the CBEMA criterion, because its minimum represents the lowest of the individual phase-to-neutral or phase-to-phase voltages on the load. The bottom trace of FIG. 2 shows the load voltage and the top trace of FIG. 3 shows load current.

[0033] FIGS. 4-5 illustrate the performance scenario with the SSVR. The load voltage is now above approximately 83% after the initial half cycle, well above the 79% required by CBEMA for this case. The voltage boost, V_LT, provided is seen on the two phases needing support (FIG. 4). This voltage is nearly a square wave, indicating that the inverter is providing all the boost it can in this condition. The bottom trace of FIG. 5 represents the variables on the dc link of the power electronic packages. The lowest trace is the current being drawn out of the dc link via the inverter to support the voltage boost. The middle trace is the current being supplied to the dc link by the rectifier. The top trace is the dc link voltage. Upon initial boosting, the inverter current is drawn mostly from the dc capacitor, causing its voltage to drop. After a few cycles, a steady state is attained where the ac voltage in the healthy phases is sufficient to drive current through the rectifier and recharge the dc capacitor each half cycle. This condition will persist until the fault is cleared.

[0034] FIG. 6 shows the performance of the SSVR in terms of lowest load voltage as a function of supply voltage on the faulted phase. This figure shows that any fault cleared in less than 0.5 seconds will meet the CBEMA criterion. Any fault having a voltage above 10% will meet the CBEMA criterion, no matter how long the fault persists.

[0035] Referring now to FIG. 7, the SSVR 10 is shown in greater detail in a single-line diagram. The basic approach is to use measurements of transformer voltage, load current, load voltage, and dc voltage to calculate a voltage boost to improve load voltage response to single phase faults on the supply system. The basic components of the SSVR 10 are a first 3-phase voltage source inverter 36 with a simple source bridge 38 and a crowbar circuit 40 to protect the voltage source inverter 36. bridge 38 may be a simple rectifier bridge as shown or may be thyristor controlled 38 (FIG. 8), or a voltage source rectifier 38 (FIG. 9) or a hybrid brige 38 containing simple rectifiers bridge 38 and thyristor controlled 38 rectifiers (FIG. 10) to better regulate the de link. The source bridge is shown to be connected to the power supply side of the SSVR, but may also be connected to the load side of the SSVR as illustrated and discussed in reference to FIGS. 22 and 23. The operating currents and voltages for both connections are explained in more detail in reference to FIGS. 20-23. A first series transformer 42 couples the inverter output to appear between the load 14 and source 18. A second series transformer 44 couples a second inverter 46 between the source 18 and load 14 downstream of the first inverter 36. Bypass and isolation switches, such as circuit breakers 48, 50, 52, are provided for protection, and a surge filter 54, preferably containing a capacitor 56 connected across the series transformers 42, 44, protect load equipment from fast front voltage steps produced by the voltage source inverters 36, 46. The filter 54 draws high frequency current through the series transformers, which, in turn, attenuates the voltage steps before they appear in the load circuit. A microprocessor based controller 58 coordinates the two voltage source inverters 36, 46 to synchronize their sampling and computation cycles so that the effective pulse width modulation (PWM) carrier frequency is doubled. For example, if the sampling rate and PWM carrier frequency in each drive is 3 kHz, then by synchronizing them in an offset manner, the net effective PWM carrier frequency is shifted to 6 kHz.

[0036] FIG. 11 is a block diagram of the controller 58 showing input signal processing at block 60, a phase locked loop synchronization at block 62, and rectified, filtered actual load voltage magnitude at block 64 combining for a boost action at block 66. Minimum and maximum boost orders are given at summer 68 where components of boost order from a flux offset control 70 are input. The final boost order is given at 72 and received by a signal processor 74 which inputs the final boost order to the firing time logic 76 to deliver the firing signals. In FIG. 11 the quantities are defined as follows:

[0037] V_TAB,BC=measured line voltages (volts).

[0038] V_TD,Q=d-, q-components of line voltage (pu).

[0039] Θ_PLL=PLL angle (rad).

[0040] C_VSIA,B,C=inverter current (amps).

[0041] C_VSID,Q=d-, q-components of inverter current (pu).

[0042] V_LORD=desired load voltage (pu, def=1.0 pu).

[0043] V_LOADAB,BC=measured load voltage (volts).

[0044] V_LOADMG=rectified, filtered actual load voltage magnitude (pu).

[0045] V_DC=measured dc voltage (pu).

[0046] V_LTDOO,LTQOO=d-, q-components of boost voltage order (pu).

[0047] D_VLTFD,Q=d-, q-components of boost order from flux offset control (pu).

[0048] V_LTDMN,LTQMN=d-, q-components of minimum boost order (pu, def=−2 pu).

[0049] V_LTDMX,LTQMX=d-, q-components of minimum boost order (pu, def=2 pu).

[0050] V_LTDO,LTQO=d-, q-components of limited boost order (pu).

[0051] V_SIPUD,Q=d-, q-components of final boost order (pu).

[0052] V_SIPUA,B,C=final boost order (pu).

[0053] U_DCMDA,B,C=firing signals.

[0054] FIG. 12 shows the abc and dq reference frames 97 and 98, respectively for the abc to dq transformation. This is an application of standard vector control principles well known in the art. The following equations described the transformations between the abc reference frame and the dq reference frame.

[0055] abc-dq:

[0056] V_d=⅔[(V_a−V_b)cos Θ−(V_b−V_c)cos(Θ+120°)].

[0057] V_q=−⅔[(V_a−V_b)sin Θ−(V_b−V_c)sin(Θ+120°)].

[0058] dq-abc:

[0059] V_a=V_dcos Θ−V_qsin Θ.

[0060] V_b=V_dcos(Θ120°)−V_qsin(Θ−120°).

[0061] V_c=V_dcos(Θ+120°)−V_qsin(Θ+120°).

[0062] FIG. 13 is a block diagram of the voltage boost function. The transformer voltage, V_TD,Q, voltage source inverter current, C_VSID,Q, (equivalent to the load current with appropriate scaling by the series transformer turns ratio), and series transformer leakage impedance, R_LT, X_LT, are used to calculate the voltage at the load without any boost. This inferred load voltage, V_LDXUF, V_LQXUF, is processed through a lead-lag compensator 78, 80 to compensate for control delays. The minimum inferred voltage, V_LDXFLis detected with a minimum peak detector 82 that immediately follows voltage decreases but follows increases through a low pass filter. The minimum inferred load voltage signal, V_LDXFL, as well as several voltage thresholds are used to determine the voltage boost orders, V_LTDOO, V_LTQOO. In FIG. 13 the quantities are defined as follows:

[0063] C_VSID,Q=d-, q-components of inverter current (pu).

[0064] V_TD,Q=d-, q-components of line voltage (pu).

[0065] R_LT=series transformer leakage resistance (pu).

[0066] X_LT=series transformer leakage reactance (pu).

[0067] V_LDXUF,LQXUF=d-, q-components of inferred load voltage (pu).

[0068] V_LDX,LQX=d-, q-components of compensated inferred load voltage (pu).

[0069] V_LDXFL=d-component of minimum inferred load voltage (pu).

[0070] V_LORD=desired load voltage (pu, def=1.0 pu).

[0071] V_MIN=minimum load voltage threshold to boost (pu).

[0072] V_HYSL=threshold hysteresis (pu, def=0.02 pu).

[0073] V_LOADMG=rectified, filtered actual load voltage magnitude (pu).

[0074] V_NBST=no boost threshold (pu, def=1.02 pu).

[0075] V_LTDOO,LTQOO=d-, q-components of boost voltage order (pu).

[0076] For a minimum inferred load voltage V_LDXFLless than a voltage threshold V_MIN, the voltage boost orders are set to the compensated inferred voltage V_LDX. When the load voltage recovers to a value greater than V_MINplus some voltage hysteresis V_HYSL, the voltage boost becomes zero. The voltage boost is also zero for an actual load voltage magnitude greater than a second voltage threshold V_NBST. This prevents boosting at high actual load voltages when the inferred voltage output of the minimum peak detector is still low due to the low pass filter.

[0077] FIGS. 14-15 show the response of the voltage boost function variables to a single phase fault on the supply system. The dc components of transformer voltage and inverter current are nominally 1.0 pu, as is the filtered inferred load voltage. At 20 msec, a single phase fault is applied. This results in a 120 Hz modulation on the various signals due to the abc/dq transformation of negative sequence components. The final voltage boost variable V_LTDOO, V_LTQOOillustrates the boost function's response to this fault.

[0078] The boost function requires an additional phase lead block 84 to compensate for the input and output processing delays 86, 88 inherent in the SSVR control. FIG. 16 illustrates these SSVR control processing delays. The lead-lag compensation 84 was selected to minimize the overall error at 120 Hz.

[0079] After a boost action, the SSVR transformer may be left with an offset flux condition. To minimize this offset, the controller 58 includes a function whereby the flux transitions are remembered and slow action is taken after the main boost event to bring the flux back toward midrange. FIG. 17 is a block diagram of the flux offset control. In FIG. 17 the quantities are defined as follows:

[0080] V_LTDO,LTQO=d-, q-components of limited boost order (pu).

[0081] V_{LTOA,LTOB,LTOC}=a-, b-, c-components of limited boost order (pu).

[0082] Θ_PLL=phase angle error (rad).

[0083] ψ_{LTOA,LTOB,LTOC}=a-, b-, c-components of series transformer core flux (pu)

[0084] K_FLXOFF=proportional gain.

[0085] DV_LTFD,Q=d-, q-components of flux offset control boost contribution (pu).

[0086] DV_LTFA,B,C=a-, b-, c-components of flux offset control boost contribution (pu).

[0087] The flux offset control starts at block 90 with dq-abc transformation on the commanded inverter voltages, V_LTDO,LTQO, to get back to the three individual phases, V_{LTOA,LTOB,LTOC}. These are input to integrator 92 to predict fluxes, ψ_{LTOA,LTOB,LTOC}, on the transformer cores for the three individual phases. The controller generates correction signals as signals proportional to these fluxes via gain K_FLXOFFin proportional gain control 94. These are transformed back to the vector dq coordinates of the regulator at block 96 and summed into the final voltage order (in summer 68 of FIG. 11) with a minus sign. By closing this loop, the signal DV_LTFwill continue to have an average value as long as the flux is offset. In steady state, the flux can have no offset because of the action of the integrator 92 and gain control 94. The gain control 94 determines how quickly flux offset is nulled.

[0088] FIGS. 18-19 illustrate the benefit of using the flux offset control. These figures show key variables of the coupling transformer during the boost operation generally described in conjunction with FIGS. 4-5. FIG. 18 represents a case without the flux offset control, while FIG. 19 is the same event with the flux offset control enabled. In each figure, the top set of three traces represents the magnetic flux in the iron core of the three phases of the transformer. The bottom set of three traces represents the magnetizing current drawn from the voltage source inverter to support this level of flux. Ideally, the transformer core flux would remain below this saturation level so that the magnetizing current would be negligible compared to the load current. When significant magnetizing current is drawn, the performance of the voltage regulator suffers. The transformer coupling is reduced, and the added current loading on the inverter can cause it to shut down when it is most needed for its primary function.

[0089] It is clear from FIGS. 18-19 that the flux offset control provides tremendous improvement in reducing the magnetizing current, by bringing the average component of flux towards zero rather than allowing it to remain near one extreme after the initial response of the boost control. As a practical matter, this function ensures more reliable operation, and also economy by minimizing the required amount of iron needed in the transformer core.

[0090] Other factors, such as the positioning of the source bridge (item 38 in FIG. 7), also help to maximize the performance and the economy of the SSVR. Two different positions of the source bridge 38 and the resulting operating currents and voltages are shown in FIGS. 20-23. Specifically, in FIGS. 20-21 the source bridge 38 is connected to the power supply side of the SSVR, and in FIGS. 22-23 the source bridge 38 is connected to the load side of the SSVR.

[0091] As shown in FIG. 20, the system is operating in the normal state with the power supply providing normal rated 1.0 pu voltage. In the normal state, the SSVR is not required to provide a voltage boost, thus the boost voltage is zero (V_B=0). Rated current (1.0 pu) is being drawn from the power supply. This current is simultaneously being carried by the inverter in its freewheeling state. The current provided to the source bridge 38 (configured as a rectifier bridge in this example) is zero (I_R=0) because there is no boost being provided. In FIG. 21, the power supply suffers a voltage loss of 50% of its rated voltage (V_S=0.5 pu). The SSVR creates a boost of V_B=0.5 pu to bring the load voltage back up to rated voltage (V_L=1.0 pu). The current drawn from the power supply is now 2.0 pu, providing 1.0 pu current to the source bridge 38. However, because the source bridge 38 is connected to the power supply, it receives the power supply's depressed voltage, which, since the source bridge is preferably a rectifier bridge or simple diode, depresses the de link voltage to 50%. This, in turn, depresses the ac output voltage of the inverter to 50% (V_VSI=0.5 pu). Consequently, the turns ratio of the transformer 42 is set for this condition, namely 1:1.

[0092] In FIG. 22, the system is again operating in the normal state (i.e., V_B=0). The source bridge 38 is now connected to the load side of the SSVR. As in the previous example, rated current is being drawn from the power supply and the current provided to the source bridge 38 is zero (I_R=0). When the power supply voltage is depressed to 50%, as shown in FIG. 23, the SSVR will again produce the boost voltage needed to keep the load at its rated voltage. In this case, since the load is sustained at its rated voltage, and since the source bridge 38 is now connected to the load, the system is able to sustain a rated voltage on the de link. Consequently, the inverter 36 now produces rated output voltage (V_VSI=1.0 pu). Thus, the turns ratio of the series transformer 42 need only be 0.5:1 for this circuit, that is, only 0.5 turns are needed to create the required 50% boost voltage with the 100% inverter voltage. Furthermore, the current through the inverter I_VSIis only half the load current. As part of the change in the system, the current in the inverter will rise during the boost period. In this case, the current in the SSVR must double because it carries the full source current. Thus, when the source bridge is connected to the load side of the SSVR, the inverter current I_VSIvaries with load-side source bridge 38, rather than the voltage V_VSIvarying and the inverter current I_VSIstaying constant as shown with the supply-side source bridge.

[0093] It can now be appreciated that there has been presented a static, series voltage regulator that boosts voltage during voltage dips and sags and supports the load during severe unbalanced voltage disturbances. Operation of the SSVR involves sensing the incoming voltage from the utility, as measured at the transformer terminals and load current, I_LMEAS. The load current I_LMEASis defined as the current which passes through the series transformer of the SSVR. This current is proportional to the inverter current C_VSI(also referred to as I_VSI) according to the turns ratio of the series transformer. Since the load current is typically measured through the inverter, it will be subsequently referred to in terms of C_VSIor I_VSI. From the measured V_Tand I_LMEAS, the next step is constructing what the load voltage would be in the absence of boost action (V_LX, compensating for the impedance drop of the SSVR itself). This information is processed through a minimum detector to obtain a signal V_LXMwhich rapidly responds to a voltage dip but remembers a dip happened for a few cycles. When V_LXMfalls below some threshold (e.g., 0.87 to 0.95 pu), then boosting begins to bring load voltage to a desired level (V_LORDER, typically=1.0). Boosting is halted after V_LXMhas been above the threshold plus hysteresis (e.g., 0.02 pu), or when the load voltage V_LMEASexceeds a high voltage threshold (e.g., 1.05 pu).

[0094] After a boost action, the SSVR transformer may be left with an offset flux condition, depending upon the exact timing of the boost requirements. To minimize this offset, the controls include a function whereby the flux transitions are remembered and slow action is taken after the main boost event to bring the flux back toward midrange. When boosting under certain fault timing considerations, it is possible to drive the SSVR series transformer into saturation. If this were ignored, performance would be at risk. The control features included in the SSVR include this consideration. Where a feeder fault occurs at a voltage zero, rather than at crest, an examination of the transformer flux and magnetizing current would indicate that there is an initial offset flux condition, but that the controller acts to limit the magnetizing current on the first cycle, then to reset the flux to prevent further saturation during the boost transient. The result is that the voltage is held above the criterion for the entire transient.

[0095] While the invention has been described with particular reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements of the preferred embodiments without departing from invention. For example, other source bridges and hybrid bridges are possible other than then ones illustrated and described.

[0096] As is evident from the foregoing description, certain aspects of the invention are not limited to the particular details of the examples illustrated, and it is therefore contemplated that other modifications and applications will occur to those skilled the art. It is accordingly intended that the claims shall cover all such modifications and applications as do not depart from the true spirit and scope of the invention.