US 6,326,291 B1Grant
Fabrication of a wide metal silicide on a narrow polysilicon gate structure
Issue Date:2001-12-04
•20 Claims
•8 Drawing Sheets
Abstract
For fabricating a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the MOSFET has a drain region, a source region, and a channel region, and the MOSFET initially has a gate comprised of a capping layer on a polysilicon gate structure disposed on a gate dielectric. A drain silicide is formed in the drain region, and a source silicide is formed in the source region. The drain and source silicides have a first silicide thickness. A first dielectric layer is conformally deposited over the drain region, the source region, and the gate and is polished down until the capping layer of the gate is exposed such that the capping layer and the first dielectric layer are substantially level. A top portion of the first dielectric layer is etched away until sidewalls at a top portion of the polysilicon gate structure are exposed. The capping layer on the polysilicon gate structure of the gate is etched away such that the top of the polysilicon gate structure is exposed. A silicidation metal is deposited to cover the top and the sidewalls of the top portion of the polysilicon gate structure that is exposed. A silicidation anneal is performed with the silicidation metal and the top portion of the polysilicon gate structure to form a gate silicide having a second silicide thickness on top of the polysilicon gate structure. Because the gate silicide is formed from the top and the sidewalls of the top portion of the polysilicon gate structure, the gate silicide has a width that is larger than the width of the polysilicon gate structure. In addition, the gate silicide is formed in a separate step from the step for forming the drain silicide and the source silicide such that the gate silicide may have a larger thickness and be comprised of different metal silicide material from that of the drain silicide and the source silicide.
Metadata
Assignee
- Advanced Micro Devices, Inc.
Inventor
- Bin Yu
Application Information
Application Number:US 09/808,839
Filing Date:2001-03-15
Priority Date:2000-06-26
Art Unit:7
Classifications
IPC:
H01L 213205
Field of Search:
438592438303438595438596
Patent Drawings (8 sheets)
Description
[0002] This is a continuation-in-part of an earlier filed copending patent application, with Ser. No. 09/603,046 filed on Jun. 26, 2000, for which priority is claimed. This earlier filed copending patent application with Ser. No. 09/603,046 is in its entirety incorporated herewith by reference.
Technical Field
[0003] This invention relates to MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and more particularly to fabrication of a wide metal silicide on a narrow polysilicon gate structure of a MOSFET for a gate with low series resistance for MOSFETs with scaled down dimensions.
Background of the Invention
[0004] Referring to FIG. 1, a cross sectional view of a conventional MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 includes a drain region 102, a source region 104, and a channel region 106 fabricated on an insulating layer 107 disposed over a semiconductor substrate 108 for SOI (silicon-on-insulator) technology, as known to one of ordinary skill in the art of electronics. A gate dielectric 110 is disposed over the channel region 106 of the MOSFET 100. The MOSFET 100 also includes a gate comprised of a polysilicon gate structure 112 disposed over the gate dielectric 110. Spacer structures 113 typically formed of an insulating material surround the gate dielectric 110 and the polysilicon gate structure 112, as known to one of ordinary skill in the art of electronics. Isolation dielectric structures 120 electrically isolate the MOSFET 100 from other devices fabricated on the insulating layer 107.
[0005] For making contact to the drain region 102, the source region 104, and the polysilicon gate structure 112 of the gate, a metal silicide is formed on the drain region 102, the source region 104, and the polysilicon gate structure 112 of the gate. A drain silicide 114 is formed on the drain region 102, a source silicide 116 is formed on the source region 104, and a gate silicide 118 is formed on the polysilicon gate structure 112 of the gate of the MOSFET 100.
[0006] For efficiency in fabrication, the drain silicide 114, the source silicide 116, and the gate silicide 118 are typically fabricated simultaneously in the prior art. During the fabrication of the silicides, the drain region 102, the source region 104, and the polysilicon gate structure 112 are exposed, and metal is deposited on those regions. Then, a silicidation anneal is performed, and the drain silicide 114, the source silicide 116, and the gate silicide 118 form from a reaction of the deposited metal with silicon during the silicidation anneal. Thus, in the prior art, the drain silicide 114, the source silicide 116, and the gate silicide 118 have substantially the same thickness and is comprised of substantially the same metal silicide material.
[0007] However, as structures of the MOSFET are modified with advancement in technology, it may be desired that the thickness of the drain silicide 114 and the source silicide 116 be different from the thickness of the gate silicide 118. In addition, it may be desired that the metal silicide material for the drain silicide 114 and the source silicide 116 be different from the metal silicide material of the gate silicide 118.
[0008] For example, a long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is to enhance the speed performance of the integrated circuit. Thus, the MOSFET 100 is fabricated with SOI (silicon-on-insulator) technology whereby the drain region 102, the source region 104, and the channel region 106 are fabricated on the insulating layer 107 to eliminate junction capacitance, as known to one of ordinary skill in the art of electronics. Because the drain region 102 and the source region 104 are fabricated directly on the insulating layer 107, the depth of the drain region 102 and the source region 104 may be limited. In that case, the thickness of the drain silicide 114 and the source silicide 116 in turn are limited. On the other hand, a large thickness of the gate silicide 118 is desired for minimizing the resistance at the gate of the MOSFET and in turn for maximizing the speed performance of the MOSFET.
[0009] In addition, another long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
[0010] Referring to FIG. 1, as the dimensions of the MOSFET 100 are scaled down, a smaller thickness is desired for the drain silicide 114 and the source silicide 116 to minimize small channel effects of the MOSFET, as known to one of ordinary skill in the art. On the other hand, a large thickness of the gate silicide 118 is desired for minimizing the resistance at the gate of the MOSFET and in turn for maximizing the speed performance of the MOSFET.
[0011] Some metal silicides, such as nickel silicide (NiSi2), are more amenable for forming a thin metal silicide. Thus, it may be desired that the drain silicide 114 and the source silicide 116 be comprised of nickel silicide (NiSi2). Other metal silicides, such as cobalt silicide (CoSi2) or titanium silicide (TiSi2), are more amenable for forming a thick metal silicide. Thus, it may be desired that the gate silicide 118 be comprised of cobalt silicide (CoSi2) or titanium silicide (TiSi2) while the drain silicide 114 and the source silicide 116 may be comprised of nickel silicide (NiSi2) such that the gate silicide 118 is comprised of a different metal silicide material from that of the drain silicide 114 and the source silicide 116.
[0012] Furthermore, with scaling down of the dimensions of the polysilicon gate structure 112 of the MOSFET, the volume of the gate silicide 118 is also scaled down resulting in higher series resistance at the gate of the MOSFET 100. Such higher series resistance degrades the speed performance of the MOSFET.
[0013] Thus, a gate silicide is desired to have a larger thickness than that of the drain silicide and the source silicide, and to be comprised of a metal silicide material that may be different from that for the drain silicide and the source silicide. In addition, a gate silicide is desired to have a larger width than that of the narrow polysilicon gate structure in a MOSFET with scaled down dimensions.
Summary of the Invention
[0014] Accordingly, the present invention is directed to a separate step for fabrication of the gate silicide from the step for fabrication of the drain silicide and the source silicide such that the gate silicide may have a different thickness and be comprised of different metal silicide material from that of the drain silicide and the source silicide. In addition, the gate silicide is formed from the top and the sidewalls of a top portion of a polysilicon gate structure that is exposed such that the gate silicide has a larger width that the width of the narrow polysilicon gate structure in a MOSFET with scaled down dimensions.
[0015] In a general aspect of the present invention, in a method for fabricating a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the MOSFET has a drain region, a source region, and a channel region, and the MOSFET initially has a gate comprised of a capping layer on a polysilicon gate structure disposed on a gate dielectric over the channel region. A drain silicide is formed in the drain region, and a source silicide is formed in the source region. The drain silicide and the source silicide have a first silicide thickness. A first dielectric layer is conformally deposited over the drain region, the source region, and the gate. The first dielectric layer is polished down until the capping layer of the gate is exposed such that the capping layer and the first dielectric layer are substantially level.
[0016] A top portion of the first dielectric layer is etched away until sidewalls at a top portion of the polysilicon gate structure are exposed. The capping layer on the polysilicon gate structure of the gate is etched away such that the top of the polysilicon gate structure is exposed. A silicidation metal is deposited to cover the top and the sidewalls of the top portion of the polysilicon gate structure that is exposed. A silicidation anneal is performed with the silicidation metal and the top portion of the polysilicon gate structure to form a gate silicide having a second silicide thickness on top of the polysilicon gate structure.
[0017] In this manner, because the gate silicide is formed from the top and the sidewalls of the top portion of the polysilicon gate structure, the gate silicide has a width that is larger than the width of the polysilicon gate structure. In addition, the gate silicide is formed in a separate step from the step of forming the drain silicide and the source silicide such that the gate silicide may have a larger thickness and be comprised of different metal silicide material from that of the drain silicide and the source silicide. The larger width and the larger thickness of the gate silicide results in minimized resistance at the gate of the MOSFET for enhanced speed performance of the MOSFET.
[0018] These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.
Brief Description of the Drawings
[0019] FIG. 1 shows a cross sectional view of a conventional MOSFET of the prior art;
[0020] FIGS. 2, 3, 4, 5, 6, 7, 8, 9, 10, and 11 show cross sectional views of a MOSFET of an embodiment of the present invention, with a separate step for fabrication of the gate silicide from the step for fabrication of the drain silicide and the source silicide, and with addition of polysilicon spacers to the polysilicon gate for fabrication of a gate silicide having a larger width than the width of the narrow polysilicon gate structure in a MOSFET with scaled down dimensions; and
[0021] FIGS. 12, 13, 14, 15, 16, 17, 18, 19, 20, and 21 show cross sectional views of a MOSFET of another embodiment of the present invention, with a separate step for fabrication of the gate silicide from the step for fabrication of the drain suicide and the source silicide, and with formation of the gate silicide from the top and the sidewalls of a top portion of the polysilicon gate structure such that the gate silicide has a larger width than the width of the narrow polysilicon gate structure in a MOSFET with scaled down dimensions.
[0022] The figures referred to herein are drawn for clarity of illustration and are not necessarily drawn to scale. Moreover, the figures referred to herein show a MOSFET that is typically part of a larger integrated circuit. Elements having the same reference number in FIGS. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, and 21 refer to elements having similar structure and function.
Detailed Description
[0023] Example embodiments of the present invention are described for forming drain and source suicides and a gate silicide of a MOSFET in SOI (semiconductor on insulator) technology. However, the present invention may also be applied for forming drain and source silicides and a gate silicide for a MOSFET in a conventional semiconductor substrate, as would be apparent to one of ordinary skill in the art of integrated circuit fabrication from the description herein.
[0024] Referring to FIG. 2, a MOSFET 200 of an embodiment of the present invention includes a drain region 202, a source region 204, and a channel region 206 fabricated on an insulating layer 207 in SOI (silicon-on-insulator) technology. The insulating layer 207 is deposited on a semiconductor substrate 208, and the drain region 202, the source region 204, and the channel region 206 are fabricated on the insulating layer 207 to minimize junction capacitance, as known to one of ordinary skill in the art of electronics. However, the present invention may also be practiced when the drain region 202, the source region 204, and the channel region 206 are fabricated within the semiconductor substrate 208.
[0025] A first type of dopant within the drain region 202 and the source region 204 may be an N-type dopant, and a second type of dopant within the channel region 206 may be a P-type dopant, for fabricating an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor). Alternatively, the first type of dopant within the drain region 202 and the source region 204 may be a P-type dopant, and a second type of dopant within the channel region 206 may be an N-type dopant, for fabricating a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor).
[0026] A gate dielectric 210 is disposed over the channel region 206 of the MOSFET 200. The gate dielectric 210 is comprised of silicon dioxide (SiO2) or silicon nitride (Si3N4) in one embodiment of the present invention. In an alternative embodiment of the present invention, the gate dielectric 210 is comprised of a high dielectric constant material having a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO2) to minimize undesired tunneling current through the gate dielectric 210 of the MOSFET 200. Processes for forming such a gate dielectric 210 are known to one of ordinary skill in the art of integrated circuit fabrication.
[0027] The MOSFET 200 also includes a gate comprised of a polysilicon gate structure 212 disposed over the gate dielectric 210. Spacer structures 214 typically formed of an insulating material surround the gate dielectric 210 and the polysilicon gate structure 212, as known to one of ordinary skill in the art of electronics. A capping layer 216 comprised of a hardmask material such as siliconoxynitride (SiON) is disposed over the top of the polysilicon gate structure 212. Isolation dielectric structures 218 electrically isolate the MOSFET 200 from other devices fabricated on the insulating layer 207.
[0028] Referring to FIG. 2, a drain silicide 220 and a source silicide 222 having a first silicide thickness are formed in the drain region 202 and the source region 204, respectively, of the MOSFET 200. Processes for formation of the drain silicide 220 in the drain region 202 and the source silicide 222 in the source region 204 are known to one of ordinary skill in the art of integrated circuit fabrication.
[0029] The drain silicide 220 and the source silicide 222 are formed to have a relatively small thickness in the drain region 202 and the source region 204, respectively. Such small thickness minimizes undesired short channel effects when the MOSFET 200 has scaled down dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication. In addition, the small thickness for the drain silicide 220 and the source silicide 222 is desired such that the drain silicide 220 and the source silicide 222 do not reach down to the insulating layer 207 within the drain region 202 and the source region 204, respectively, in SOI (silicon-on-insulator) technology. The drain silicide 220 and the source silicide 222 are preferably comprised of a metal silicide, such as nickel silicide (NiSi2), that is amenable for formation of a relatively thin metal silicide.
[0030] The capping layer 216 prevents formation of any metal silicide in the polysilicon gate structure 212 during formation of the drain silicide 220 in the drain region 202 and the source silicide 222 in the source region 204. Referring to FIG. 3, for formation of a gate silicide having a relatively large width and thickness, according to an embodiment of the present invention, a first dielectric layer 230 having a thickness in a range of from about 4000 Å (angstroms) to about 6000 Å (angstroms) is deposited over the drain region 202, the source region 204, and the gate of the MOSFET 200. The first dielectric layer 230 is comprised of a dielectric material such as silicon dioxide (SiO2) for example.
[0031] Referring to FIG. 4, the first dielectric layer 230 over the drain region 202, the source region 204, and the gate is polished down until the capping layer 216 is exposed such that the capping layer 216 and the dielectric layer 230 are substantially level. The capping layer 216 which is typically comprised of a hardmask material such as siliconoxynitride (SiON) may act as the stopping layer in the polishing process. Processes for thus polishing the first dielectric layer 230, such as (CMP) chemical mechanical polishing, are known to one of ordinary skill in the art of integrated circuit fabrication.
[0032] Referring to FIG. 5, the capping layer 216 is etched away to expose the top of the polysilicon gate structure 212. In addition, a top portion of the first dielectric layer 230 is etched away such that sidewalls 232 of the polysilicon gate structure 212 at the top portion of the polysilicon gate structure 212 are exposed. Processes for etching away the capping layer 216, which may be comprised of siliconoxynitride for example, and the first dielectric layer 230, which may be comprised of silicon dioxide (SiO2) for example, are known to one of ordinary skill in the art of integrated circuit fabrication.
[0033] Referring to FIGS. 5 and 6, polysilicon spacers 234 are formed at the exposed sidewalls 232 at the top portion of the polysilicon gate structure 212. Processes for formation of such polysilicon spacers 234 such as a deposition and etch-back process are known to one of ordinary skill in the art of integrated circuit fabrication.
[0034] Referring to FIGS. 6 and 7, a silicidation metal 236 is deposited to cover the top of the polysilicon gate structure 212 and the polysilicon spacers 234. The silicidation metal 236 is used for forming the gate silicide. Referring to FIGS. 7 and 8, the silicidation metal is etched away substantially from the first dielectric layer 230 such that the silicidation metal remains to cover the top of the polysilicon gate structure 212 and the polysilicon spacers 234. Processes for deposition and patterning and etching of the silicidation metal 236, such as when the silicidation metal 236 is comprised of cobalt or titanium, are known to one of ordinary skill in the art of integrated circuit fabrication.
[0035] Referring to FIGS. 8 and 9, a silicidation anneal is performed with the silicidation metal 236 reacting with the polysilicon gate structure 212 that is exposed above the dielectric layer 230 and with the polysilicon spacers 234 to form a gate silicide 240 having a second silicide thickness on top of the polysilicon gate structure 212. Silicidation anneal processes are known to one of ordinary skill in the art of integrated circuit fabrication.
[0036] With the additional polysilicon spacers 234 extending beyond the sidewalls 232 of the polysilicon gate structure 212, the width of the gate silicide 240 is larger than the width of the polysilicon gate structure 212. This feature is especially advantageous for MOSFETs having scaled down dimensions in the tens of nanometers. A wider gate silicide 240 results in a higher volume of silicide which minimizes the resistance at the gate of the MOSFET 200 to enhance the speed performance of the MOSFET 200.
[0037] In addition, comparing the gate silicide 240 to the drain silicide 220 and the source silicide 222, the second silicide thickness of the gate silicide 240 is relatively larger than the first silicide thickness of the drain silicide 220 and the source silicide 222. Referring to FIG. 5, the thickness of the gate silicide 240 may be determined by controlling the height of the polysilicon gate structure 212 that is exposed after the top portion of the first dielectric layer 230 is etched away. The second silicide thickness of the gate silicide 240 is controlled to be larger than the first silicide thickness of the drain silicide 220 and the source silicide 222. Such thicker gate silicide 240 is advantageous for minimizing resistance at the gate of the MOSFET 200 to enhance the speed performance of the MOSFET 200.
[0038] In addition, the gate silicide 240 is comprised of a metal silicide material, such as cobalt silicide (CoSi2) or titanium silicide (TiSi2), that is more amenable for formation of a thick metal silicide. Referring to FIG. 7, the silicidation metal 236 is cobalt or titanium in one embodiment of the present invention.
[0039] In this manner, because the gate silicide 240 is formed in a separate step from the step for formation of the drain silicide 220 and the source silicide 222, the gate suicide 240 may be formed to have larger thickness than that of the drain suicide 220 and the source silicide 222. In addition, with such separate fabrication steps, the gate silicide may be comprised of a different metal silicide than that for the drain silicide 220 and the source silicide 222. By addition of the polysilicon spacer 234 to the sidewalls 232 of the polysilicon gate structure 212 of the gate, the gate silicide has a width that is larger than the width of the polysilicon gate structure 212.
[0040] The drain silicide 220 and the source silicide 222 are relatively thin such that short channel effects may be minimized in the MOSFET 200 having scaled down dimensions. At the same time, the gate silicide 240 is relatively thick and wide to minimize gate resistance at the gate of the MOSFET 200 to enhance the speed performance of the MOSFET 200.
[0041] Referring to FIGS. 10 and 11, for formation of interconnect to the gate silicide, a second dielectric layer 250 is deposited over the gate silicide 240 and over the first dielectric layer 230. A gate interconnect 252 is formed on the second dielectric layer 250, and the gate interconnect 252 is conductively coupled to the gate silicide 240 with a gate via 254.
[0042] In addition, a drain interconnect 256 is formed on the second dielectric layer 250, and the drain interconnect 256 is conductively coupled to the drain silicide 220 with a drain via 258. Similarly, a source interconnect 260 is formed on the second dielectric layer 250, and the source interconnect 260 is conductively coupled to the source silicide 222 with a source via 262. Processes for formation of interconnects and vias are known to one of ordinary skill in the art of integrated circuit fabrication.
[0043] For forming a MOSFET 300 according to another embodiment of the present invention, referring to FIGS. 2 and 12, after formation of the drain and source silicides 220 and 222 that are relatively thin in FIG. 2, the spacer structures 214 are etched away from the polysilicon gate structure 212. Processes for etching away the spacer structures 214 which may be comprised of silicon dioxide (SiO2) for example, are known to one of ordinary skill in the art of integrated circuit fabrication.
[0044] Referring to FIG. 13, for formation of a gate silicide having a relatively large width and thickness, according to this embodiment of the present invention, a first dielectric layer 270 having a thickness in a range of from about 3000 Å (angstroms) to about 5000 Å (angstroms) is conformally deposited over the drain region 202, the source region 204, and the gate of the MOSFET 300. The first dielectric layer 270 is comprised of a dielectric material such as silicon dioxide (SiO2) for example. Processes for depositing such a first dielectric layer 270 are known to one of ordinary skill in the art of integrated circuit fabrication.
[0045] In a preferred embodiment of the present invention, the first dielectric layer 270 is deposited with a CVD (chemical vapor deposition) process using a temperature of less than about 400° Celsius. Some high dielectric constant materials of the gate dielectric 210, such as metal oxides for example, react with the channel region 206 at relatively high temperatures. The relatively low temperature of less than about 400° Celsius for depositing the first dielectric layer 270 prevents reaction of such a gate dielectric 210 with the channel region 206 to preserve the integrity of the gate dielectric 210. Such a CVD process for conformally depositing the dielectric layer 210 are known to one of ordinary skill in the art of integrated circuit fabrication.
[0046] Referring to FIG. 14, the first dielectric layer 270 over the drain region 202, the source region 204, and the gate is polished down until the capping layer 216 is exposed such that the capping layer 216 and the first dielectric layer 270 are substantially level. The capping layer 216 which is typically comprised of a hardmask material such as siliconoxynitride (SiON) may act as the stopping layer in the polishing process. Processes for thus polishing the first dielectric layer 270, such as (CMP) chemical mechanical polishing, are known to one of ordinary skill in the art of integrated circuit fabrication.
[0047] Referring to FIG. 15, a top portion of the first dielectric layer 270 is etched away such that sidewalls 272 of the polysilicon gate structure 212 at the top portion of the polysilicon gate structure 212 are exposed. Processes, such as time-controlled etching processes, for etching away the top portion of the first dielectric layer 270, which may be comprised of silicon dioxide (SiO2) for example, are known to one of ordinary skill in the art of integrated circuit fabrication.
[0048] Referring to FIGS. 2, 12, 13, 14, and 15, the spacer structures 214 are etched away before the first dielectric layer 270 is deposited because the spacers structures 214 may be comprised of an insulating material having a different density from the first dielectric layer 270, in a preferred embodiment of the present invention. The uniform density of the first dielectric layer 270 surrounding the polysilicon gate structure 212 ensures uniform polishing and etching of the dielectric material surrounding the polysilicon gate structure 212.
[0049] Referring to FIG. 16, the capping layer 216 is etched away to expose the top of the polysilicon gate structure 212. In one embodiment of the present invention, the height 274 of the top portion of the polysilicon gate structure 212 that is exposed is in a range of from about 200 angstroms to about 400 angstroms when the thickness of the drain and source silicides 220 and 222 is less than about 200 angstroms. Processes for etching away the capping layer 216, which may be comprised of siliconoxynitride for example, are known to one of ordinary skill in the art of integrated circuit fabrication.
[0050] Referring to FIG. 17, a silicidation metal 276 is conformally deposited to cover the top and the sidewalls of the top portion of the polysilicon gate structure 212. The silicidation metal 276 is used for forming the gate silicide, and may be comprised of cobalt or titanium for example. Processes for deposition of such silicidation metal 276 are known to one of ordinary skill in the art of integrated circuit fabrication.
[0051] Referring to FIG. 18, a silicidation anneal is performed with the silicidation metal 276 reacting with the polysilicon gate structure 212 that is exposed above the dielectric layer 230 to form a gate silicide 280 having a second silicide thickness on top of the polysilicon gate structure 212. The silicidation metal 276 reacts with the polysilicon gate structure 212 from the top and the sidewalls of the exposed top portion of the polysilicon gate structure 212. Silicidation anneal processes are known to one of ordinary skill in the art of integrated circuit fabrication.
[0052] Referring to FIGS. 18 and 19, after formation of the gate silicide 280, any remaining silicidation metal 276 is etched away. Processes for selectively etching away the remaining silicidation metal 276 are known to one of ordinary skill in the art of integrated circuit fabrication.
[0053] In this manner, because the silicidation metal 276 reacts with the polysilicon gate structure 212 from the top and the sidewalls of the exposed top portion of the polysilicon gate structure 212, the width of the gate silicide 280 is larger than the width of the polysilicon gate structure 212. This feature is especially advantageous for MOSFETs having scaled down dimensions in the tens of nanometers. A wider gate silicide 280 results in a higher volume of silicide which minimizes the resistance at the gate of the MOSFET 300 to enhance the speed performance of the MOSFET 300.
[0054] In addition, comparing the gate silicide 280 to the drain silicide 220 and the source silicide 222, the second silicide thickness of the gate silicide 280 is relatively larger than the first silicide thickness of the drain silicide 220 and the source silicide 222. Referring to FIG. 17, the thickness of the gate silicide 280 may be determined by controlling the height 274 of the top portion of the polysilicon gate structure 212 that is exposed after the top portion of the first dielectric layer 270 is etched away. The second silicide thickness of the gate silicide 280 is controlled to be larger than the first silicide thickness of the drain silicide 220 and the source silicide 222. Such thicker gate silicide 280 is advantageous for minimizing resistance at the gate of the MOSFET 300 to enhance the speed performance of the MOSFET 300.
[0055] In addition, the gate silicide 280 is comprised of a metal silicide material, such as cobalt silicide (CoSi2) or titanium silicide (TiSi2), that is more amenable for formation of a thick metal silicide. Referring to FIG. 17, the silicidation metal 276 is cobalt or titanium in one embodiment of the present invention.
[0056] In this manner, because the gate silicide 280 is formed in a separate step from the step for formation of the drain silicide 220 and the source silicide 222, the gate silicide 280 may be formed to have larger thickness than that of the drain silicide 220 and the source silicide 222. In addition, with such separate fabrication steps, the gate silicide 280 may be comprised of a different metal silicide than that for the drain silicide 220 and the source silicide 222. Because the silicidation metal 276 reacts with the polysilicon gate structure 212 from the top and the sidewalls of the exposed top portion of the polysilicon gate structure 212, the width of the gate silicide 280 is larger than the width of the polysilicon gate structure 212.
[0057] The drain silicide 220 and the source silicide 222 are relatively thin such that short channel effects may be minimized in the MOSFET 300 having scaled down dimensions. At the same time, the gate silicide 280 is relatively thick and wide to minimize gate resistance at the gate of the MOSFET 300 to enhance the speed performance of the MOSFET 300.
[0058] Referring to FIGS. 20 and 21, for formation of interconnect to the gate silicide 280, a second dielectric layer 282 is deposited over the gate silicide 280 and over the first dielectric layer 270. A gate interconnect 284 is formed on the second dielectric layer 282, and the gate interconnect 284 is conductively coupled to the gate silicide 280 with a gate via 286.
[0059] In addition, a drain interconnect 288 is formed on the second dielectric layer 282, and the drain interconnect 288 is conductively coupled to the drain silicide 220 with a drain via 290. Similarly, a source interconnect 292 is formed on the second dielectric layer 282, and the source interconnect 292 is conductively coupled to the source silicide 222 with a source via 294. Processes for formation of interconnects and vias are known to one of ordinary skill in the art of integrated circuit fabrication.
[0060] The foregoing is by way of example only and is not intended to be limiting. For example, any materials specified herein are by way of example only. As will be understood by those skilled in the art, the integrated circuit structures described herein may be made or used in the same way regardless of their position and orientation. Accordingly, it is to be understood that terms and phrases such as “sidewall,” “top,” “over,” and “on,” as used herein refer to the relative location and orientation of various portions of the structures with respect to one another, and are not intended to suggest that any particular absolute orientation with respect to external objects is necessary or required.
[0061] In addition, example embodiments of the present invention are described for forming drain and source silicides and a gate silicide of a MOSFET in SOI (semiconductor on insulator) technology. However, the present invention may also be applied for forming drain and source silicides and a gate silicide for a MOSFET in a conventional semiconductor substrate, as would be apparent to one of ordinary skill in the art of integrated circuit fabrication from the description herein.
[0062] The invention is limited only as defined in the following claims and equivalents thereof.
Claims
I claim:
1. A method for fabricating a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), said MOSFET having a drain region, a source region, and a channel region, and said MOSFET initially having a gate comprised of a capping layer on a polysilicon gate structure disposed on a gate dielectric over said channel region, the method including steps of:
A. forming a drain silicides in said drain region and forming a source silicide in said source region, said drain suicide and said source silicide having a first silicide thickness formed in a first silicidation anneal;
wherein said MOSFET initially includes dielectric spacers disposed on sidewalls of said polysilicon gate structure, and wherein said drain silicide is formed with said drain region exposed to a side of said dielectric spacers during said first silicidation anneal, and wherein said source silicide is formed with said source region exposed to a side of said dielectric spacers during said first silicidation anneal;
and wherein said capping layer on said polysilicon gate structure prevents formation of a silicide on said polysilicon gate structure during said first silicidation anneal;
B. depositing a first dielectric layer over said drain region, said source region, and said gate;
C. polishing down said first dielectric layer until said capping layer of said gate is exposed such that said capping layer and said first dielectric layer are substantially level;
D. etching away a top portion of said first dielectric layer until sidewalls at a top portion of said polysilicon gate structure are exposed;
E. etching away said capping layer on said polysilicon gate structure of said gate such that the top of said polysilicon gate structure is exposed;
F. depositing a silicidation metal to cover the top and said sidewalls of said top portion of said polysilicon gate structure that is exposed; and
G. performing a second silicidation anneal with said silicidation metal and said top portion of said polysilicon gate structure to form a gate silicide having a second silicide thickness on top of said polysilicon gate structure;
wherein said gate silicide has a width that is larger than a width of said polysilicon gate structure of said gate.
2. The method of claim 1, wherein said drain silicide and said source silicide are comprised of a different material from said gate silicide.
3. The method of claim 2, wherein said drain silicide and said source silicide are comprised of nickel silicide (NiSi2), and wherein said gate silicide is comprised of one of cobalt silicide (CoSi2) or titanium silicide (TiSi2).
4. The method of claim 1, wherein said first silicide thickness of said drain suicide and said source suicide is smaller than said second silicide thickness of said gate silicide.
5. The method of claim 1, wherein said first silicide thickness of said drain and source suicides is less than about 200 angstroms, and wherein said top portion of said polysilicon gate structure has a height in a range of from about 200 angstroms to about 400 angstroms.
6. The method of claim 1, further including the steps of:
depositing a second dielectric layer over said gate silicide and over said first dielectric layer; and
forming a gate interconnect on said second dielectric layer, wherein said gate interconnect is conductively coupled to said gate silicide with a gate via through said second dielectric layer.
7. The method of claim 6, further including the steps of:
forming a drain interconnect on said second dielectric layer, wherein said drain interconnect is conductively coupled to said drain silicide with a drain via through said second dielectric layer and said first dielectric layer; and
forming a source interconnect on said second dielectric layer, wherein said source interconnect is conductively coupled to said source silicide with a source via through said second dielectric layer and said first dielectric layer.
8. The method of claim 1, wherein a first type of dopant within said drain region and said source region is an N-type dopant, and wherein a second type of dopant within said channel region is a P-type dopant for fabricating an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor).
9. The method of claim 1, wherein a first type of dopant within said drain region and said source region is a P-type dopant, and wherein a second type of dopant within said channel region is an N-type dopant for fabricating a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor).
10. A method for fabricating a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), said MOSFET having a drain region, a source region, and a channel region, and said MOSFET initially having a gate comprised of a capping layer on a polysilicon gate structure disposed on a gate dielectric over said channel region, the method including steps of:
A. forming a drain silicide in said drain region and forming a source silicide in said source region, said drain silicide and said source silicide having a first silicide thickness;
B. depositing a first dielectric layer over said drain region, said source region, and said gate;
C. polishing down said first dielectric layer until said capping layer of said gate is exposed such that said capping layer and said first dielectric layer are substantially level;
D. etching away a top portion of said first dielectric layer until sidewalls at a top portion of said polysilicon gate structure are exposed;
E. etching away said capping layer on said polysilicon gate structure of said gate such that the top of said polysilicon gate structure is exposed;
F. depositing a silicidation metal to cover the top and said sidewalls of said top portion of said polysilicon gate structure that is exposed;
G. performing a silicidation anneal with said silicidation metal and said top portion of said polysilicon gate structure to form a gate silicide having a second silicide thickness on top of said polysilicon gate structure;
wherein said gate silicide has a width that is larger than a width of said polysilicon gate structure of said gate;
and wherein said MOSFET initially includes dielectric spacers disposed on sidewalls of said polysilicon gate structure; and
H. etching away said dielectric spacers from said sidewalls of said polysilicon gate structure before said step B.
11. The method of claim 10, wherein said drain silicide and said source silicide are comprised of a different material from said gate silicide.
12. The method of claim 11, wherein said drain silicide and said source silicide are comprised of nickel silicide (NiSi2), and wherein said gate silicide is comprised of one of cobalt silicide (CoSi2) or titanium silicide (TiSi2).
13. The method of claim 10, wherein said first suicide thickness of said drain silicide and said source silicide is smaller than said second silicide thickness of said gate silicide.
14. The method of claim 10, wherein said MOSFET initially includes dielectric spacers disposed on sidewalls of said polysilicon gate structure, and wherein said method further includes the step of:
etching away said dielectric spacers from said sidewalls of said polysilicon gate structure before said step B.
15. The method of claim 10, wherein said first silicide thickness of said drain and source silicides is less than about 200 angstroms, and wherein said top portion of said polysilicon gate structure has a height in a range of from about 200 angstroms to about 400 angstroms.
16. The method of claim 10, further including the steps of:
depositing a second dielectric layer over said gate silicide and over said first dielectric layer; and
forming a gate interconnect on said second dielectric layer, wherein said gate interconnect is conductively coupled to said gate silicide with a gate via through said second dielectric layer.
17. The method of claim 16, further including the steps of:
forming a drain interconnect on said second dielectric layer, wherein said drain interconnect is conductively coupled to said drain silicide with a drain via through said second dielectric layer and said first dielectric layer; and
forming a source interconnect on said second dielectric layer, wherein said source interconnect is conductively coupled to said source silicide with a source via through said second dielectric layer and said first dielectric layer.
18. The method of claim 10, wherein a first type of dopant within said drain region and said source region is an N-type dopant, and wherein a second type of dopant within said channel region is a P-type dopant for fabricating an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor).
19. The method of claim 10, wherein a first type of dopant within said drain region and said source region is a P-type dopant, and wherein a second type of dopant within said channel region is an N-type dopant for fabricating a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor).
20. A method for fabricating a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), said MOSFET having a drain region, a source region, and a channel region, and said MOSFET initially having a gate comprised of a capping layer on a polysilicon gate structure disposed on a gate dielectric over said channel region, and said MOSFET initially including dielectric spacers disposed on sidewalls of said polysilicon gate structure, the method including the sequential steps of:
A. forming a drain silicide in said drain region and a source silicide in said source region, said drain silicide and said source silicide having a first silicide thickness;
B. etching away said dielectric spacers from said sidewalls of said polysilicon gate structure;
C. depositing a first dielectric layer over said drain region, said source region, and said gate;
D. polishing down said first dielectric layer until said capping layer of said gate is exposed such that said capping layer and said first dielectric layer are substantially level;
E. etching away a top portion of said first dielectric layer until sidewalls at a top portion of said polysilicon gate structure are exposed;
wherein said first silicide thickness of said drain and source silicides is less than about 200 angstroms, and wherein said top portion of said polysilicon gate structure has a height in a range of from about 200 angstroms to about 400 angstroms;
F. etching away said capping layer on said polysilicon gate structure of said gate such that the top of said polysilicon gate structure is exposed;
G. depositing a silicidation metal to cover said top and said sidewalls of said top portion of said polysilicon gate structure that is exposed;
H. performing a silicidation anneal with said silicidation metal and said top portion of said polysilicon gate structure to form a gate silicide having a second silicide thickness on top of said polysilicon gate structure;
wherein said gate silicide has a width that is larger than a width of said polysilicon gate structure of said gate;
and wherein said drain silicide and said source silicide are comprised of a different material from said gate silicide;
and wherein said drain silicide and said source silicide are comprised of nickel silicide (NiSi2), and wherein said gate silicide is comprised of one of cobalt silicide (CoSi2) or titanium silicide (TiSi2);
and wherein said first silicide thickness of said drain silicide and said source silicide is smaller than said second silicide thickness of said gate silicide;
I. depositing a second dielectric layer over said gate silicide and over said first dielectric layer;
J. forming a gate interconnect on said second dielectric layer, wherein said gate interconnect is conductively coupled to said gate silicide with a gate via through said second dielectric layer;
K. forming a drain interconnect on said second dielectric layer, wherein said drain interconnect is conductively coupled to said drain silicide with a drain via through said second dielectric layer and said first dielectric layer; and
L. forming a source interconnect on said second dielectric layer, wherein said source interconnect is conductively coupled to said source silicide with a source via through said second dielectric layer and said first dielectric layer;
and wherein a first type of dopant within said drain region and said source region is an N-type dopant, and wherein a second type of dopant within said channel region is a P-type dopant for fabricating an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor);
and wherein said first type of dopant within said drain region and said source region is a P-type dopant, and wherein said second type of dopant within said channel region is an N-type dopant for fabricating a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor).