DC offset cancellation apparatus and method for digital demodulatation

[0002] 1. Field of the Invention

[0003] The present invention relates to digital signal processing and, more particularly, to methods and apparatus that utilize noise shaping technology for DC offset cancellation prior to digital demodulation.

[0004] 2. Description of the Related Art

[0005] Referring to FIG. 1, a block diagram of a satellite QPSK (Quadrature Phase Shift Keying) receiver is schematically illustrated. In FIG. 1, an antenna 1 is provided to detect a radio frequency (RF) signal, typically in Ku band, which is then converted by a LNB low-noise block (not shown in the drawing) into an intermediate frequency signal IF_1, generally ranging from about 950 MHz to about 1450 MHz in frequency. A tuner 2 receives the signal IF_1 and transmits another intermediate frequency signal IF_2, typically at about 479.5 MHz, to scalars 3 and 4. A local oscillator 5 transmits a local oscillating signal (LO) to scalars 3 and 4. As shown, the local oscillating signal LO transmitted to scalar 4 is shifted by 90 degrees in phase from the local oscillating signal LO transmitted to scalar 3. The scalars 3 and 4 mix the signal IF_2 with the respective local oscillating signal LO, thus generating analog in-phase signal I_Aand analog quadrature phase signal Q_A, respectively.

[0006] An analog-to-digital converter (ADC) 7 is utilized to digitize the analog in-phase signal I_A, thus providing a digital in-phase signal I_D, while an ADC 8 digitizes the analog quadrature phase signal Q_Ato provide a digital quadrature phase signal Q_D. Both the digital in-phase signal I_Dand the digital quadrature phase signal Q_Dare transmitted to a digital demodulator 10 for further processing. Preferably, ADCs 7 and 8 have 6-bit resolution. Moreover, a clock generator 9 generates a fixed-frequency clock signal CLK, preferably with a frequency greater than 60 MHz, for driving ADCs 7 and 8.

[0007] Since DC offset in a QPSK signal can result in problems during demodulation, it is preferable to eliminate any DC offset prior to the signal entering digital demodulator 10. Circuits for DC offset cancellation can be categorized into three types: analog, semi-analog, and digital.

[0008] The analog type circuit for DC offset cancellation is employed to eliminate DC offset from analog signals. When applied to a satellite QPSK receiver, as shown in FIG. 1, analog type circuits should be arranged between scalars 3 and 4 and the associated ADC 7 or 8, in order to process I_Aand Q_A, respectively. U.S. Pat. No. 5,508,656 discloses an example of an analog type circuit for DC offset cancellation. This patent utilizes a switching-capacitor technique for DC offset cancellation.

[0009] U.S. Pat. Nos. 5,617,060 and 5,699,011 disclose examples of a semi-analog type circuit for DC offset cancellation. When applied to a satellite QPSK receiver, such as depicted in FIG. 1, semi-analog type circuits are used to process both the I and Q channel, and are arranged in feedback loops from I_Dto I_Aand from Q_Dto Q_A, respectively. In these systems, the respective digital signal, I_Dor Q_D, is processed to acquire its digital DC offset, after which a digital-to-analog converter (DAC) converts the digital DC offset to analog, and feeds the analog DC offset back for subtraction from the respective analog signal, I_Aor Q_A.

[0010] A digital type circuit for DC offset cancellation is disclosed in U.S. Pat. No. 5,281,968, and is employed to cancel DC offsets from digital signals. When applied to a satellite QPSK receiver, such as depicted in FIG. 1, a digital type circuit should be arranged between both ADC 7 and digital demodulator 10 and ADC 8 and digital demodulator 10. These circuits are used to process I_Dand Q_D, respectively, to eliminate any DC offset contained therein.

[0011] FIG. 2 provides a block diagram of a conventional digital type circuit for DC offset cancellation. The circuit comprises a subtracter 20, an attenuator 21 and an accumulator 22. As shown in FIG. 2, subtracter 20 receives the respective digital signal, I_Dor Q_D, which is designated by digital signal x, from the associated ADC 7 or ADC 8, and subtracts a signal Vdc, representing the DC offset, from signal x, thus generating output signal y. Signal y is then fed back to accumulator 22 to generate accumulation value z, which is sent to attenuator 21. In FIG. 2, accumulator 22 consists of a delay 23, which is expressed in the form of a Z-transform, and an adder 24. In accumulator 22, the output of adder 24 is registered and delayed for a sampling period by delay 23, after which it is fed back to adder 24, which adds it to current signal y. Attenuator 21 is used to multiply the accumulation value z by a constant k, which is typically a very small negative power of two such as 2⁻¹⁶, to generate DC offset signal Vdc. DC offset signal Vdc is then subtracted from digital signal x in subtracter 20 to generate output signal y. Output signal y is then transmitted to digital demodulator 10 for further processing. Thus, any DC offset is canceled from I_Dor Q_D, respectively, before being sent to digital demodulator 10.

[0012] Disadvantageously, application of the circuit of FIG. 2 to a satellite QPSK receiver gives rise to an enormous increase in the required word length for QPSK signals. For ease and clarity, assume that ADC 7 and ADC 8 are provided with 6-bit resolution and their outputs are in 2's-complement form. This six-bit format can be used to express an integer ranging from −32 to 31 in decimal notation with the least significant bit representing one. To practically cancel DC offset signal Vdc, signal y should be represented by a large number of fraction bits in addition to the integer bits. For example: $\begin{array}{ccc}x& \mathrm{xxxxxx}.& \\ -\mathrm{Vdc}& \mathrm{xx}.& \mathrm{xxxxxxxxx\dots }\\ y& \mathrm{xxxxxx}.& \mathrm{xxxxxxxxx\dots }\end{array}$

[0013] In other words, the conventional circuit of FIG. 2 requires the corrected digital in-phase signal I_Dand the corrected digital quadrature phase signal Q_Dto have a very large word length. In general, the larger the over sampling rate, the ratio of the ADC sample rate to the QPSK symbol rate, the larger the required word length. In the application of single channel per carrier (SCPC), the over sampling rate is quite large and very large word length is needed. Thus, these greater word lengths expand the hardware complexity of the arithmetic circuits of demodulator 10 operating on the QPSK signals. Furthermore, because the frequency of the clock signal CLK is usually greater than 60 MHz, the demodulator may not have sufficient time to process the QPSK signals with greater word length.

[0014] It is therefore an object of the present invention to provide a digital type circuit for DC offset cancellation that uses a reduced word length for corrected QPSK signals.

[0015] It is another object of the present invention to provide a circuit and method for DC offset cancellation to reduce the operational burden on the digital demodulator, and thus decrease hardware complexity. A DC offset cancellation circuit consistent with this invention comprises a subtracter for subtracting a quantized DC offset from a digital signal, a noise shaper for converting an unquantized DC offset into the quantized DC offset, the quantized DC offset having fewer bits than the unquantized DC offset and an average value in the time domain approximates the unquantized DC offset, an accumulator for outputting an accumulation value of the outputs of the subtracter, and an attenuator for multiplying the accumulation value by a constant to generate the unquantized DC offset and transmitting the unquantized DC offset to the noise shaper, wherein the constant is less than one.

[0016] A method of DC offset cancellation consistent with this invention comprises subtracting a quantized DC offset from a digital signal by using a subtracter, accumulating an output of the subtracter to form an accumulation value, multiplying the accumulation value by a constant to generate an unquantized DC offset, converting the unquantized DC offset to said quantized DC offset whose average value in the time domain approximates said unquantized DC offset and has fewer bits than said unquantized DC offset.

[0017] The following detailed description, given by way of example, is not intended to limit the invention to the embodiments described herein, and will best be understood in conjunction with the accompanying drawings, in which:

[0018] FIG. 1 schematically illustrates a block diagram of a conventional QPSK receiver;

[0019] FIG. 2 schematically illustrates a block diagram of a conventional digital type circuit for DC offset cancellation;

[0020] FIG. 3 schematically illustrates a block diagram of a DC offset cancellation circuit in accordance with one preferred embodiment of the present invention;

[0021] FIG. 4 schematically illustrates a block diagram of one example of a noise shaper shown in FIG. 3; and

[0022] FIG. 5 schematically illustrates a block diagram of a DC offset cancellation circuit in accordance with another preferred embodiment of the present invention

[0023] Referring to FIG. 3, a circuit diagram of a DC offset cancellation circuit in accordance with a preferred embodiment of the present invention is schematically illustrated. In FIG. 3, the DC offset cancellation circuit comprises a subtracter 30, an attenuator 31, an accumulator 32, and a noise shaper 33. Noise shaper 33 is also termed a delta-sigma modulator in literature.

[0024] As shown in FIG. 3, subtracter 30 receives the digital in-phase signal I_Dor the digital quadrature phase signal Q_D, which is designated as a digital signal x, from the associated ADC 7 or ADC 8, and subtracts a quantized DC offset v_dc from signal x so as to generate output signal y. Signal y is then fed back to accumulator 32 to generate accumulation value z, which is transmitted to attenuator 31. In FIG. 3, accumulator 32 consists of a delay 34, which is expressed in the form of a Z-transform, and an adder 35. The output of adder 35 is registered and delayed for a sampling period by delay 34, after which it is fed back to adder 35 for addition with current signal y. Attenuator 31 is used to multiply accumulation value z by constant k to generate an unquantized DC offset u_dc. Typically, the value of k is a very small negative power of 2, such as 2⁻¹⁶. The unquantized DC offset u_dc is then converted by noise-shaper 33 into the quantized DC offset v_dc.

[0025] To avoid increasing the required word lengths of the corrected digital in-phase signal I_Dand the corrected digital quadrature signal Q_D, the number of bits required for expressing the DC offset is reduced. Thus, according to the present invention, noise shaper 33 is utilized to convert the unquantized DC offset u_dc into the quantized DC offset v_dc. As a result of this conversion, the number of bits required for the quantized DC offset v_dc is less than that of the unquantized DC offset u_dc.

[0026] Assume that the least significant bit of ADC 7 or 8 is one. If the unquantized DC offset u_dc is ⅓ in decimal notation, that is one-third of the least significant bit of ADC 7 or 8, two integer bits and sixteen fraction bits are required to represent the unquantized DC offset u_dc as 00. 01010101 01010101 in order to effectively express the DC offset.

[0027] In the time domain, the quantized DC offset v_dc, if exemplified to possess two integer bits, is sequentially 00, 00, 01, 00, 00, 01, 00, 00, 01, . . ., etc., wherein the logic pattern of “01” represents one least significant bit of ADC 7 or 8, and the logic pattern of “00” represents zero. Therefore, the average value of the quantized DC offset v_dc approaches and is equal to the unquantized DC offset u_dc over a long time period, and thus approximates it.

[0028] Moreover, if exemplified to possess two integer bits and one fraction bit, the quantized DC offset v_dc is sequentially 00.0, 00.1, 00.1, 00.0, 00.1, 00.1, 00.0, 00,1, 00.1, . . ., etc., wherein the logic pattern of “00.1” represents half of the least significant bit of ADC 7 or 8, and the logic pattern of “00.0” represents zero. Again, the average value of the quantized DC offset v_dc is equal to the unquantized DC offset u_dc over a long time period.

[0029] Consequently, although the unquantized DC offset u_dc possesses a large number of fraction bits, the quantized DC offset v_dc can be simplified so it possesses one or zero fraction bits. For example: $\begin{array}{ccc}x& \mathrm{xxxxxx}.& \\ -\mathrm{v\_dc}& \mathrm{xx}.& x\\ y& \mathrm{xxxxxx}.& x\end{array}$

[0030] Referring to FIG. 4, a block diagram of one example of noise shaper 33, as shown in FIG. 3, is schematically illustrated. In FIG. 4, a first-order noise shaping circuit is illustrated, comprising an adder 40, a delay 41, a subtracter 42, and a multi-bit quantizer 43.

[0031] In FIG. 4, adder 40 receives the unquantized DC offset u_dc and adds it to the output of delay 41, after which the sum is transmitted to multi-bit quantizer 43 and subtracter 42. Subtracter 42 subtracts the output of multi-bit quantizer 43 from the output of adder 40 and then transmits the result to delay 41. Multi-bit quantizer 43 is employed to process the output of adder 40 to determine the quantized DC offset v_dc.

[0032] Referring to FIG. 5, a circuit diagram of a DC offset cancellation circuit in accordance with another preferred embodiment of the present invention is schematically illustrated, wherein the different parts with those of the embodiment in FIG. 3 are indicated with a different numeral. In the drawing, a signal processing circuit 50 is provided to process the signal y, then transmitted to the accumulator 32. For example, the signal processing circuit 50 can be a low pass filter, a decimation filter, or a multiplier which multiplies the signal y by a gain control value.

[0033] Thus, the cancellation circuit of the preferred embodiments includes a noise shaper to convert the unquantized DC offset into a quantized DC offset having fewer bits than that of the unquantized DC offset. The use of the noise shaper reduces the required word length for QPSK signals and lessens the operational burden on the digital demodulator, thus decreasing its hardware complexity.

[0034] While the invention has been described with reference to various illustrative embodiments, the description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those person skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as may fall within the scope of the invention defined by the following claims and their equivalents.