Digital disk recording and reproduction apparatus

[0002] This application is a divisional of prior application Ser. No. 09/091,163 filed Jun. 9, 1998, now U.S. Pat. No. 6,198,710.

[0003] The present invention relates to a digital recording method, a digital disk, a digital disk recording apparatus, and a digital disk reproduction apparatus, and more particularly, to a digital recording method for recording digital data efficiently onto a medium, a digital disk, a digital disk recording apparatus, and a digital disk reproduction apparatus.

[0004] The media of magneto-optical disks, optical disks, phase change disks, and the like are known as digital disks. The recording and reproduction of the disk are all carried out by data transfer in AC coupling. This means that it is difficult to record/reproduce signal components of the low frequency region at high efficiency with respect to data recorded at high density on a digital disk.

[0005] It is therefore necessary to carry out modulation that suppresses the direct current and low frequency components for recording data. The recorded data stream includes the clock frequency components of recording. At the time of reproduction, the clock frequency components are extracted from the signal of the reproduced data stream. Self clock control is provided that reproduces the reference clock of the reproduction apparatus by the extracted clock frequency component. In modulating digital data, self clock control must be feasible and with few direct current and low frequency components. EFM, 1-7 RLL modulation, 2-7 RLL modulation and the like are known as such modulation systems. RLL-modulated data is NRZI-modulated or NRZ-modulated and recorded on a medium.

[0006] Japanese Patent Laying-Open No. 2-96982 proposes a method of preparing a plurality of pseudo random data streams and scrambling the data stream with the pseudo random data that has the smallest DSV (Digital Sum Variation) at the time of recording. Such an adaptive type modulation method that reduces the value of DSV is proposed.

[0007] It is known to form a sine wave shape (wobble shape) having a predetermined cycle and amplitude at the wall of a groove in a disk medium. This wobble is well known by those skilled in the art as disclosed in, for example, Japanese Patent Laying-Open No. 7-311962. Address information and the like are recorded in a multiplexed manner by this wobble.

[0008] A main object of the present invention is to provide a digital recording method of favorable digital recording efficiency, a digital disk, a digital disk recording apparatus and a digital disk reproduction apparatus.

[0009] Another object of the present invention is to propose an example of an adaptive type modulation method that suppresses direct current and low frequency components.

[0010] The present invention is directed to a digital recording method of selecting and recording modulation record data that has the direct current component at the time of recording suppressed, out from a group of modulation record data candidates. A plurality of types of data of a predetermined number of bits are added to input data as initial data. In a predetermined sequence for every predetermined number of bits, exclusive-OR is taken between the current code modulation unit to be transformed and the code modulation unit immediately preceding that current code modulation unit. By applying a convolution process substituting for that current code modulation unit, a group of candidates of a plurality of types of modulation record data are generated from the input data. The direct current component in the recording operation of each of the plurality of modulation record data are compared with each other. Modulation record data is selected and recorded according to the comparison result. By the invention of the present application, the direct current component at the recording/reproduction system can be suppressed with only a slight increase in data length.

[0011] According to a preferable embodiment of the present invention, the data length n of the initial data added to the input data is 2≦n≦32. More preferably, the data length n of the initial data is 4≦n≦8.

[0012] Further preferably, the data length m of the input data is L times (L is an integer of at least 2) the initial data.

[0013] According to another aspect of the present invention, a digital disk has a wobble formed. A data stream is formed in phase synchronization with the wobble configuration.

[0014] According to another aspect of the present invention, a digital disk recording apparatus writes data in synchronization with the wobble formed in a digital disk. A wobble signal is extracted from the digital disk. A reference clock signal is generated in synchronization with the wobble signal. Data is written according to the reference clock signal.

[0015] According to yet another aspect of the present invention, a digital disk reproduction apparatus reads out written data in synchronization with the wobble formed in a digital disk. A wobble signal is extracted from the digital disk. A reference clock signal is generated in synchronization with this wobble signal. A reproduced signal is digitized by the reference clock signal.

[0016] FIG. 1 shows a magneto-optical disk according to a first embodiment of the present invention.

[0017] FIG. 2 shows a portion of the magneto-optical disk of FIG. 1.

[0018] FIG. 3 shows a reproduction waveform of a wobble signal.

[0019] FIG. 4 is a block diagram showing an example of a recording apparatus.

[0020] FIG. 5 is a block diagram showing an example of a reproduction apparatus.

[0021] FIG. 6 is a block diagram showing an example of the modulation circuit shown in FIG. 4.

[0022] FIG. 7 is a diagram for describing an operation of the modulation circuit of FIG. 6.

[0023] FIGS. 8A and 8B are diagrams for describing an optimum adaptive type modulation method.

[0024] FIG. 9 is a block diagram of an adaptive type modulation circuit.

[0025] FIG. 10 is a block diagram specifically showing an adaptive type modulation circuit.

[0026] FIGS. 11A and 11B are diagrams for describing an operation of the adaptive type modulation circuit shown in FIG. 10.

[0027] FIGS. 12A and 12B are diagrams for describing a demodulation operation.

[0028] FIG. 13 is a diagram showing the data length relationship between initial data (Tj) and primitive data (input data).

[0029] FIG. 14 is a waveform diagram showing a frequency spectrum.

[0030] FIG. 15 is a diagram showing the data length relationship between initial data (Tj) and primitive data (input data).

[0031] FIG. 16 shows the frequency spectrum of FIG. 15.

[0032] FIGS. 17A-17E are block diagrams showing combination examples of modulation circuits.

[0033] FIGS. 18A and 18B show examples of Tj arranged together.

[0034] FIG. 19 shows an example of a clock mark provided in a linear track.

[0035] FIG. 20 shows an example of a clock mark provided in a meandering track.

[0036] FIG. 21 shows an example of a track having one side linear and the other side wobbled.

[0037] FIG. 22 shows an example where the meander configuration of a track is in phase at both walls of the groove and land.

[0038] FIG. 23 shows an example in which the meander configuration of a track is in opposite phase at both walls of the groove and land.

[0039] FIG. 24 shows an example in which only one of the walls of the groove and land meanders in a track.

[0040] Embodiments of the present invention will be described in detail hereinafter with reference to the drawings.

[0041] FIG. 1 shows a magneto-optical disk according to a first embodiment of the present invention; FIG. 2 shows a portion of this magneto-optical disk; and FIG. 3 shows a reproduction waveform of a wobble signal.

[0042] Referring to FIG. 1, a digital disk 10 is a magneto-optical disk, employing the zone CLV system (ZCLV system). This ZCLV system is well known, so that detailed description thereof will not be repeated. Magneto-optical disk 10 has a groove formed at the surface of the disk. The groove is provided in a spiral manner from the inner circumference towards the outer circumference of the disk. The wall at both sides of this groove meanders as shown in FIG. 2. In the mastering process of the glass plate to form this disk, a meander groove is formed with a wobble signal that is wobbled by a unitary frequency clock that becomes the reference in disk rotary control and in generating a bit clock in recording/reproducing data. This is called “clocking wobble”. In this case, the frequency of clocking wobble is recorded so as to be in synchronism with the data to be recorded. In the first embodiment, the frequency of the clock wobble is set to 1.1 MHz, which is ⅛ the clock frequency 8.8 MHz (constant rotary control) in data recording.

[0043] The groove has an amplitude of approximately 10 nm to 50 nm in the radius direction of the disk. Each track of the groove on the disk is formed of 60 zones radially for ZCLV control. CVL control is provided for each zone. In this ZCVL, control is provided so that the revolution is greater at the inner circumferential zone and smaller at the outer circumferential zone to reduce difference in the linear velocity between different zones. As shown in FIG. 1, the groove has a data region in which data is written and an address region multiplexed with the absolute address information formed on the disk. At the wobble of the address region, address information is modulated beforehand using a bi-phase coding method and the like with respect to the wobble signal to be incorporated as a wobble of the groove.

[0044] FIG. 3 shows a wobble signal in the proximity of the boundary of the address region. When the information serving as an address mark is recorded by wobble as address information at the address segment area, it is apparent from FIG. 3 that 0 is recorded as a value of bi-phase data for the clocking wobble portion. Therefore, a signal which is a bi-phase-modulated version of the address information data is formed in wobble at the address region area of FIG. 1. In the data region area, a signal which is a bi-phase-modulated version of the data that takes the value of 0 is formed at the wobble. A reproduced signal from this wobble can be used for controlling the disk rotation.

[0045] One feature of the present invention lies in that this wobble is used as a reference for generating a clock oriented to writing with respect to data that is to be recorded/reproduced. Another feature of the present invention lies in that this wobble is used as a reference for generating a clock for reading with respect to data that is to be recorded/reproduced. In other words, data is recorded/reproduced in synchronization with this wobble.

[0046] FIG. 4 is a schematic block diagram of a recording apparatus. The magneto-optical disk recording/reproduction apparatus of FIG. 4 does not have the circuitry of the reproduction system depicted since only recording operation is described here.

[0047] Data to be recorded (referred to as primitive data hereinafter) is input through an input terminal 14. This primitive data is modulated by a modulation circuit 16 and provided to a magnetic head 20 via an amplifier 18 to be recorded on magneto-optical disk 10. The process carried out by modulation circuit 16 includes an error correction coding method for error correction in reproduction, an adaptive type modulation to reduce the DSV value, NRZ modulation (or NRZI modulation) and the like.

[0048] The data recorded on magneto-optical disk 10 is recorded into the data region in synchronization with the wobble. A write timing signal therefor is applied from a timing controller 22 to modulation circuit 16. A write clock signal is supplied from a PLL oscillation circuit 24 to modulation circuit 16. A wobble signal from the wobble formed in magneto-optical disk 10 is read out by optical head 26. The read output is provided to a matrix circuit 28.

[0049] Matrix circuit 28 outputs a tracking error signal, a focus error signal, a RF signal, and a wobble signal according to the output of optical head 26. The tracking error signal is applied to a tracking control circuit 30. The focus error signal is applied to a focus control circuit 32. The tracking control signal and the focus control signal are returned to optical head 26. The RF signal output from matrix circuit 28 is applied to the reproduction system to be demodulated. The wobble signal output from matrix circuit 28 is applied to PLL circuit 24, an address detection circuit 40, and a spindle servo circuit 34. Spindle servo circuit 34 compares the wobble signal with a signal from a 1.1 MHz reference oscillator 36 to provide control of the rotation of a motor 38, whereby the wobble signal and the 1.1 MHz reference signal synchronize with each other. Address detection circuit 40 detects an address signal that is multiplexed in bi-phase with the wobble signal. The value of the detected address signal and a detection timing signal are applied to timing controller 22. PLL oscillation circuit 24 provides a 8.8 MHz clock signal in phase synchronization with the 1.1 MHz wobble signal.

[0050] In the example shown in FIG. 4, data is recorded on magneto-optical disk 10 by the clock signal in synchronization with the reproduced wobble signal. More specifically, the data recorded on magneto-optical disk 10 is written in synchronization with the wobble configuration.

[0051] FIG. 5 is a block diagram showing a reproduction apparatus according to an embodiment of the present invention. FIG. 5 has only the reproduction system depicted. Only elements differing from those of FIG. 4 will be described here. The RF signal output from matrix signal 28 is applied to an A/D conversion circuit 42. A/D conversion circuit 42 receives a clock signal for reproduction from PLL circuit 24. The RF signal is binarized according to this clock signal for reproduction. The digital data from A/D conversion circuit 42 is applied to a demodulation circuit 44. The clock signal for reproduction from PLL circuit 24 is also applied to demodulation circuit 44. The digital data is demodulated according to this clock signal for reproduction to be restored to primitive data. This process of demodulation circuit 44 is opposite to that of modulation circuit 16 of FIG. 4.

[0052] In the embodiment shown in FIG. 5, a clock signal in synchronization with a reproduced wobble signal is generated, and a data reproduction process is carried out by this clock signal. According to the present embodiment, a clock signal in synchronization with reproduction data can be obtained without generating a clock signal from the clock component of a RF signal. In other words, recording and reproduction of a sufficient level can be effected without taking account of a self clock signal that was considered to be mandatory for conventional digital recording/reproduction. The modulation system of the present embodiment takes into consideration both the issues of “self clock” and “DSV value suppression”. It can be said that the conventional RLL modulation is no longer mandatory for digital disk recording/reproduction. The conventional RLL modulation has the disadvantage that the amount of data is great. For example, in 1-7 modulation [(1, 7, 2, 3) modulation], the DSV value can be suppressed. However, the primitive data of 2 bits is increased to 3 bits. In other words, the amount of data is increased 50% by this modulation.

[0053] As an adaptive type modulation method of the apparatus of the present embodiment, the data recording efficiency can be improved by employing only the adaptive type modulation introduced in the aforementioned Japanese Patent Laying-Open No. 2-96982, not the typical RLL modulation.

[0054] In the adaptive type modulation of Japanese Patent Laying-Open No. 2-96982, the information indicating the pseudo random series for demodulation is also recorded to send this information (information code) to the reproduction side. However, when an error is generated in data reproduction to result in an erroneous information code, there is a possibility that erroneous propagation is generated in the entire scrambled data block.

[0055] Since suppression of the DSV value is insufficient in the conventional 1-7 RLL modulation, a further modulation method that can suppress the DSV value is required. However, the amount of data will be further increased for this purpose. In the following second embodiment, adaptive modulation according to the DSV value can be effected with little increase in the amount of data. Also, modulation with lower error propagation is carried out.

[0056] FIG. 6 is a block diagram of the modulation circuit of FIG. 4; FIG. 7 is a diagram for describing an operation of the modulation circuit of FIG. 6; and FIGS. 8A and 8B are diagrams for describing adaptive type modulation.

[0057] Since the demodulation circuit carries out a process opposite to that of modulation circuit 16, a block diagram thereof is not particularly depicted. In the present embodiment, primitive data of approximately 2-K bytes (2048 bytes) is recorded into one data region of magneto-optical disk 10. The input primitive data is applied to an error correction coding circuit 46. Error correction coding circuit 46 divides the primitive data of FIG. 7(a) into units of 2048 bytes to apply an error correction coding process on the 2048-byte data of FIG. 7(b). As shown in FIG. 7(c), an error correction code is added to be converted into data of 2400 bytes.

[0058] This data is applied to an adaptive type modulation circuit 48. Adaptive type modulation circuit 48 divides the data of FIG. 7(c) into units of 40 bits. Initial data of 4 bits is added to each 40-bit data of FIG. 7(d). Then, the data is divided for every 4 bits. The convolution process of exclusive-OR is applied between the 4-bit data and the initial data for modulation. By selecting the value of the 4-bit data to be added, the DSV value can be suppressed. This will be described afterwards. As shown in FIG. 7(f), the data of 2640 bytes is applied to a Sync·Resync addition circuit 50. A Sync·Resync signal is added by this Sync·Resync addition circuit 50 as shown in FIG. 7(g). This data is recorded on magneto-optical disk 10 via an NRZ modulation circuit 52 and amplifier 18.

[0059] The adaptive type modulation of the present embodiment will be described in detail hereinafter. In data conversion, initial data of a plurality of bits is added to the head of each one block data. If this initial data is 2 bits, there are four possible types of values [00] [01] [10] [11]. If this initial data is 4 bits, the sixteen values of [0000] [0001] [0010] [0011] [0100] [0101] [0110] [0111] [1000] [1001] [1010] [1011] [1100] [1101] [1110] [1111] are possible.

[0060] Thus, initial data (transform number j) of j types (j is a power of 2) is added to generate j pre-transform block data.

[0061] The principle of conversion will be described with reference to FIGS. 8A and 8B. For each of the j pre-transform data starting from the head transform unit excluding the initial data, an exclusive-OR (modulo2) operation is performed between the current code transform unit to be transformed and the transform unit (initial data or transformed code modulation unit) right before the current code transform unit. The result is substituted for the current code modulation unit (convolution process). As a result, j post-transform data are generated. More specifically, for each of the j pre-transform data, modulo2 operation of the first code transform unit D0 and initial data Tj is carried out to produce post-transform data D′0 of the first code transform unit excluding the initial data. This data D′0 is substituted for D0.

[0062] Then, modulo2 operation is carried out of data D′0 of the transformed code transform unit and the next code transform unit D1 to produce the next post-transform data D′1. This value is substituted for D1. A similar process is repeated up to the last code transform unit of that block. In data demodulation, in the order of the transform unit excluding the first demodulation code unit (initial data Tj) of the pre-inverse transform data, exclusive-OR operation is carried out between the current transform unit to be inverse-transformed and the transform unit (initial data or demodulation code unit before inversion) right before the current transform unit. The obtained value is substituted for the relevant current demodulation code unit. As a result, post-inverse transform data is generated. More specifically, by the modulo2 operation of the first demodulation code unit D′0 and initial data Tj, post-inverse transform data DO is generated, which is substituted for D′0. Then, modulo2 operation is carried out between D′0 (demodulation code unit before inverse transform) and the next demodulation code unit D′1, whereby the next post-inverse transform data D1 is generated. This value is substituted for D′1.

[0063] A similar process is repeated up to the last demodulation code unit of the relevant data. In data inversion, one immediately preceding demodulation code unit that is not yet inverted is used in the inverse transform of the current demodulation code unit. Therefore, the effect of an error, if any, is limited to the current modulation code unit, and will not be propagated to the subsequent modulation code unit. For example, when there is an error in modulation code unit D′i that is not yet inverse-transformed, only the post-inverse transform demodulation code unit Di and Di+1 are affected by this error.

[0064] A specific manner of data transform will be described to provide the principle of the above process.

[0065] FIG. 9 is a schematic block diagram of an adaptive type modulation circuit; FIG. 10 is a more specific block diagram thereof; and FIGS. 11A and 11B show the processing procedure of an adaptive type modulation circuit.

[0066] It is assumed that the initial data has a data length of 2 bits, and the primitive data has a data length of 8 bits. The input 8-bit primitive data is [10001101]. The added 2-bit initial data includes the four types of T1: [00], T2: [01], T3: [10], T4: [11]. Primitive data [1001101] is applied to input terminal 14 of FIG. 10 to be provided to adaptive type modulation circuit 48. The primitive data is applied to Tj addition conversion circuits 54a-54dto be converted. In Tj addition conversion circuit 54acorresponding to T1, the conversion shown in FIG. 11A is carried out. In Tj addition conversion circuit 54bcorresponding to T2, the conversion shown in FIG. 11B is carried out.

[0067] The outputs of Tj addition conversion circuits 54a-54dare applied to recording time data series conversion circuits 56a-56d. Recording time data series conversion circuits 56a-56dconvert the outputs of Tj addition conversion circuits 54a-54dinto data series output to the recording/reproduction system. In the present embodiment, the output of Tj addition conversion circuit 54 is applied to NRZ modulation circuit 52 to be modulated and provided to the recording/reproduction system. It can be considered that the output of Tj addition conversion circuit 54 is provided directly to the recording/reproduction system in the present embodiment. The conversion process is ceased at recording time data series conversion circuits 56a-56d, so that the input is output intact.

[0068] The outputs of recording time data series conversion circuits 56a-56dare applied to DSV value measurement circuits 58a-58dand to peak value measurement circuits 60a-60d. DST value measurement circuits 58a-58dobtain the DST value of the 10-bit data (primitive data 8 bits+initial data 2 bits) actually output to the recording/reproduction system. Peak value measurement circuits 60a-60ddetect and hold the peak value of the direct current variation of the 10 bits (primitive data 8 bits+initial data 2 bits) actually output to the recording/reproduction system. More specifically, in the example shown in FIG. 11A, DSV value measurement circuit 58aoutputs “−4”, and peak value measurement circuit 60aoutputs “−4”. In the example shown in FIG. 11B, DSV value measurement circuit 58boutputs “2”, and peak value. measurement circuit 60boutputs “4”. Respective outputs of DSV value measurement circuits 58a-58dand peak value measurement circuits 60a-60dare applied to a select circuit 62.

[0069] Select circuit 62 selects the Tj having a small absolute value of this peak value from the outputs of peak value measurement circuits 60a-60d. When the absolute value of the peak value is identical, the Tj having a smaller absolute value of DSV is selected. When the absolute value of this DSV is also identical, either thereof is selected. Select circuit 62 provides this value of j to Tj addition conversion circuit 54. Tj addition conversion circuit 54 carries out the Tj addition conversion according to this j value. Accordingly, adaptive type modulation is carried out to suppress the direct current component at the recording/reproduction system. A Tj having a DSV value of “0” may be selected by select circuit 62. In this case, the DSV value is set as the initial set values of the peak hold of the direct current variation and DSV measurement of the next ten bits (primary data 8 bits+initial data 2 bits).

[0070] In determining and providing the Tj by select circuit 62, the outputs of DSV value measurement circuits 58a-58dcorresponding to this Tj are provided to peak hold circuits 60a-60dand DSV value measurement circuits 58a-68dto be set as the initial set values of the peak hold of the direct current variation and DSV measurement of the next 10 bits (primitive data 8 bits+initial data 2 bits).

[0071] Preventing error propagation in the recording/reproduction system will be described briefly hereinafter. FIGS. 12A and 12B show the procedure in demodulating data that has been modulated by an adaptive type modulation circuit. When the signal shown in FIG. 11A is to be recovered to former data via the recording/reproduction system, the process shown in FIG. 12A is carried out. Even when error occurs in the recording/reproduction system, the error will not be propagated to the entire block as shown in FIG. 12B. The relationship between the data length of primitive data and the data length of the initial data added thereto will be considered hereinafter.

[0072] FIG. 13 shows the data length relationship between initial data Tj and primitive data (input data); and FIG. 14 shows a frequency spectrum.

[0073] The frequency spectrum as a result of simulation of adaptive type modulation by adding initial data of various data length with a constant data length ratio of the primitive data to initial data of FIG. 13 is shown by the frequency spectrum of FIG. 14. In FIG. 14, the standardized frequency is plotted along the horizontal axis, where f is the frequency component when the data series is frequency-analyzed by Fourier conversion, and fc is the frequency component with the highest frequency. More specifically, fc corresponds to the data series of (101010. . . ), and the gain is plotted along the vertical axis.

[0074] In FIG. 14, the signal component of the low frequency region is suppressed in the data series after the abovedescribed adaptive type modulation as the gain in the region of low standardized frequency becomes smaller. More specifically, the suppression effect of the direct current component which is an object of the present invention is increased. Data of at least 2 bits is preferable as the initial data for observation in FIG. 14. This is because DSV control is not carried out in one block by one bit. In other words, although selection is made from two types in the case of one bit, the two data only differ in opposite polarity. Therefore, adaptive control is not substantially carried out by a DSV value by just one block. In the case of one bit, the initial data of the current block is just set so that the DSV repeated from the prior block is canceled. DSV value control can be carried out only from a plurality of bits. In the case of 2 bits, selection is made from 4 types of data. However, considering the data with only the polarity inverted as one type, there are two types of data. Therefore, adaptive control by a DSV value can be carried out by just one block. In the case of four bits, selection is made from 16 data. Considering data of just opposite polarity as one, there is a total of 8 types. Therefore, adaptive control can be carried out sufficiently by a DSV value for only one block.

[0075] Although at least 2 bits is required as the data length n of the initial data, the suppression effect of direct current component is significant when the data length is 4 bits or more, as appreciated from FIG. 14. However, there is no great difference in the suppression effect of the direct current component between the data length of 4 bits and 8 bits for the initial data. It is appreciated from the tendency of the simulation result that improvement in the direct current suppression effect is exhibited up to 32 bits of the data length n of the initial data. A data length greater than 32 bits for initial data will not provide any improvement in the direct current components suppression. Only the block data length will be increased. Therefore, the data length n of the initial data is desirably 8 bits or below taking into consideration the circuit complexity for the abovedescribed adaptive type modulation.

[0076] Simulation was carried out for adaptive type demodulation with initial data having a data length of 4 bits added to primitive data having various data length m. A frequency spectrum of the result thereof is shown in FIG. 16.

[0077] It is appreciated from FIG. 16 that the data length of primitive data is desirably 100 bytes (800 bits) or below when the length of the initial data is 4 bits. Referring to FIG. 16, an excessive short data length of primitive data results in increase in the ratio of the data length of initial data to primitive data. The entire data amount will be increased. Therefore, the data length of primitive data is preferably not more than approximately 10 bytes when the data length of initial data is 4 bits taking into consideration redundancy of the initial data.

[0078] In view of the foregoing, the data length n of initial data and the data length m of primitive data are preferably set so as to satisfy the following equation.

[0079] (4 bits/800 bits)≦(n/m)≦(4 bits/80 bits)

[0080] More specifically,

[0081] 0.005≦(n/m)≦0.05

[0082] Considering that the data length n of the initial data is preferably 4≦n≦8 (bits) from the result of the simulation of FIG. 14, the data length m of primitive data should preferably satisfy the following equation.

[0083] 80≦m≦1600 (bits)

[0084] Also, data length m of primitive data set to an integer multiple of the data length n of initial data is preferable from the standpoint of efficiency-since the operation of modulo2 can be completed. This adaptive type modulation may be employed together with another RLL modulation as mentioned before.

[0085] FIGS. 17A-17E show combinations of the modulation circuits. FIG. 17A corresponds to the example shown in FIG. 9; FIG. 17B corresponds to an arrangement of a RLL modulation circuit 60 provided as a proceeding stage of adaptive type modulation circuit 48 of FIG. 17; and FIG. 17C corresponds to an arrangement of an NRZI modulation circuit 70 instead of NRZ modulation circuit 52 of FIG. 17A. FIG. 17D corresponds to an arrangement of RLL modulation circuit 60 as a preceding stage of adaptive type modulation circuit 48 of FIG. 17C; and FIG. 17E corresponds to an arrangement of exchange of adaptive type modulation circuit 48 and RLL modulation circuit 60 of FIG. 17D.

[0086] When the present invention is applied to a conventional disk, the arrangement shown in FIG. 17E is preferable. According to the arrangement of FIG. 17E, the DSV value must be measured taking into consideration RLL modulation circuit 60 and NRZI modulation circuit 70 in selecting Tj by adaptive type modulation circuit 48. However, since the self clock component generated at RLL modulation circuit 60 is provided to the recording/reproduction system without being destroyed, both self clock recording and current component suppression can be achieved reliably.

[0087] In the previous embodiment, the convolution process is carried out from the beginning in the units of the data length n of the initial data. However, an arbitrary order may be taken.

[0088] FIGS. 18A and 18B show an arrangement of Tj together.

[0089] FIGS. 19-21 show examples having a clock mark of low frequency provided instead of the continuous wobble shown in FIGS. 1-3. Particularly, FIG. 19 shows an example of a linear track, wherein a clock mark of a cycle of w1 and a width of w2 is inserted. FIG. 20 corresponds to a meandering track; and FIG. 21 corresponds to a track having one linear side and another meandering side.

[0090] FIG. 22 corresponds to a track having a meander configuration of the same phase at both walls of the groove and land; FIG. 23 corresponds to a meandering track of opposite phase at both walls of the groove and land; and FIG. 24 corresponds to a track of a configuration where only one wall of the groove and land meanders. Each embodiment of the present invention can be applied in any of such cases.

[0091] According to the present invention, the direct current component at the recording/reproduction system can be suppressed with only a small increase in the data length. Since the reference clock signal is obtained from a wobble signal, data modulation for self clocking does not have to be considered. Furthermore, data can be recorded /reproduced to or from a digital disk at high efficiency. A digital recording apparatus with little error propagation and fine suppression of direct current components can be provided.