Differential amplifiers having β compensation biasing circuits therein

[0002] The present invention relates to integrated circuit devices, and more particularly to integrated amplifier circuits.

[0003] The gain of conventional integrated amplifier circuits is typically influenced by changes in temperature and process variations that may occur during fabrication. For example, the gain of the bipolar emitter coupled pair (ECP) differential amplifier illustrated by FIG. 1 is typically a function of the beta (β) of the bipolar transistors therein. As understood by those skilled in the art, β may be influenced significantly by changes in temperature and by variations in bipolar fabrication processes. The voltage gain (A_v) of the ECP differential amplifier of FIG. 1 is frequently expressed as:

[0004] A_v=βR_cI_e/(β+1)V_t  (1)

[0005] where V_tis the thermal voltage (V_t=KT/q). Equation (1) illustrates that the voltage gain is strongly dependent on the value of β for relatively small β.

[0006] As illustrated by FIG. 2, a common technique for limiting fluctuations in the voltage gain of an ECP differential amplifier includes the use of a compensation resistor, R_comp, in a bipolar current mirror which generates the bias current I_bias. The inclusion of the compensation resistor provides some degree of beta compensation by increasing the voltage on the base of Q4 and thereby increasing the collector current in Q4. However, to provide adequate compensation, the size of R_compfrequently has to be relatively large, which may increase the chip area required by the differential amplifier. Compensation resistors also typically have parameters that vary with temperature and such variations can also contribute to gain error. In addition, the bipolar transistors within the current mirror of FIG. 2 can consume relatively large amounts of power.

[0007] Attempts have also been made to substitute MOS devices for the bipolar devices of FIG. 2 in order to reduce power consumption requirements in current mirrors. For example, FIG. 3 illustrates a conventional ECP differential amplifier having a MOS-based current mirror therein that generates a bias current (l_bias) at a level equal to (N)(IREF), where IREF denotes a magnitude of a reference current provided by a fixed current source of conventional design and N designates the mirror gain (e.g., width of NMOS transistor M6 relative to the width of NMOS transistor M5). MOS-based current mirrors can provide additional benefits over bipolar-based current mirrors, including higher output impedance, lower compliance voltage and lower noise. MOS-based current mirrors may also require less decoupling capacitance and typically have improved scaling capability relative to bipolar-based current mirrors. Nonetheless, MOS-based current mirrors typically do not provide significant built-in compensation for β variations and because of the high gate impedance of MOS transistors compensation resistors typically may not be used successfully.

[0008] Thus, notwithstanding the above-described circuits for biasing and compensating differential amplifiers, there continues to be a need for improved biasing circuits that can have low power consumption requirements and can provide excellent compensation for β variations.

[0009] Preferred differential amplifier embodiments include biasing circuits therein that can automatically account for process and/or temperature induced variations in β and thereby more uniformly maintain the voltage gain of the differential amplifier at a desired level. According to one preferred embodiment, a differential amplifier is provided that comprises first and second bipolar transistors electrically coupled together as an emitter-coupled pair (ECP) and a biasing circuit that is electrically connected to first and second emitters of the first and second bipolar transistors, respectively. This biasing circuit includes a current mirror that sets a magnitude of an emitter bias current in the first emitter at a value proportional to (β+1+Z)/(β+1), where β is the gain of the first bipolar transistor and 1≦Z≦2. In this manner, the gain of the differential amplifier can be set at a level proportional to (β²+β(Z+1))/(β²+2β+1) which is a relatively weak function of β, even for small β.

[0010] According to another preferred embodiment, a differential amplifier is provided that includes first and second bipolar transistors electrically coupled together as an emitter-coupled pair and first and second current sources that generate a first reference current (IREF₁) and a second reference current (IREF₂), respectively. First and second current mirrors are also provided. The first current mirror generates a compensation current having a magnitude proportional to IREF₁/(β+1), where β is the gain of the first bipolar transistor. The second current mirror, which is electrically connected to first and second emitters of the first and second bipolar transistors, sets a magnitude of an emitter bias current in the first emitter at a level proportional to (IREF₂+(N1)(IREF₁/(β+1)), where N1 is a current gain of the first current mirror. To provide a preferred level of β compensation, the magnitude of (N1)(IREF₁) is preferably set at a level equal to IREF₂. Thus, Z=1, where Z=(N1)(IREF1)/(IREF₂). These first and second current mirrors also operate to set a magnitude of an emitter bias current in the first emitter at a value proportional to (β+2)/(β+1) when Z=1.

[0011] According to still another preferred embodiment, a differential amplifier is provided that comprises first and second bipolar transistors electrically coupled together as an emitter-coupled pair and a biasing circuit that is electrically connected to first and second emitters of the first and second bipolar transistors, respectively. The biasing circuit includes first and second current sources that generate a first reference current (IREF₁) and a second reference current (IREF₂), respectively. A pair of current mirrors are also provided. A first current mirror generates a compensation current having a magnitude proportional to IREF₁. A second current mirror is electrically connected to first and second emitters of the first and second bipolar transistors, respectively, and sets a magnitude of an emitter bias current in the first emitter at a level proportional to a sum of IREF₂and a magnitude of the compensation current. The magnitude of the compensation current is preferably set at a level sufficient to achieve a magnitude of an emitter bias current in the first emitter at a value proportional to (β+Z+1)/(β+1) when combined with IREF₂.

[0012] FIG. 1 is an electrical schematic of a conventional emitter coupled pair (ECP) differential amplifier.

[0013] FIG. 2 is an electrical schematic of a conventional ECP differential amplifier that utilizes a resistor within a bipolar current mirror to provide beta compensation.

[0014] FIG. 3 is an electrical schematic of a conventional ECP differential amplifier that includes a MOS-based current mirror therein.

[0015] FIG. 4 is an electrical schematic of an ECP differential amplifier according to a preferred embodiment of the present invention.

[0016] FIG. 5 is plot of emitted coupled pair gain versus beta for an ECP differential amplifier having uncompensated gain and preferred compensated gain.

[0017] FIG. 6 is a plot of percentage gain error as a function of beta for an ECP differential having uncompensated gain and preferred compensated gain.

[0018] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.

[0019] Referring now to FIG. 4, a preferred differential amplifier 10 includes first and second bipolar transistors Q1 and Q2 electrically coupled together as an emitter-coupled pair (ECP). As illustrated, the collector of the first bipolar transistor QI is connected to an output node and to a power supply signal line Vcc by a first collector resistor R_c. Similarly, the collector of the second bipolar transistor Q2 is connected to another output node and to the power supply signal line Vcc by a second collector resistor R_c. The base electrodes of the first and second bipolar transistors Q1 and Q2 are also electrically connected to respective input nodes. As will be understood by those skilled in the art, the differential voltage gain of the differential amplifier may be expressed as VoutVin. The collector, base and emitter currents I_c, I_band I_ein the first and second bipolar transistors Q1 and Q2 are related by the following expressions:

[0020] βI_b=I_c  (2)

[0021] (β+1)I_b=I_e  (3)

[0022] where β is the current gain of the first and second bipolar transistors Q1 and Q2.

[0023] A biasing circuit 12 is also provided to establish a desired quiescent emitter current I_ein each of the first and second bipolar transistors Q1 and Q2. In particular, the biasing circuit 12 preferably sets a bias current I_biasat a level defined by the following expression:

[0024] I_bias=N2(IREF₂+(N1)IREF₁/(β+1))  (4)

[0025] where IREF₁and IREF₂are the magnitudes of the first and second reference currents provided by first and second current sources 14 and 16, and N1 and N2 are the current gains of first and second current mirrors 18 and 20, respectively, as explained more fully hereinbelow. When the value of (N1)(IREF₁) is set to a level equal to IREF₂, the above equation can be simplified to:

[0026] I_bias=2(I_e)=K(1+1/(β+1))=K(β+2)/(β+1)  (5)

[0027] where K equals (N2)(IREF₂). Substituting equation (5) into equation (1) yields an expression for the voltage gain of the preferred differential amplifier 10 which is a relatively weak function of β, even for small β:

[0028] A_v=½(R_cK/V_t)(β²+2β)/(β²+2β+1)  (6)

[0029] Referring still to the biasing circuit 12 of FIG. 4, the first current source 14 provides a constant first reference current IREF₁to a preliminary NMOS current mirror 22 having first and second NMOS transistors M1 and M2 and a gain that may be set to unity. The drain of NMOS transistor M2 is electrically connected to an emitter of a third bipolar transistor Q3 that has the same p as the first and second bipolar transistors Q1 and Q2. To establish the 1/(β+1) current compensation illustrated by equation (5), the base electrode of the third bipolar transistor Q3 can be used as a reference current sink to a first current mirror 18 which comprises PMOS transistors M3 and M4 and has a gain equal to N1. An NMOS transistor M7 is also provided and configured as a resistor to set the drain voltage of NMOS transistor M2 at a desired quiescent level.

[0030] As illustrated, the first current mirror 18 generates a compensation current having a value equal to:

[0031] (N1)IREF₁/(β+1)  (7)

[0032] This compensation current is combined with the second reference current IREF₂provided by the second current source 16 and then amplified by the second current mirror 20 to provide the bias current illustrated by equation (4).

[0033] Referring now to FIG. 5, a plot is provided of simulated gain (dB) versus beta for an ECP differential amplifier having uncompensated gain (FIG. 1) and an ECP differential amplifier having compensated gain (FIG. 4). This plot illustrates how the biasing circuit 12 of FIG. 4 can be utilized to reduce fluctuations in voltage gain when variations in beta occur in response to temperature and/or processing changes.

[0034] Selecting a value of (N1)(IREF₁) which is not equal to IREF₂may also be used advantageously to further reduce an error associated with the voltage gain of the differential amplifier over a range of β, where the error is defined as I_c(desired)−I_c(actual). In particular, equation (5) may be rewritten as:

[0035] I_bias=2(I_e)=(N2)(IREF₂)(1+N1 (IREF₁/IREF₂)/(β+1))  (8)

[0036] From equation (8), an equation for the collector current I_cmay be expressed as:

[0037] I_c=(I_e*)(β²+β(1+Z)/(β²+2β+1))  (9)

[0038] where I_e*=½ (N2)(IREF₂) and Z=N1 (IREF₁/IREF₂). Assuming an ideal condition where I_c=I_e*(when β=∞), then a percentage gain error can be defined as:

[0039] % ERROR=1−(β²+β(1+Z)/(β²+2β+1))  (10)

[0040] Referring now to FIG. 6, a plot of percentage gain error as a function of β is provided for cases where no beta compensation is provided and for cases where beta compensation is provided by establishing Z=1 and Z=2. As illustrated, establishing the quantity of 1<(N1 (IREF₁)/IREF₂)≦2 provides significant reductions in gain error relative to the uncompensated case.

[0041] In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.