Scheme for reducing leakage current in an input buffer

[0002] The present application relates to the field of electronic circuitry. In particular the present application discloses apparatus and methods for addressing leakage in CMOS environments.

[0003] A problem associated with leakage is shown in FIG. 1. FIG. 1 shows a typical CMOS inverter circuit 100. CMOS logic circuits are specified to be compatible not only for CMOS level (0 to 3.3 v) input signals but also TTL level (0.4 to 2.4 v) input signals. The TTL requirement typically causes leakage in PFET 101a. Specifically, if input node 103ahas a TTL level logic high (V_IH) input of 2.4 volts, the gate to source voltage of PFET 101ais 0.9 volts for a 3.3 volt supply node 105a. Such a voltage causes PFET 101ato turn “on”.

[0004] However, since this is an inverting circuit, a logic high input ideally turns PFET 101a“off” and NFET 102a“on” resulting in ground voltage at output node 104aand no current flow from supply node 105athrough PFET 101a.

[0005] If the TTL high input turns PFET 101a“on”, leakage current flows from supply node 105athrough PFET 101a(and most likely through NFET 102ato round). Obviously, an integrated circuit having potentially tens or hundreds of inverting or similar circuits will dramatically increase its power consumption if the leakage just described occurs. Thus, some form of addressing the leakage is necessary.

[0006] Some solutions for addressing this leakage problem boost the input voltage after its supplied at input node 103asuch that the voltage at the gate of PFET 101ais high enough to cut off PFET 101a. However, this solution is not permissible with specifications requiring high input resistance. Thus the solution is not practicable in relation to most all industry requirements.

[0007] FIG. 2 shows a more robust design for addressing the leakage problem just described. Three stages are shown in circuit 200 of FIG. 2: a buffer stage 201a, a variable supply stage 202a, and a logical detect stage 204. As shown, the buffer stage supply node 210ais coupled to the variable supply stage output 211aat net 203; the buffer stage output 212ais coupled to the output node 104band the logic detect stage input 213aat net 209; the logic detect stage output 214ais coupled to the variable supply stage input 215aat net 205 and the variable supply stage supply node 216ais coupled to supply node 105b. Input node 103bis coupled to buffer stage input 218a.

[0008] The buffer stage 201ais simply the inverter circuit 100 of FIG. 1. However, “buffer stages” may be almost any conceivable design having leakage. Variable supply stage 202amodulates the voltage or current applied to buffer stage supply node 210ain such a manner that voltage and/or current is limited when the logic detect stage 204 senses a logic low at output node 104b. A logic low at output node 104bmeans leakage is possible as input node 103bmust be high. Thus the logic detect stage cuts off the power to buffer stage 201aif leakage is possible. Buffer stage supply node 210areverts back to the supply voltage (i.e. voltage at supply node 105b) when the logic detect stage 204 senses a logic high. That is, the supply voltage returns when leakage is impossible (input node 103bis low).

[0009] Thus, the logical detect stage 204 merely detects the logic level at buffer stage output 212a.

[0010] In the example of circuit 200, variable supply stage 202ahas a switch transistor 207 and a decoupling capacitor 208. Ideally, when there is no possibility of leakage (i.e., when input node 103bis low), switch transistor 207 is on and the full supply voltage appears at the buffer stage supply node 210a. When leakage is possible (i.e., when input node 103bis high), switch transistor 207 is off leaving the decoupling capacitor 208 as the sole voltage source at the source of PFET 101b. The decoupling capacitor 208 voltage is then a function of the amount of leakage through PFET 101b, if any exists.

[0011] Problems exist, however, if one employs a logic detect stage 204. One problem is that the voltage at buffer stage supply node 210ais cut off from supply node 105beven if no actual leakage exists. The voltage is cut off if leakage is merely possible. That is, if a CMOS level high signal (approx. 3.3) is placed at input node 103bthe switch transistor 207 is cut off even though there is no risk of leakage through transistor 101b. Anytime the voltage at buffer stage supply node 210ais dropped, a corresponding reduction in circuit speed is realized. That is, at output node 104bthere is typically some capacitive loading 217. Anytime the voltage at buffer stage 201asupply node 210ais reduced, the charge/discharge time at output node 104blengthens. Thus use of a logic detect stage 204 results in slower circuit speed not only for TTL level but also CMOS level input signals at input node 103b.

[0012] A further problem involves decoupling capacitor 208 as shown and described with reference to FIG. 3. FIGS. 3a-3cshow critical voltages for cases where the high to low transition of the input voltage at input node 103bis ideal. FIGS. 3d-3fshow the same critical voltages if the input voltage transition is less than ideal. Use of circuit 200 of FIG. 2 results in improper circuit operation for the input voltage shown in FIG. 3d. Essentially circuit 200 only works for synchronous applications and not asynchronous applications.

[0013] “Synchronous” simply means some kind of clocking or other mechanism exists whereby critical voltages must make logic transitions (either high to low or low to high) within some limited time period. “Asynchronous” environments have no such limited time period. Therefore, it is possible for practically unlimited transition time periods (such as that shown in FIG. 3d) within asynchronous environments but not in synchronous environments (i.e., the transition shown in FIG. 3ais almost necessary in synchronous environments).

[0014] FIG. 3ais a schematic depiction of an ideal TTL input voltage signal. The fall time from the voltage high level (V_IH=2.4 volts) to the logic low level (V_IL=0.4 volts) is zero. Better put, the transition from logic high to logic low is instantaneous. For instantaneous transitions the source voltage of PFET transistor 101band the output node 104bvoltage are shown in FIGS. 3band 3crespectively.

[0015] As shown in FIG. 3b, while the input node 103bvoltage is at a TTL level logic high (V_IH=2.4 v), the source voltage of PFET 101bslightly less than V_IH+V_T(=2.4+0.7=3.1). This voltage results from the fact that, as discussed, switch transistor 207 is cut off by logic detect stage 204 when logic level high signals are placed input node 103b. At the time switch transistor 207 is cut off, which is shortly after the input voltage transitions from low to high (not shown in FIG. 3aor 3d), the voltage at decoupling capacitor 208 (and the source of PFET 101b) is the full supply voltage at node 105b. This causes PFET 101bto leak. The source of leakage current is decoupling capacitor 208 since transistor 207 is cut off. As PFET 101bcontinues to leak, charge is continually drawn from decoupling capacitor 208 resulting in a continual voltage drop in decoupling capacitor 208 voltage and continued drop at the source of PFET 101b. This gradual decay in decoupling capacitor 208 voltage stops at the point where PFET 101bbecomes cut off (i.e., when slightly less than the threshold voltage (V_T) appears across the gate-to-source region of PFET 101b.) The source of PFET 101bis then “stuck” at slightly less than V_IH+V_Tas no current path to ground exists from decoupling capacitor 208. This is the state shown in FIG. 3bprior to the high to low transition at t_oa.

[0016] Once there is a transition at input node 103bfrom logic high to logic low, as shown at t_oain FIGS. 3a-c, NFET 102bconverts from on to off and PFET 101bturns from off to on as there is an instantaneous gate-to-source voltage of slightly less than 3.1 volts across transistor 101bat time t_oa. With transistor 101b“on” at time t_oathe decoupling capacitor 208 voltage (3.1 volts) appears at output node 104bas shown in FIG. 3c. This enables inverter 206 of logic detect stage 204 to flip and place a logic level low signal at the variable supply stage input 215aat time t_oa+Δt where Δt is the propagation delay in logic detect stage 204. At time t_oa+Δt switch transistor 207 is turned “on” which ultimately charges up decoupling capacitor 208 to the supply voltage of supply node 105b. Thus FIGS. 3a-3cshow proper operation when the transition at input node 103bis ideal.

[0017] FIGS. 3d-3fshow circuit operation when the input voltage (V_IN) transition is less than ideal. Specifically, when there is a long fall time from logic high to logic low (t_1a−t_oa). In this case the voltage at decoupling capacitor 208 is slightly less than 3.1 volts when the input voltage at input node 103bis high. In a somewhat iterative process, the decoupling capacitor 208 voltage (i.e., source voltage of PFET 101b) gradually decays along with the input voltage as shown in FIG. 3e.

[0018] The iterative process occurs as follows: first the decoupling capacitor decays to a voltage slightly less than V_IH+V_Tby time t_oaas already discussed. Then, the input node 103bvoltage (V_IN) drops slightly to V_IH−ΔV in accordance with the gradual decay shown in FIG. 3d. Once the input voltage drops to V_IH−ΔV, the gate to source voltage of PFET 101bchanges from slightly less than V_Tto slightly more than V_T. Thus transistor 101bchanges from off to on and begins to leak charge out of decoupling capacitor 208. The leakage continues until the decoupling capacitor 208 voltage drops to slightly less than V_IH+V_T−ΔV which turns transistor 101boff. Thus by this process, the decoupling capacitor 208 voltage drops ΔV identically with the input voltage. As V_INcontinuously drops, so does the voltage at the source of transistor 101b.

[0019] Ultimately, the ramp down of the input voltage at input node 103bfalls below V_T(approximately equal to 0.7 v). At this point NFET 102bturns off and, ideally, PFET 101bturns on. However, because the source voltage of transistor 101b(i.e., the voltage across the decoupling capacitor 208) has been dragged down by the decaying input voltage there is simply no charge left in decoupling capacitor 208 to raise the output node 104bto a logic high level. Thus, inverter 206 never sees a high input and never switches transistor 207 on. Because input voltages such as those shown in FIG. 3dare conceivable within asynchronous environments solutions for the leakage problem such as those shown in FIG. 2 are simply unacceptable for asynchronous applications. Thus what is needed is an approach that operates within an asynchronous environment and/or does not limit circuit speed for CMOS level input signals.

[0020] A circuit for addressing leakage is described. The circuit may have a variable supply stage including an active load in parallel with a switch transistor where the active load and the switch transistor are coupled to a decoupling capacitor. The circuit may also have a leakage detect stage having a leak device coupled to a critical node.

[0021] An embodiment of the circuit may have a supply node; an input node; an output node; a buffer stage where the buffer stage supply node is coupled to a variable supply stage output, the buffer stage input is coupled to the input node and the buffer stage output is coupled to the output node; a leakage detect stage where the leakage detect stage supply node is coupled to the supply node and the leakage detect stage input is coupled to the input node; and a variable supply stage where the variable supply stage supply node is coupled to the supply node and the variable supply stage input is coupled to the leakage detect stage output.

[0022] Furthermore, the buffer stage may comprise an inverter circuit and the leakage detect stage may comprise a latch. The variable supply stage may comprise a switching circuit having an active load.

[0023] The leakage detect stage may have a leak device coupled to a critical node where the critical node is coupled to the leakage stage output. The leak device may be a leak transistor and the critical node may be coupled to a capacitive element where the capacitive element is the inherent capacitance associated with the metal interconnect lines of an integrated circuit. The critical node may also be coupled to a current shunt element for shunting leakage where the current shunt element is a reverse biased current balancing diode. Also, the critical node may be coupled to a discharge transistor for removing charge from the critical node.

[0024] Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description which follows below.

[0025] FIG. 1 is a depiction of a typical CMOS inverter.

[0026] FIG. 2 is a depiction of a circuit for addressing a leakage problem.

[0027] FIG. 3ais a depiction of an ideal high to low V_INtransition at input node 103bof FIG. 2.

[0028] FIG. 3bis the PFET 101bsource voltage for the input transition of FIG. 3a.

[0029] FIG. 3cis the output node 104bvoltage for the input transition of FIG. 3a.

[0030] FIG. 3dis a depiction of a non-ideal high to low input transition.

[0031] FIG. 3eis the PFET 101bsource voltage for the input transition of FIG. 3d.

[0032] FIG. 3fis the output node 104bvoltage for the input transition of FIG. 3d.

[0033] FIG. 4 is a depiction of a circuit for addressing leakage configured in accordance with the teachings presented below.

[0034] FIG. 5 is a more detailed depiction of one example of a circuit configured as shown in FIG. 4.

[0035] FIG. 6ais a depiction of a non-deal high to low input transition at input node 103dof FIG. 5.

[0036] FIG. 6bis a depiction of the PFET 101dsource voltage for the embodiment of FIG. 5 resulting from the input transition of FIG. 6a.

[0037] FIG. 6cis a depiction of the output node 104dvoltage for the embodiment of FIG. 5 resulting from the input transition of FIG. 6a.

[0038] A circuit for addressing leakage is described. The circuit may have a variable supply stage having an active load in parallel with a switch transistor where the active load and the switch transistor are coupled to a decoupling capacitor. The circuit may also have a leakage detect stage having a leak device coupled to a critical node.

[0039] One embodiment of the circuit may have a supply node; an input node; an output node; a buffer stage where the buffer stage supply node is coupled to a variable supply stage output, the buffer stage input is coupled to the input node and the buffer stage output is coupled to the output node; a leakage detect stage where the leakage detect stage supply node is coupled to the supply node and the leakage detect stage input is coupled to the input node; and a variable supply stage where the variable supply stage supply node is coupled to the supply node and the variable supply stage input is coupled to the leakage detect stage output.

[0040] Furthermore, the buffer stage may comprise an inverter circuit and the leakage detect stage may comprise a latch. The variable supply stage may comprise a switching circuit having an active load.

[0041] The leakage detect stage may have a leak device coupled to a critical node where the critical node is coupled to the leakage stage output. The leak device may be a leak transistor and the critical node may be coupled to a capacitive element where the capacitive element is the inherent capacitance associated with the metal interconnect lines of an integrated circuit. The critical node may also be coupled to a current shunt element for shunting leakage where the current shunt element is a reverse biased current balancing diode. Also, the critical node may be coupled to a discharge transistor for removing charge from the critical node.

[0042] These and other embodiments of the present invention may be realized in accordance with the following teachings and it should be evident that various modifications and changes may be made in the following teachings without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense and the invention measured only in terms of the claims.

[0043] FIG. 4 shows a general depiction of one embodiment. Circuit 400 is suitable for asynchronous applications and does not reduce speed for CMOS level inputs. As shown in FIG. 4, Circuit 400, has a buffer stage 201b, a leakage detect stage 401aand a variable supply stage 202b. The buffer stage input 218bis coupled to the input node 103cand the leakage detect stage input 403a. The leakage detect stage output 402ais coupled to the variable supply stage input 215b. The variable supply stage output 211bis coupled to the buffer stage supply node 210b. The leakage detect stage and variable supply stage supply-nodes 404, 216bare coupled to the supply node 105c. Output node 104cis coupled to buffer stage 201boutput node 212b.

[0044] In the embodiment shown in FIG. 4, buffer stage 201bis a CMOS inverter circuit. However, the inverter circuit shown in FIG. 4 is just one embodiment. The buffer stage according to this invention is any conceivable design having leakage. Leakage is simply any undesired current that can be reduced or eliminated by modulating the voltage current (or both) at the buffer stage supply node 210b.

[0045] The variable supply stage 202bis a type of switching circuit. Switching circuits modulate the voltage, current (or both) applied to the buffer stage supply node 210b. A supply node is any node used as a source for voltage and/or current. The variable supply stage 202bcould be identical to the variable supply stage 202aof FIG. 2. However, as discussed, variable supply stage 202aof FIG. 2 only works acceptably within synchronous environments. Embodiments of the variable supply stage 202bother than the specific embodiment 202aof FIG. 2 are possible. One of these other embodiments, discussed ahead is capable of use within asynchronous environments. Thus variable supply stage 202bis intended to cover embodiments for synchronous as well as asynchronous applications.

[0046] Various embodiments may have a leakage detect stage 401a. Whereas the circuit 200 of FIG. 2 controlled the variable supply stage 202bwith logic level detection, this invention may sense actual leakage within circuit 400. Thus a leakage detect stage 401ais a stage that detects actual leakage and directly or indirectly controls the variable supply stage 202baccordingly.

[0047] A leakage detect stage 401ahas the advantage of reducing the supply voltage or current at buffer stage supply node 210bif and only if actual leakage is occurring. Thus, unlike the prior art which reduces the voltage at buffer stage supply node 210bfor CMOS level inputs (which do not cause PFET 101cto leak) resulting in unnecessary degradation in speed, leakage detect stage 401aenables full speed operation for CMOS level inputs.

[0048] Of course, asynchronous applications that are insensitive to the degradation in speed for CMOS input signals may choose not to employ a leakage detect stage 401a. These applications may have an asynchronous embodiment of the variable supply stage 202b(such as the one discussed ahead) coupled to a logic detect stage 204 (referring back to FIG. 2). A logic detect stage directly or indirectly controls the variable supply stage 202bvia detection of a logic signal as opposed to actual leakage. Thus various embodiments exist having an asynchronous variable supply stage 202aand a logic detect stage (such as logic detect stage 204 of FIG. 2).

[0049] Similarly, other embodiments exist within synchronous environments sensitive to the degradation in speed for CMOS signals. These embodiments may contain leakage detect stage 401acoupled to a synchronous variable stage 202a(such as the one shown in FIG. 2).

[0050] A specific embodiment of the circuit of FIG. 4 is shown in FIG. 5. This particular embodiment is for asynchronous applications that are sensitive to speed degradation for CMOS level input signals. Thus this specific embodiment shown in FIG. 5 employs: 1) a synchronous variable supply stage 202cthat does not induce circuit performance degradation as shown back in FIGS. 3d-fand 2) a leakage detect stage 401b. As shown in FIG. 5, buffer stage input 218cis coupled to input node 103dand leakage detect stage input 403b. Leakage detect stage output 402bis coupled to variable supply stage input 215c. Variable supply stage output 211cis coupled to buffer stage supply node 210b.

[0051] Buffer stage 201cis comprised of many extraneous elements much of which is discussed later. For present purposes, buffer stage 201cis essentially an inverter circuit 526. This inverter circuit 526 includes an NFET 102dcoupled to a PFET 101d. The gate node of both transistors 102d, 101dare coupled to the buffer stage input 218c. When input node 103dis a logic high, ideally NFET 102dis on and PFET 101dis off resulting in a logic low at buffer stage output 212band output node 104d. It is this logic stage where leakage typically occurs. In this embodiment, input node 103dis also coupled to leakage detect stage input 403b.

[0052] The leakage detect stage input 403bis coupled to the totem pole arrangement 504. The totem pole arrangement 504 is a PFET transistor 501 atop NFET 502 atop “chip enable” NFET 503. Most critical to the arrangement 504 is the “leak transistor”, PFET 501. Essentially, actual leakage through leak transistor 501 is sensed by leakage detect stage 401band such detection is used to control variable control stage 202c.

[0053] Although this embodiment shows a leak transistor 501, in a more broad sense, other structures could be used. For example, a standard test cite structure or diode could be used. Thus the invention extends to “leak devices”, generally not just a leak transistor 501. A leak device is any structure intentionally formed to produce leakage or produce an “on” channel at a critical circuit state or transition during which leakage may occur. In the embodiment of FIG. 5, a leak transistor is employed because it is desirable to have leakage through the leak device if and only if PFET 101dis leaking. Thus it is desirable not only to use a leak transistor but also use a leak transistor having identical dimensions, doping profiles, etc. as PFET 101d. Thus it is preferable to use leak devices that replicate the structure or leakage that occurs within the buffer stage 201.

[0054] The leakage current through leak transistor 501, if any exists, flows through NFET 502 and chip enable transistor 503. When the logic level at input node 103dis high (for either TTL or CMOS level inputs), NFET 502 is on. Obviously, chip enable transistor 503 is also on and Power On Reset transistor 514 is off. Transistor 506 is off as discussed later. Thus all leakage current must charge the capacitive element 522 at critical node 507. As the leakage current charge the capacitive element 522, critical node 507 is responsive to the leakage according to: $\begin{array}{cc}{V}_{\mathrm{critical}\mathrm{node}}=\frac{1}{C}\int I_{\mathrm{leakage}}dt& \text{<equation 1>}\end{array}$

[0055] where C is the capacitance of the capacitive element 522, I_leakageis the leakage current and V_{critical node}is the voltage of the critical node 507.

[0056] Thus in this embodiment, the voltage at the critical node 507 rises over time as leakage current continues to flow. Referring to FIG. 5, once the critical node voltage is sufficient to turn on latch input transistor 508 the latch output node 509 is converted to a logic high. As the latch output node 509 is coupled to the leakage detect stage output node 402b, the logic high is delivered to the variable supply stage input 215c.

[0057] The critical node 507 is any node that is responsive to the leakage current and, as such, many possible critical node embodiments exist. For example, instead of employing a capacitive element, a resistive element can be used. Further still, an ammeter circuit could be employed to sense the leakage current. In such an embodiment, by definition the ammeter output is the critical node. Thus the critical node is any node that is responsive to the leakage current and is not necessarily a node through which leakage current flows.

[0058] Furthermore, the capacitive element 522 of the embodiment shown in FIG. 5 is the inherent capacitance associated with the metal interconnect lines of an integrated circuit. Furthermore, in embodiments (such as the embodiment shown in FIG. 5) having a transistor or device coupled to the critical node 507 (such as transistors 506, 508) the capacitive element 522 includes the inherent capacitance (e.g., gate, source, drain) associated with the transistor or device. Also, other embodiments such as deliberate capacitive structures may be employed as well. However, deliberate capacitive elements may slow the response time as they are relatively large structures. For typical device geometries the leakage current is only about 1-100 μA.

[0059] Continuing with an operational description of FIG. 5, the logic high at variable supply stage input node 215cturns off switch transistor 517. This ends the previously uninterrupted coupling between supply node 105dand buffer stage supply node 210b. Thus the desired action of cutting the supply voltage at the source node of PFET 101dwhen actual leakage occurs is accomplished.

[0060] At this point PFET 101dcontinues to leak while decoupling capacitor 516 sources the leakage current thereby reducing its voltage accordingly. Thus the decoupling capacitor 516 voltage drops gradually as PFET 101dcontinues to leak. Ultimately a steady state condition is reached, as shown in the first portion of time (up to t_oa) in FIG. 6b, where the decoupling capacitor 516 voltage (and PFET 101dsource node) is slightly less than the TTL level high input (at input node 103d) plus the threshold voltage (=2.4+0.7=3.1 volts). Thus, in this steady state, the source voltage of PFET 101dis slightly less than 3.1 volts and PFET 101dis cut off.

[0061] At this point, if the input voltage at input node 103dtransitions slowly from the logic high state to a logic low level (as shown in FIG. 6aand FIG. 3d) the circuit of FIG. 5 behaves differently than that shown in FIGS. 3eand 3fwhich are associated with the circuit of FIG. 2. That is, the asynchronous embodiment of the variable supply stage 202bof FIG. 4 is now described.

[0062] After time t_OC, when the input voltage begins to gradually decline, the source voltage of PFET 101dbegins to gradually decline identically to the iterative process described previously. That is, the source voltage simply follows a voltage path slightly less than V_IN+V_T. However, once the voltage of the decoupling capacitor 516 drops to a value Vcc−V_T(equal to 3.3−0.7=2.6 volts) active load transistor 518 turns on and clamps decoupling capacitor 516 and PFET 101dsource node to approximately Vcc−V_Tvolts. Thus a key difference between the synchronous variable supply stage 202aof FIG. 2 is use of an active load in parallel with the switch transistor 517. As the gate and drain of active load 518 are tied together, active load 518 has a voltage current relationship according to: $\begin{array}{cc}{V}_{\mathrm{DS}}=V_T+\sqrt{\frac{I_{\mathrm{DS}}}{\beta }}& \text{<equation 2>}\end{array}$

[0063] where V_DSis the drain/source voltage, V_Tis the threshold voltage, I_DSis the drain/source current and β is the transistor gain.

[0064] As the leakage current that continues to flow through PFET 101d(equal to I_DSof active load 518) is small, the voltage drop across active load 518 is approximately V_T.

[0065] Different embodiments exists for the asynchronous variable supply stage. That is, an asynchronous supply stage is not limited to designs having only active loads but extends instead to any device that holds the decoupling capacitor 516 voltage such that the capacitor does not track a slowly decaying input voltage as shown in FIG. 3E. Thus, clamping devices include active loads, diodes, totem pole structures or other similar limiting devices.

[0066] After decoupling capacitor 516 voltage is clamped the input voltage continues to decay (comparing FIGS. 6aand 6b). Once the input voltage drops to a value one threshold below the clamped voltage of active load 518 the PFET 101dturns permanently on (time t₃of FIG. 6a). However, even though PFET 101dis on, the input voltage is still above the threshold voltage NFET 102d. Therefore NFET 102dis still on, resulting in buffer stage output 212bcontinuing to be grounded as shown in FIG. 6c. In order to help ensure that V_sdoes not drop after t₃because 101dis on (which would pull substantial current through active load 518) it is recommended that β₅₁₈be sufficiently larger than β_102d. Once, however, the input voltage drops to a level just below the threshold voltage of NFET 102d(0.7 volts), the NFET transistor 102dturns off. This is time t₄in FIGS. 6a-6c.

[0067] Thus at time t₄NFET transistor 102dis off and PFET 101dis on. The result is the full source voltage of PFET 101dat the buffer stage output 104eas shown in FIG. 6c.At this point the problem described in relation to FIGS. 3d-3fis avoided. That is, voltage exists at the source of PFET 101dsufficient to switch any downstream logic even though the input voltage has gradually decayed.

[0068] Once the logic level of buffer stage output 212bshifts from logic low to logic high at time t₄of FIG. 6 a series of events occur. First, discharge transistor 506 turns on which removes the charge from capacitive element 522 thereby dropping the critical node 507 voltage to 0. This turns off latch input transistor 508. Also, as the buffer stage output 212bvoltage is high, latch input transistor 512 is turned on. This sets the latch output 509 to a low logic level which subsequently turns on switch transistor 517 in the variable supply stage 202c. In the transient time Δt_B, (from t₄to t₄+Δt_B, referring to FIG. 6) that it takes to flip latch 505, the voltage on the decoupling capacitor 518 may decay slightly as the current through p-channel FET 101dincreases in order to drive any capacitive load 217 that may exist at output node 104d. However, this decay may be minimized as the capacitance of capacitor 518 is increased well beyond the capacitance of capacitive load 217. Once the transient time to flip the latch has passed (Δt_B) and switch transistor 517 is turned on, decoupling capacitor 516 voltage ramps up to the full supply node 105dvoltage (3.3 volts).

[0069] A few details of the leakage detect stage 401bare discussed next. Specifically, transistors have a parasitic diode (e.g., parasitic diode 540) associated with the drain/substrate and source/substrate junctions. The effects of parasitic diode 540 are typically noticeable only when the transistor is off because the parasitic diode leakage is small (typically, 10 pA to 10 nA) compared to “on” transistor currents. When leak transistor 501 is off due to a CMOS level input at input node 103d, the parasitic diode 540 produces such a small leakage current from the supply node 105fwhich ultimately charges capacitive element 522.

[0070] Thus even for CMOS level inputs, the critical node 507 voltage increases according to equation 1. As the leakage current when leak transistor 501 is off (CMOS level high input) is much smaller than the leakage current when leak transistor 501 is on (TTL level high input), the charging rate of capacitive element 522 is much slower for parasitic diode 540 induced leakage currents. Thus in most cases the leakage current associated with parasitic diode 540 is not a problem as a logic low input appears before the critical node voltage rises substantially.

[0071] Nevertheless, it is possible (especially within asynchronous applications) a CMOS level high input signal may appear at the gate of leak transistor 501 indefinitely such that the critical node voltage rises to a level that causes latch 505 to flip incorrectly. In the embodiment of FIG. 5, reversed biased current balancing diode 513 is coupled to critical node 507 in order to shunt the parasitic diode 540 leakage current away from capacitive element 522 thereby stabilizing the critical node 507 voltage. As long as the leakage current of reversed biased current balancing diode 513 is greater than the leakage current of parasitic diode 540, capacitive element 522 cannot accumulate enough charge to flip latch 505. This is usually accomplished by simply making the surface area of reverse biased current balancing diode 513 greater than the area of parasitic diode 540.

[0072] Reversed biased current balancing diode 513 is essentially a current shunt element. Thus any device capable of shunting charge away from capacitive element 522 may be used in place of reverse biased current balancing diode 513.

[0073] As discussed, discharge transistor 506 resets critical node 507 to ground level while the input voltage is low, thus preventing voltage build up on node 507 during subsequent high level inputs. The Power on Reset (POR) node 525 is used to ground the critical node 507 (via transistor 514) and the leakage detect stage 401boutput 402b(via transistor 515) during a reset. The Chip Enable node 523 is used to ground the output node 104d(via transistor 520) and isolates the leak transistor 501 from the critical node 507 (via transistor 503) when the Chip Enable node 523 is at a logic low. Transistor network 521 is used to adjust the trip point of inverter 526.

[0074] Although only a 3.3 v supply node 105dvoltage has been discussed in the specific embodiment of FIG. 5, it is readily apparent the concepts discussed herein are not solely limited to 3.3 v supply applications. For example, the invention is easily employed within 5 v supply applications provided the device that clamps the decoupling capacitor 516 voltage sustains a larger voltage drop. That is, as shown in FIG. 6B, the clamping voltage occurs at V_s=V_cc−V_T=2.6 v which is less than 3.1 v. V_swill stabilize at approximately 3.1 v=V_IH+V_Tfor most all applications (since typically V_IH=2.4 v and V_TH=0.7 regardless of the supply voltage employed.) Thus the clamping voltage must be at 3.1 v or less. Thus for 5 v applications there must be at least a 1.9 v voltage drop. One embodiment for 5 v supply applications is a triple totem pole structure of active load devices having a voltage drop of 2.1 v (equal 3×0.7) which therefore clamps the PFET 101dat 2.9 v (which is less than or equal to 3.1 v as required).

[0075] Thus, a novel scheme for reducing current on an input buffer has been described.