Serially buffered medium translator

[0002] The present invention relates to data medium translators, in particular, local and wide area network data medium translators.

[0003] Previously, the most widely used approach for transmitting a first format data on a second format was to use the same approach as in the network hub. However, translation via the data hub port introduces significant data delays, typically in excess of 90 serial data bits, which reduces the network performance and adds to the limitations of the physical size of the network.

[0004] Such data delay and other data translation limitations experienced by hub and other prior data translation devices are, in large part, a result of internal transfer data from the incoming media serial format to an internal parallel format for buffering or processing, and back to the serial format for retransmission. The well established building blocks used in many such systems consist of an integrated circuit, e.g. part # DP83223, which provides the necessary electrical signalling and media state, while a second subsequently connected integrated circuit, e.g. part # DP83240, recovers the clock signal from the incoming signal, decodes or descrambles the NRZ, MLT3 or other cipher format encrypted signal and provides a plaintext data signal in a 4-bit parallel standard. The plaintext parallel data is then received by a buffer or processor provided by a variety of integrated circuits. For hub configurations, similar parallel data paths are provided.

[0005] As demonstrated by the widespread adherence to the parallel data format by integrated circuit and equipment designers, the limitations imposed on the data flow by the parallel format are generally accepted as unavoidable, and thus the performance of data translation equipment is only marginally improved.

[0006] The apparatus and method according to the present invention provide a serially buffered data translator including physical layer devices which provide the necessary media interfacing and clock recovery and a serial stream of encrypted data to a serial buffer, which provides frame synchronization with a minimal data bit delay, typically 5 bits. In one embodiment according to the present invention, the serial buffer comprises a National Semiconductor part no. DP83222 previously intended for serial descrambling prior to data conversion to parallel format and subsequent processing, but adapted according to the present invention to provide the serial bit output prior to retransmission in the alternate medium format.

[0007] Having recognized the desirability, and providing the apparatus and method to provide data translation according to the present invention, a total translated data delay time of 15 bits or less is achieved. When compared to the typical 4-bit serial-parallel-serial data systems data delay of at least 45 bits, the apparatus of the present invention provides a significant improvement.

[0008] These and further features of the present invention will be better understood by reading the following Detailed Description together with the Drawing, wherein

[0009] FIG. 1 is a block diagram of one embodiment of the present invention providing translation between a twisted pair and fiber optic medium;

[0010] FIG. 1A is a block diagram of the scrambler/descrambler device according to the embodiment of FIG. 1; and

[0011] FIG. 2A and FIG. 2B are a block diagrams of the respective descrambler/scrambler structures as provided by an integrated circuit used in the embodiment of FIG. 1.

[0012] The preferred embodiment 50 of the present invention as shown in FIG. 1, provides data translation from a first medium 52 via a transceiver 62, clock recovery device 66, stream cipher device 60 and second medium transceiver 64 to the second medium 54. In the present embodiment, the first exemplary medium is full or half duplex twisted pair compliant with ANSI X3T9.5 TP-PMD and IEEE 802.3 100BASE-TX Ethernet twisted pair specifications; other media are supportable according to the present invention. The second medium complies with the IEEE 802.3 100BASE-FX, FDDI fiber optic specifications; other media is supportable according to the present invention.

[0013] Data coming from the second medium to the first is translated according to the present invention via the second medium transceiver 64, second medium clock recovery device 68, stream cipher stream 60, and to the first medium 52 through the first medium transceiver 62.

[0014] The transceivers 62 and 64 typically comprise integrated circuit systems appropriate for each data medium. In the present embodiment, twisted pair medium transceivers 62 comprise on of parts no. DP 83223 of National Semiconductor, or equivalent, and fiber optic transceiver 64 comprises transceiver part no. HFBR-5103-SC by Hewlett-Packard, or equivalent, connected as known in the art to provide and receive serial electrical signals corresponding to the incoming or outgoing medium data. Typically, such circuit systems 62, 64 detect medium data signals present and provide a corresponding signal on paths 72, 74 to a link detect circuit 58. If the incoming medium signal fails or becomes unacceptably diminished in quality, the signal on the corresponding path changes. The link detect circuit then provides a 'lost synchronization' signal on path 76 to reset the stream cipher device 60 to reinitiate buffering and/or descrambling or scrambling according to the direction of the data interruption and as provided by the particular stream cipher device 60 structure implemented.

[0015] The stream cipher device 60 comprises a bidirectional descrambler/scrambler which receives, processes, and outputs data in entirely while in the 5-bit format. Although not limited thereto, the serial buffer of the present invention is economically implemented, in part, with a National Semiconductor part no. DP83222, and/or its equivalents.

[0016] The block diagram of the internal scrambler/descrambler device 60 according to one embodiment of the present invention is shown in FIG. 1A, wherein the stream cipher descrambler 100 provides the NRZ(I) decoded recovered data (received from signal path 63) to the fiber optic transceiver 64 via signal path 55 after being re-encoded (NRZ(I)) at a recovered clock rate provided over signal path 65. Similarly, the stream cipher scrambler 130 provides the NRZ(I) decoded data (received from the signal path 69) to the twisted pair transceiver 62 via signal path 53 as cipher scrambled data after being re-NRZ(I)-encoded.

[0017] The descrambler operates in either a sample mode or a hold mode according to the state of the MUX 120 as controlled by the signal provided by a register and line state monitor/hold timer 112 which detects a particular synchronizing data sequence. In the present embodiment, the IDLE line state, characterized by two sequences of 5 binary “1's” will allow data synchronization. However, the descrambler incoming data (at 102) is encrypted and received by tapped shift register 106 having an output via XOR gate 108 to be again combined with the original incoming stream via XOR 110 to provide an output, received by the register monitor/timer 112, which provides the original (unscrambled) IDLE data bit (2 groups of 5 “1” bits). When sufficient (>50, typically) idle “1” bits are received, the MUX 120 recirculates (via XOR 116), and provides an output, which when XOR combined with the incoming data by XOR gate 114, provides the descrambled data output at 122. When a loss of signal is indicated by a signal on 76, the descrambler re-enters sample mode. Other modes of synchronization are within the scope of the present invention as may be incorporated in integrated circuit for the particular medium data synchronization standard. The recovered twisted pair clock signal is received to provide the clock signals to the descrambler registers upon receipt of a particular initial frame signal. Further description of the operation of the particular descrambler (DP 83222) is provide by the 1994 National Semiconductor FDDI Data Book or equivalent, incorporated by reference. The descrambled data (plaintext) output 122 signal is re-NRZ(I) encoded and then received by the fiber optic medium transceiver 64 for transmission thereon at the rate of the data provided by the descrambled data output.

[0018] Similarly, the block diagram of the serial register 60 scrambler logic 130 is shown in FIG. 2B, wherein the fiber optic medium 54 data is received at the unscrambled data input 132 from the clock recovery device 68. The fiber optic medium recovered clock signal is received by a clock synchronization circuit 134 to provide the register clock and reset signals to the scrambler register(s) upon receipt of a frame synchronizing symbol on the received fiber optic medium data signal.

[0019] In the present embodiment, the fiber optic medium uses an NRZ (or NRZ-type) format which is presented to the input at 132 which is combined at the XOR gate 140 with a bit sequence generated by a linear feedback shift register 134 comprising a shift register 136 and XOR gate 138 connected to recirculate the XOR of bits 9 and 11. The scrambler data output 142 signal is received by the twisted pair transceiver 62 for transmission onto the twisted pair medium 52.

[0020] In the present embodiments, the descrambler 100 and scrambler 130 logic is contained within a single integrated circuit and may be independently and simultaneously operated to provide full duplex first-to-second and second-to-first media translation. Other embodiments may provide serial register 60 implementation with discrete logic and/or multiple descrambler/scrambler integrated circuits.

[0021] Alternate embodiments of the present invention provide a more direct data path from the medium (e.g. 52, 54) signals, such as directly from the medium receiver or transceiver (e.g. 62, 64).

[0022] Further modifications and substitutions made by one of ordinary skill in the art are considered within the scope of the present invention which is not to be limited except by the claims which follow.