Complementary source coupled logic

[0002] 1. Field of the Invention

[0003] The present invention relates to differential logic circuits and, more particularly, to differential logic circuits suitable for low voltage differential signaling.

[0004] 2. Description of the Related Art

[0005] Electrical circuits have used differential logic circuits for many years. Early single-ended bipolar digital logic families, such as Resistor-Transistor Logic (RTL), Diode-Transistor Logic (DTL), and Transistor-Transistor Logic (TTL), which made use of a saturating transistor inverter and large signal swing, exhibited large propagation delay time because of their saturation delay time. To overcome the saturation delay, differential logic families based on non-saturating current switches and low signal swing, such as Current Mode Logic (CML), Emitter Coupled Logic (ECL), and Positively-referenced Emitter Coupled Logic (PECL), have been widely used in bipolar integrated circuits. CML is the simplest form of differential logic in bipolar integrated circuits. The poor capacitive drive of CML was later overcome in ECL by coupling the differential output by an emitter follower.

[0006] The counterparts of CML and ECL in bipolar integrated circuits are obtainable in Complementary Metal Oxide Semiconductor (CMOS) integrated circuits, and they are referred to as Current Mode Logic (CML) and Source Coupled Logic (SCL), respectively.

[0007] FIG. 1 is a schematic diagram of a conventional n-type SCL circuit 100. The n-type SCL circuit 100 is composed of n-type CML differential pair and two n-type single-ended source followers. The n-type CML differential pair includes transistors 102 and 104, load transistors 106 and 108, and a current source (Is). The transistors 102 and 104 are coupled to a supply voltage (V_DD) through the load transistors 106 and 108. The transistors 102 and 104 receive a differential input (IN+ and IN−). The load transistors 106 and 108 are biased by a bias voltage signal. The current source (Is) 110 couples the commonly connected sources of the transistors 102 and 104 to ground. A first of the n-type single-ended source followers includes a transistor 112 and a current source (Is) 114, and a second of the n-type single-ended source followers includes a transistor 116 and a current source (Is) 118. Similarly, the p-type SCL is composed of a p-type CML differential pair and two p-type source followers.

[0008] Both CML and SCL operate with low signal swing as required for high-speed operation. The SCL may potentially operate at higher speed since the source followers in SCL isolate the capacitive loading from the drains of CML differential pair. Furthermore the SCL is well suited for driving large impedance loads because of its low output impedance.

[0009] FIG. 2 is a schematic diagram of a low-voltage variable-delay gain stage circuit 200 that is known in the art. The low-voltage variable-delay gain stage circuit 200 is a Complementary Metal Oxide Semiconductor (CMOS) device that can operate at lower operating voltages than could earlier designs due to the PMOS load biased by NMOS source follower and the folded PMOS control stage to avoid stacking.

[0010] The low-voltage variable-delay gain stage circuit 200 uses NMOS source followers 202 and 204 which bias load transistors 206 and 208 (p-type transistors), respectively. Further, the low-voltage variable-delay gain stage 200 includes a differential pair including n-type transistors 210 and 212. The transistors 210 and 212 form a differential pair and have their sources commonly coupled to ground through a current source 218. The outputs for the low-voltage variable-delay gain stage 200 are obtained from the drains of the transistors 210 and 212 of the differential pair. The low-voltage variable-delay gain stage 200 also includes gain-control circuitry 220. Here, the cross-coupled transistors 222 and 224 biased by current source 226 introduce a negative resistance equal to −2/g_m, where g_mdenotes the average transconductance of transistors 222 and 224. This negative resistance partially cancels the resistance at the drain of the load transistors 206 and 208, increasing the effective output impedance and hence the delay. Transistors 228 and 230 receive a control voltage and change the amount of current flowing through the transistors 210 and 212 versus transistors 222 and 224.

[0011] The low-voltage variable-delay gain stage 200 uses PMOS loads (i.e., p-type load transistors 206 and 208) biased by NMOS source follower (i.e., n-type transistor 202 and 204). The advantage of the use of the NMOS source followers to bias the PMOS loads, as opposed to a constant reference voltage being used to bias the loads, is that an extended constant R_onis maintained across the load transistors 206 and 208 in the triode region. The outputs are obtained from the drains of the differential pair (210 and 212), and thus, the logic topology of the low-voltage variable-delay gain stage 200 is CML.

[0012] The CML and SCL topologies are applicable to both intra-chip building blocks and inter-chip interface. When CML and SCL are used for interface, they require impedance matched loads terminated to a fixed voltage. More recently, the Low Voltage Differential Signaling (LVDS) standard has been developed to provide yet another form of differential interface. LVDS requires impedance-matched loads only, and does not require a fixed termination voltage. Thus, LVDS can be used between a transmitter and a receiver that have ground shift. However, the ground shift imposes that the receiver should accommodate the input common mode variation resulting from it. The current LVDS standard specifies that the DC level of the receiver output is at 1.2V and ground shift up to ±1.2V is allowed, which impose minimum 0 to 2.4V of input common mode range at the receiver. This common mode range is almost equivalent to rail-to-rail in 2.5V supply.

[0013] The differential pairs in CML or SCL have limited input common-mode range. The n-type differential pair operates from V_TNto V_DDand the p-type differential pair operates from V_SSto V_DD−V_TP, where V_DDand V_SSare supply voltage voltages and V_TNand V_TPare threshold voltages of the n-type and p-type transistors, respectively. In order to accommodate the rail-to-rail input common mode range, both n-type and p-type differential pairs are often used and the output signals of both pairs should be combined.

[0014] The conventional approach to combine the outputs of an n-type and a p-type differential pair is to mirror the currents of one type and add the current to a summing node. This approach is applicable only to CML, but not to SCL without loss of bandwidth. Thus, there is a need for ways to combine the outputs of n-type and p-type SCL pairs.

[0015] Broadly speaking, the invention relates to a Complementary Source Coupled Logic (CSCL) topology suitable for low voltage differential signaling. The Complementary Source Coupled Logic topology is referred to as Complementary Source Coupled Logic as it contains both n-type and p-type Source Coupled Logic (SCL) topology. The CSCL topology can be used to form any differential Boolean logic design, but is particularly well suited for buffering small signal differential signals with large input common-mode range.

[0016] The invention can be implemented in numerous ways, including as a computer system, an apparatus, and a method. Several embodiments of the invention are discussed below.

[0017] As a differential circuit having a high bandwidth over a rail-to-rail common mode range, one embodiment of the invention includes: a first differential pair receiving first and second differential inputs; a first pair of active loads coupled between said first differential pair and a first power source; a first current source coupled between the first differential pair and a second power source; a second differential pair receiving the first and second differential inputs; a second pair of active loads coupled between the second differential pair and the second power source; a second current source coupled between the second differential pair and the first power source; a first complementary source follower coupled to a first node between the first of the first pair of the active loads and the first differential pair and coupled to a first node between the a first of the second pair of the active loads and the second differential pair; and a second complementary source follower coupled to a second node between the second of the first pair of the active loads and the first differential pair and coupled to a second node between the second of the second pair of the active loads and the second differential pair.

[0018] As a low voltage differential signaling circuit using complementary source coupled logic, the low voltage differential signaling circuit comprising: an n-type differential pair receiving first and second differential inputs; a first pair of active loads coupled between the n-type differential pair and a first power source; a first current source coupled between the n-type differential pair and a second power source; a p-type differential pair receiving the first and second differential inputs; a second pair of active loads coupled between the p-type differential pair and the second power source; a second current source coupled between the second differential pair and the first power source; a first complementary source follower coupled to a first node between the first of the first pair of the active loads and the n-type differential pair and coupled to a first node between the first of the second pair of the active loads and the p-type differential pair, the first source follower producing a first differential output at a first output node; and a second complementary source follower coupled to a second node between the second of the first pair of the active loads and the n-type differential pair and coupled to a second node between the second of the second pair of the active loads and the p-type differential pair, the second complementary source follower producing a second differential output at a second output node.

[0019] As a low voltage differential signaling circuit including a first type differential pair and a pair of first type source followers, wherein according to one embodiment of the invention, the improvement includes a second type differential pair, the second type being complementary to the first type, and the pair of source followers are complementary source followers that are shared by the pair of complementary type differential pairs.

[0020] The invention has numerous advantages. One advantage of the invention is extended rail-to-rail input common mode range. Another advantage of the invention is that very high frequency (or high bandwidth) operation is obtainable. Still another advantage of the invention is that it yields good drive capabilities.

[0021] Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.

[0022] The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and in which:

[0023] FIG. 1 is a schematic diagram of a conventional Source Coupled Logic (SCL) circuit;

[0024] FIG. 2 is a schematic diagram of a low-voltage variable-delay gain stage circuit that is known in the art;

[0025] FIG. 3 is a block diagram of a complementary source coupled logic circuit according to one embodiment of the invention; and

[0026] FIG. 4 is a schematic diagram of a complementary source coupled logic circuit according to one embodiment of the invention.

[0027] The invention relates to a complementary source coupled logic topology suitable for high speed low voltage differential signaling. The topology is referred to as complementary source coupled logic as it contains both n-type and p-type source coupled logic. The two different types of differential pairs detect input signal from rail-to-rail and provides both n-type and p-type outputs. The complementary source followers then combine and buffer the outputs of the complementary differential pairs.

[0028] Conventionally complementary designs, when combining p-type and n-type in a complementary fashion, tend to use current mirrors and current summers (i.e., wired OR) to mirror currents to the opposite type devices. Unfortunately, such conventional approaches are slow and thus not suitable for high-speed operation. The invention offers a gate-efficient, high-speed (high-bandwidth) logic topology. The invention uses a complementary source follower at each differential output. The complementary source followers provide low output impedance and good drive capability without extra transistors. Overall, the logic topology can provide low gain and very high bandwidth together with a rail-to-rail input common mode range.

[0029] Embodiments of the invention are discussed below with reference to FIGS. 3-4. However, those skilled in the art will readily appreciate the detailed description given herein with respect to these figures is for explanatory purposes as the invention extends beyond these limited embodiments.

[0030] FIG. 3 is a block diagram of a complementary source coupled logic circuit 300 according to one embodiment of the invention. The complementary source coupled logic circuit 300 includes an n-type differential pair 302 that receives differential inputs (IN+ and IN−) at input terminals. The n-type differential pair 302 is coupled to ground through a current source 304. The n-type differential pair 302 also has a first output node 306 and a second output node 308. The first output node 306 is coupled to supply voltage (V_DD) through an active load 310, and the second output node 308 is coupled to the supply voltage (V_DD) though an active load 312.

[0031] The complementary source coupled logic circuit 300 also includes a p-type differential pair 314. The p-type differential pair 314 also receive the differential inputs (IN+ and IN−) to its input terminals as does the n-type differential pair 302. The p-type differential pair 314 is coupled to the supply voltage (V_DD) through a current source 316. The p-type differential pair 314 also has a first output node 318 and a second output node 320. The first output node 318 is coupled to ground through an active load 322, and the second output node 320 is coupled to ground through an active load 324.

[0032] In addition, the complementary source coupled logic circuit 300 also includes a first complementary source follower 326 and a second complementary source follower 328. The first complementary source follower 326 is coupled to the first output node 306 of the n-type differential pair 302 and to the first output node 318 of the p-type differential pair 314. The first complementary source follower 326 outputs a first differential output (OUT+). The second complementary source follower 328 is coupled to the second output node 308 of the n-type differential pair 302 and to the second output node 320 of the p-type differential pair 314. The second complementary source follower 328 outputs a second differential output (OUT−).

[0033] Further, the complementary source coupled logic circuitry 300 provides a feedback path 330 from the output of the first complementary source follower 326 to the active load 310 associated with the n-type differential pair 302 as well as the active load 322 associated with p-type differential pair 314. Similarly, the complementary source coupled logic circuitry 300 also provides a feedback path 332 from the output of the second complementary source follower 328 to the active load 312 associated with p-type differential pair 314. The feedback provided by the feedback paths 330 and 332 serve to bias the active loads 310, 312, 322 and 324 in their triode operational region where the impedance is low and R_onis approximately constant. The triode operational region is the region of operation of a transistor where the drain current I_DSchanges approximately linearly with respect to the drain voltage V_DS. At the edge of triode region and the beginning of saturation region, the resistance rapidly changes. Thus, the feedback operates to gradually change the gate voltage V_GSso that the triode operational region is extended and thus R_onis maintained approximately constant. With n-type active loads, the feedback gradually increases V_GS, and with p-type active loads, the feedback gradually decreases V_GS. As a result, the n-type pair 302 and the p-type pair 314 achieve low-gain yet high-bandwidth, and the output nodes 308 and 306 of the n-type differential pair 302 and the outputs nodes 318 and 320 of the p-type differential pair 314 achieve low signal swings.

[0034] Moreover, the outputs of the two differential pairs 302 and 314 are combined directly by the two complementary source followers 326 and 328. A complementary source follower is referred to as a complementary source follower since it is composed of an n-type source follower and a p-type source follower. In complementary source followers, the sources of the two different types of source followers are connected together and one type of source follower acts as the current source for the other type of source follower. Conventionally, a source follower includes a transistor and a current source, where the current source is either a passive resistor or a transistor current source with DC-biased gate and high output impedance at the drain. In contrast, according to this embodiment of the invention, when one of the source followers in the complementary source follower is used as current source, the gate is biased by the output of the differential pair of the same type and the output current is available at the source with low impedance. Thus, when one of the source followers acts as a current source, it does not act as efficiently as conventional current sources and thus, results in reduced gain at the output of the source follower. However, low gain is desired in high-speed operation, since it reduces the swing and increases the bandwidth. Furthermore, complementary source followers offer an efficient method of combining the outputs of two differential pairs directly into a low impedance node without mirroring and summing currents.

[0035] Outputs from the complementary source coupled logic circuit 300 are taken from low impedance nodes of the first and second complementary source followers 326 and 328. Hence, the resulting complementary outputs produced by the complementary source coupled logic circuit 300 have low gain, high bandwidth and good drive capabilities. The complementary source coupled logic circuit is also efficient in that other additional circuitry is not need to bias the active loads or the current sources.

[0036] FIG. 4 is a schematic diagram of a complementary source coupled logic circuit 400 according to one embodiment of the invention. The complementary source coupled logic 400 is, for example, a more detailed embodiment of the complementary source coupled logic 300 illustrated in FIG. 3. In this embodiment, the complementary source coupled logic 400 is a complementary metal oxide semiconductor (CMOS) device. The complementary source coupled logic circuit 400 offers high-speed operation, as well as rail-to-rail input common mode range. Still further, the complementary source coupled logic circuit 400 provides low impedance from complementary source followers.

[0037] The complementary source coupled logic circuit 400 includes transistors 402 and 404 which have their source terminals commonly coupled to ground through current source 406. The transistors 402 and 404 form a first differential pair. In this embodiment, the transistors are n-type transistors and thus the first differential pair can be classified as an n-type differential pair. The various transistors of the complementary source coupled logic circuit 400, including the transistors 402 and 404, are assumed to be Field Effect Transistors (FETs) with each having a drain terminal, a gate terminal, and a source terminal.

[0038] The drain terminal of the transistor 402 is coupled to a node 408 and the drain terminal of the transistor 404 is coupled to a node 410. The nodes 408 and 410 can be considered output nodes or output terminals of the first differential pair. The complementary source coupled logic circuit 400 also includes transistors 412 and 414 that serve as active loads for the first differential pair. More particularly, the transistor 412 is coupled between a supply voltage (or power supply) (V_DD) and the node 408. The transistor 414 is coupled between the supply voltage (V_DD) and the node 410.

[0039] The complementary source coupled logic circuit 400 also includes transistor 416 and 418 that together form a second differential pair. The source terminals of the transistor 416 and 418 are commonly coupled to the supply voltage (V_DD) through a current source 420. The transistors 416 and 418 form a second differential pair. In this embodiment, the transistors are p-type transistors and thus the second differential pair can be classified as a p-type differential pair.

[0040] The drain terminal of the transistor 416 is coupled to a node 422 and the drain terminal of the transistor 418 is coupled to a node 424. The nodes 422 and 424 can be considered output nodes or output terminals of the second differential pair. The complementary source coupled logic circuit 400 also includes transistor 426 and 428 that serve as active loads for the second differential pair. More particularly, the transistor 426 is coupled between ground and node 422. The transistor 414 is coupled between ground and the node 424.

[0041] The complementary source coupled logic circuit 400 also included a first complementary source follower consisting of transistor 430 and 432. The first complementary source follower is complementary because each of the transistors 430 and 432 is of a different type. In this embodiment, the transistor 430 is an n-type transistor and the transistor 432 is a p-type transistor. More particularly, the transistor 430 of the first complementary source follower has a drain terminal connected to a supply voltage (V_DD), a gate terminal connected to the node 408, and a source terminal connected to a first differential output (OUT+) at output node 434. The transistor 432 has a source terminal connected to the output node 434, a gate terminal connected to node 422, and a drain terminal connected to ground.

[0042] In addition, the complementary source coupled logic circuit 400 includes a second complementary source follower consisting of transistor 438 and 440. The second complementary source follower is complementary because each of the transistors 438 and 440 is of a different type. In this embodiment, the transistor 438 is an n-type transistor and the transistor 440 is a p-type transistor. More particularly, the transistor 438 of the first complementary source follower has a drain terminal connected to the supply voltage (V_DD), a gate terminal connected to the node 410, and a source terminal connected to a second differential output (OUT−) at output node 442. The transistor 440 has a source terminal connected to the output node 442, a gate terminal connected to node 424, and a drain terminal connected to ground.

[0043] Further, to provide feedback from the output node 434 to the transistors 412 and 426 serving as active loads for the first differential pair, a feedback link 436 is provided. Specifically, the feedback link 436 operates to bias the transistors 412 and 426 by supplying a feedback signal to the gate terminals of the transistors 412 and 426 via the feedback link 436. The biasing of the transistors 412 and 426 serves to operate the transistors 412 and 426 in the triode region which improves voltage swing by maintaining the impedance of the active loads (transistors 412 and 426) low. Here, the transistor 430 of the first complementary source follower acts as a current source for the transistor 432, and the transistor 432 of the first complementary source follower acts as the current source for the transistor 430. Accordingly, the first complementary source follower is shared by one side of both the first and second differential pairs.

[0044] Similarly, to provide feedback from the output node 442 to the transistors 414 and 428 serving as active loads for the first differential pair, a feedback link 444 is provided. Specifically, the feedback link 444 operates to bias the transistors 414 and 428 by supplying a feedback signal to the gate terminals of the transistors 414 and 428 via the feedback link 444. The biasing of the transistors 414 and 428 serves to operate the transistors 414 and 429 in the triode region which improves voltage swing by maintaining the impedance of the active loads (transistors 414 and 428) low. Here, the transistor 438 of the first complementary source follower acts as a current source for the transistor 440, and the transistor 440 of the first complementary source follower acts as the current source for the transistor 438. Accordingly, the first complementary source follower is shared by one side of both the first and second differential pairs.

[0045] The SCL circuit enables a wide variety of high-speed signaling. The SCL is suitable for differential logic designs including Boolean operations (e.g., AND, OR, XOR), selectors, or multiplexers. The SCL is also suitable for buffers using low-swing high-speed differential signals.

[0046] Conventional SCL circuits have limited input common-mode range. The input common-mode range of an n-type SCL circuit is from (V_SS+V_TN) to V_DDand the input common-mode range of a p-type SCL circuit is from V_SSto (V_DD−V_TP), where the threshold voltages V_TNor V_TPare approximately 0.6 Volts. However, the limited input common-mode range of SCL is extended to rail-to-rail using complementary source followers in CSCL. According to the invention, the input common-mode of CSCL can extend from V_SSto V_DD.

[0047] Furthermore, CSCL can achieve extended common-mode while maintaining the bandwidth of SCL. The complementary source coupled logic circuit 400 shown in FIG. 4 can, for example, support a signal bandwidth of 5 Giga Hertz (GHz) and a data rate in excess of 5 Giga bits per second (Gbps) in standard 0.25 um CMOS process. In addition, the CSCL circuits are scalable with process technology. The CSCL circuits can, for example, be implemented in a 0.18, 0.25, or 0.35 um CMOS process.

[0048] The CSCL circuit according to invention is particularly well suited to buffer the low-swing high-speed signals with large input common-mode variation, e.g., as LVDS input receivers which can accommodate rail-to-rail input common-mode variation.

[0049] The invention has numerous advantages. One advantage of the invention is the rail-to-rail input common-mode range, which is required by LVDS standard. Another advantage of the invention is that very high frequency (or high-bandwidth) operation is obtainable. Still another advantage of the invention is that it yields good drive capabilities.

[0050] The many features and advantages of the present invention are apparent from the written description and, thus, is intended by the appended claims to cover all such features and advantages of the invention. Further, since numerous modification and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation as illustrated and described. Hence, all suitable modifications and equivalents may be resorted to as falling within the scope of the invention.